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ARM: GIC: remove direct use of gic_raise_softirq

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In preparation of moving gic code to drivers/irqchip, remove the direct
platform dependencies on gic_raise_softirq. Move the setup of
smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask
function to trigger wake-up IPIs.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: David Brown <davidb@codeaurora.org>
Cc: Daniel Walker <dwalker@fifo99.com>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Rob Herring 2012-11-26 15:05:48 -06:00
parent 428fef8ad8
commit b1cffebf10
18 changed files with 33 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
arch/arm/common/gic.c
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@ -617,6 +617,27 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
}
#endif
#ifdef CONFIG_SMP
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
int cpu;
unsigned long map = 0;
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
map |= 1 << cpu_logical_map(cpu);
/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
dsb();
/* this always happens on GIC0 */
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
}
#endif
static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hw)
{
@ -743,6 +764,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
if (WARN_ON(!gic->domain))
return;
#ifdef CONFIG_SMP
set_smp_cross_call(gic_raise_softirq);
#endif
gic_chip.flags |= gic_arch_extn.flags;
gic_dist_init(gic);
gic_cpu_init(gic);
@ -756,27 +780,6 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)
gic_cpu_init(&gic_data[gic_nr]);
}
#ifdef CONFIG_SMP
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
{
int cpu;
unsigned long map = 0;
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
map |= gic_cpu_map[cpu];
/*
* Ensure that stores to Normal memory are visible to the
* other CPUs before issuing the IPI.
*/
dsb();
/* this always happens on GIC0 */
writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
}
#endif
#ifdef CONFIG_OF
static int gic_cnt __initdata = 0;

1
arch/arm/include/asm/hardware/gic.h
View File

@ -40,7 +40,6 @@ int gic_of_init(struct device_node *node, struct device_node *parent);
void gic_secondary_init(unsigned int);
void gic_handle_irq(struct pt_regs *regs);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
static inline void gic_init(unsigned int nr, int start,
void __iomem *dist , void __iomem *cpu)

3
arch/arm/kernel/smp.c
View File

@ -416,7 +416,8 @@ static void (*smp_cross_call)(const struct cpumask *, unsigned int);
void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
{
smp_cross_call = fn;
if (!smp_cross_call)
smp_cross_call = fn;
}
void arch_send_call_function_ipi_mask(const struct cpumask *mask)

4
arch/arm/mach-exynos/platsmp.c
View File

@ -149,7 +149,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
__raw_writel(virt_to_phys(exynos4_secondary_startup),
cpu_boot_reg(phys_cpu));
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
break;
@ -190,8 +190,6 @@ static void __init exynos_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)

4
arch/arm/mach-highbank/platsmp.c
View File

@ -33,7 +33,7 @@ static void __cpuinit highbank_secondary_init(unsigned int cpu)
static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
highbank_set_cpu_jump(cpu, secondary_startup);
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
@ -56,8 +56,6 @@ static void __init highbank_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-imx/platsmp.c
View File

@ -71,8 +71,6 @@ static void __init imx_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
void imx_smp_prepare(void)

4
arch/arm/mach-msm/platsmp.c
View File

@ -115,7 +115,7 @@ static int __cpuinit msm_boot_secondary(unsigned int cpu, struct task_struct *id
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@ -153,8 +153,6 @@ static void __init msm_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init msm_smp_prepare_cpus(unsigned int max_cpus)

4
arch/arm/mach-omap2/omap-smp.c
View File

@ -157,7 +157,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
booted = true;
}
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
/*
* Now the secondary core is starting up let it run its
@ -231,8 +231,6 @@ static void __init omap4_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)

3
arch/arm/mach-realview/platsmp.c
View File

@ -14,7 +14,6 @@
#include <linux/io.h>
#include <mach/hardware.h>
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
@ -59,8 +58,6 @@ static void __init realview_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init realview_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-shmobile/platsmp.c
View File

@ -26,6 +26,4 @@ void __init shmobile_smp_init_cpus(unsigned int ncores)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}

2
arch/arm/mach-shmobile/smp-emev2.c
View File

@ -100,7 +100,7 @@ static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}

2
arch/arm/mach-socfpga/platsmp.c
View File

@ -83,8 +83,6 @@ static void __init socfpga_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-spear13xx/platsmp.c
View File

@ -104,8 +104,6 @@ static void __init spear13xx_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init spear13xx_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-tegra/platsmp.c
View File

@ -159,8 +159,6 @@ static void __init tegra_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)

4
arch/arm/mach-ux500/platsmp.c
View File

@ -91,7 +91,7 @@ static int __cpuinit ux500_boot_secondary(unsigned int cpu, struct task_struct *
*/
write_pen_release(cpu_logical_map(cpu));
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@ -155,8 +155,6 @@ static void __init ux500_smp_init_cpus(void)
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/mach-vexpress/ct-ca9x4.c
View File

@ -182,8 +182,6 @@ static void __init ct_ca9x4_init_cpu_map(void)
for (i = 0; i < ncores; ++i)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init ct_ca9x4_smp_enable(unsigned int max_cpus)

2
arch/arm/mach-vexpress/platsmp.c
View File

@ -128,8 +128,6 @@ static void __init vexpress_dt_smp_init_cpus(void)
for (i = 0; i < ncores; ++i)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)

2
arch/arm/plat-versatile/platsmp.c
View File

@ -79,7 +79,7 @@ int __cpuinit versatile_boot_secondary(unsigned int cpu, struct task_struct *idl
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
gic_raise_softirq(cpumask_of(cpu), 0);
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {