forked from luck/tmp_suning_uos_patched
Renesas ARM Based SoC PM Domain Updates for v4.3
* Make rcar_sysc_ch const for r8a779[09] SoCs * Get rid of on_off_fn() function pointer * Use BIT() macro instead of open coding * Make struct rcar_sysc_ch * parameters const * Break infinite loop * Shrink rcar_sysc_ch size * Improve documentation -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVn2fOAAoJENfPZGlqN0++MSUQAKx3FN6a+M3rqaDTLNJd8/Lt fkkBIkCrdBSmYpM5xIKtBYy/Eb7Z3DN2hwB2gX29uL+ARjqiEos5ENDqlyG4fHBl vPgH+1pGHsWp7LrIV1qUT0jqax9rx89YUjkaIl7Swn9eug3bpDOkt5D6WPfYViu0 BR5PuUaEQAlNfOuKxrKGC2e9gsmgXewPMcu2x0W5gOPKIRf397kXDh0q83LKuWa1 TsnYBOMjzughhACppu+MErmf8VkUPYO+jq7aWWDytRyHWk/ieycsVYb6PQ0ssYlr x2YGiSFyOYl9OsdCMpRnq6BSKEPVrL4AZggd02+ep+bxuI0TPK2+fX1o+eFmnM5T C+fiEqV85X/iaXMuicFYpy4KcjwlHHyE1Qxt/UbN9Ff2VsWxF8GPXpO7HWeKHzYd f4kInzIyXvfeQWaq9zxV/UIZ2e+qOjDpxNiyFGNzY95s4wY2Yj9EHy27c8X3NE59 RXZCWDETpTTOGFHh6Txm2ToY7jv6I9W8s06Ia3eGAcpRbjr7iy5eo6aJQrfDsxI4 eEa59d7WxZcgpI96ZDYlSeyK7X3AdMqc2wE6x7Rz6qM2veDHqgenEbdSRBcb/hBn gkd2xS+1ONPrmWplkU56hcKjEFLc8gjIQVJMDYmNTK3PWuIHVJfnd5mbM8BKQJbH vdq871dNJRgbWsYXg419 =h3Um -----END PGP SIGNATURE----- Merge tag 'renesas-pm-domain-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup Merge "Renesas ARM Based SoC PM Domain Updates for v4.3" from Simon Horman: * Make rcar_sysc_ch const for r8a779[09] SoCs * Get rid of on_off_fn() function pointer * Use BIT() macro instead of open coding * Make struct rcar_sysc_ch * parameters const * Break infinite loop * Shrink rcar_sysc_ch size * Improve documentation * tag 'renesas-pm-domain-for-v4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7790: Make struct rcar_sysc_ch const ARM: shmobile: r8a7779: Make struct rcar_sysc_ch const ARM: shmobile: R-Car: Get rid of on_off_fn() function pointer ARM: shmobile: R-Car: Use BIT() macro instead of open coding ARM: shmobile: R-Car: Make struct rcar_sysc_ch * parameters const ARM: shmobile: R-Car: Break infinite loop ARM: shmobile: R-Car: Shrink rcar_sysc_ch size ARM: shmobile: R-Car: Improve documentation Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
b3f81739ab
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@ -35,7 +35,8 @@ struct r8a7779_pm_domain {
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struct rcar_sysc_ch ch;
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};
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static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
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static inline
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const struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d)
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{
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return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
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}
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@ -15,32 +15,58 @@
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#include <asm/io.h>
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#include "pm-rcar.h"
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/* SYSC */
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#define SYSCSR 0x00
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#define SYSCISR 0x04
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#define SYSCISCR 0x08
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/* SYSC Common */
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#define SYSCSR 0x00 /* SYSC Status Register */
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#define SYSCISR 0x04 /* Interrupt Status Register */
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#define SYSCISCR 0x08 /* Interrupt Status Clear Register */
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#define SYSCIER 0x0c /* Interrupt Enable Register */
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#define SYSCIMR 0x10 /* Interrupt Mask Register */
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#define PWRSR_OFFS 0x00
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#define PWROFFCR_OFFS 0x04
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#define PWRONCR_OFFS 0x0c
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#define PWRER_OFFS 0x14
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/* SYSC Status Register */
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#define SYSCSR_PONENB 1 /* Ready for power resume requests */
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#define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
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#define SYSCSR_RETRIES 100
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#define SYSCSR_DELAY_US 1
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/*
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* Power Control Register Offsets inside the register block for each domain
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* Note: The "CR" registers for ARM cores exist on H1 only
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* Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
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*/
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#define PWRSR_OFFS 0x00 /* Power Status Register */
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#define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
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#define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
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#define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
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#define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
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#define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
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#define SYSCISR_RETRIES 1000
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#define SYSCISR_DELAY_US 1
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#define SYSCSR_RETRIES 100
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#define SYSCSR_DELAY_US 1
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#define PWRER_RETRIES 100
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#define PWRER_DELAY_US 1
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#define SYSCISR_RETRIES 1000
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#define SYSCISR_DELAY_US 1
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static void __iomem *rcar_sysc_base;
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static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
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static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch,
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int sr_bit, int reg_offs)
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static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
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{
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unsigned int sr_bit, reg_offs;
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int k;
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if (on) {
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sr_bit = SYSCSR_PONENB;
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reg_offs = PWRONCR_OFFS;
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} else {
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sr_bit = SYSCSR_POFFENB;
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reg_offs = PWROFFCR_OFFS;
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}
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/* Wait until SYSC is ready to accept a power request */
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for (k = 0; k < SYSCSR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCSR) & (1 << sr_bit))
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if (ioread32(rcar_sysc_base + SYSCSR) & BIT(sr_bit))
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break;
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udelay(SYSCSR_DELAY_US);
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}
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@ -48,27 +74,17 @@ static int rcar_sysc_pwr_on_off(struct rcar_sysc_ch *sysc_ch,
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if (k == SYSCSR_RETRIES)
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return -EAGAIN;
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iowrite32(1 << sysc_ch->chan_bit,
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/* Submit power shutoff or power resume request */
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iowrite32(BIT(sysc_ch->chan_bit),
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rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
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return 0;
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}
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static int rcar_sysc_pwr_off(struct rcar_sysc_ch *sysc_ch)
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static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
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{
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return rcar_sysc_pwr_on_off(sysc_ch, 0, PWROFFCR_OFFS);
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}
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static int rcar_sysc_pwr_on(struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_pwr_on_off(sysc_ch, 1, PWRONCR_OFFS);
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}
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static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
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int (*on_off_fn)(struct rcar_sysc_ch *))
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{
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unsigned int isr_mask = 1 << sysc_ch->isr_bit;
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unsigned int chan_mask = 1 << sysc_ch->chan_bit;
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unsigned int isr_mask = BIT(sysc_ch->isr_bit);
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unsigned int chan_mask = BIT(sysc_ch->chan_bit);
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unsigned int status;
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unsigned long flags;
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int ret = 0;
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@ -78,15 +94,26 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
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iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
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do {
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ret = on_off_fn(sysc_ch);
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/* Submit power shutoff or resume request until it was accepted */
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for (k = 0; k < PWRER_RETRIES; k++) {
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ret = rcar_sysc_pwr_on_off(sysc_ch, on);
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if (ret)
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goto out;
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status = ioread32(rcar_sysc_base +
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sysc_ch->chan_offs + PWRER_OFFS);
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} while (status & chan_mask);
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if (!(status & chan_mask))
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break;
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udelay(PWRER_DELAY_US);
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}
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if (k == PWRER_RETRIES) {
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ret = -EIO;
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goto out;
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}
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/* Wait until the power shutoff or resume request has completed * */
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for (k = 0; k < SYSCISR_RETRIES; k++) {
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if (ioread32(rcar_sysc_base + SYSCISR) & isr_mask)
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break;
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@ -106,22 +133,22 @@ static int rcar_sysc_update(struct rcar_sysc_ch *sysc_ch,
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return ret;
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}
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int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch)
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int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_off);
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return rcar_sysc_power(sysc_ch, false);
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}
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int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch)
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int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch)
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{
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return rcar_sysc_update(sysc_ch, rcar_sysc_pwr_on);
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return rcar_sysc_power(sysc_ch, true);
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}
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bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch)
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bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
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{
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unsigned int st;
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st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
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if (st & (1 << sysc_ch->chan_bit))
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if (st & BIT(sysc_ch->chan_bit))
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return true;
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return false;
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@ -2,14 +2,14 @@
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#define PM_RCAR_H
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struct rcar_sysc_ch {
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unsigned long chan_offs;
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unsigned int chan_bit;
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unsigned int isr_bit;
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u16 chan_offs;
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u8 chan_bit;
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u8 isr_bit;
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};
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int rcar_sysc_power_down(struct rcar_sysc_ch *sysc_ch);
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int rcar_sysc_power_up(struct rcar_sysc_ch *sysc_ch);
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bool rcar_sysc_power_is_off(struct rcar_sysc_ch *sysc_ch);
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int rcar_sysc_power_down(const struct rcar_sysc_ch *sysc_ch);
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int rcar_sysc_power_up(const struct rcar_sysc_ch *sysc_ch);
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bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch);
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void __iomem *rcar_sysc_init(phys_addr_t base);
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#endif /* PM_RCAR_H */
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@ -32,25 +32,25 @@
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#define AVECR IOMEM(0xfe700040)
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#define R8A7779_SCU_BASE 0xf0000000
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static struct rcar_sysc_ch r8a7779_ch_cpu1 = {
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static const struct rcar_sysc_ch r8a7779_ch_cpu1 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 1, /* ARM1 */
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.isr_bit = 1, /* ARM1 */
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};
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static struct rcar_sysc_ch r8a7779_ch_cpu2 = {
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static const struct rcar_sysc_ch r8a7779_ch_cpu2 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 2, /* ARM2 */
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.isr_bit = 2, /* ARM2 */
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};
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static struct rcar_sysc_ch r8a7779_ch_cpu3 = {
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static const struct rcar_sysc_ch r8a7779_ch_cpu3 = {
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.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
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.chan_bit = 3, /* ARM3 */
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.isr_bit = 3, /* ARM3 */
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};
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static struct rcar_sysc_ch *r8a7779_ch_cpu[4] = {
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static const struct rcar_sysc_ch * const r8a7779_ch_cpu[4] = {
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[1] = &r8a7779_ch_cpu1,
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[2] = &r8a7779_ch_cpu2,
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[3] = &r8a7779_ch_cpu3,
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@ -66,7 +66,7 @@ void __init r8a7779_register_twd(void)
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static int r8a7779_platform_cpu_kill(unsigned int cpu)
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{
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struct rcar_sysc_ch *ch = NULL;
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const struct rcar_sysc_ch *ch = NULL;
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int ret = -EIO;
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cpu = cpu_logical_map(cpu);
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@ -82,7 +82,7 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
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static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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struct rcar_sysc_ch *ch = NULL;
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const struct rcar_sysc_ch *ch = NULL;
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unsigned int lcpu = cpu_logical_map(cpu);
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int ret;
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@ -26,12 +26,12 @@
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#include "rcar-gen2.h"
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#include "r8a7790.h"
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static struct rcar_sysc_ch r8a7790_ca15_scu = {
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static const struct rcar_sysc_ch r8a7790_ca15_scu = {
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.chan_offs = 0x180, /* PWRSR5 .. PWRER5 */
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.isr_bit = 12, /* CA15-SCU */
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};
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static struct rcar_sysc_ch r8a7790_ca7_scu = {
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static const struct rcar_sysc_ch r8a7790_ca7_scu = {
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.chan_offs = 0x100, /* PWRSR3 .. PWRER3 */
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.isr_bit = 21, /* CA7-SCU */
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};
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