forked from luck/tmp_suning_uos_patched
[ARM] pxa: move FICP register definitions into pxaficp_ir.c
Signed-off-by: Eric Miao <eric.miao@marvell.com>
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@ -369,52 +369,9 @@
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/*
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* Fast Infrared Communication Port
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* Fast Infrared Communication Port - moved into drivers/net/irda/pxaficp_ir.c
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*/
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#define FICP __REG(0x40800000) /* Start of FICP area */
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#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
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#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
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#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
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#define ICDR __REG(0x4080000c) /* ICP Data Register */
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#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
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#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
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#define ICCR0_AME (1 << 7) /* Address match enable */
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#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
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#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
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#define ICCR0_RXE (1 << 4) /* Receive enable */
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#define ICCR0_TXE (1 << 3) /* Transmit enable */
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#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
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#define ICCR0_LBM (1 << 1) /* Loopback mode */
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#define ICCR0_ITR (1 << 0) /* IrDA transmission */
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#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
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#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
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#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
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#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
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#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
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#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
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#ifdef CONFIG_PXA27x
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#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
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#endif
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#define ICSR0_FRE (1 << 5) /* Framing error */
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#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
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#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
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#define ICSR0_RAB (1 << 2) /* Receiver abort */
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#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
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#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
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#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
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#define ICSR1_CRE (1 << 5) /* CRC error */
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#define ICSR1_EOF (1 << 4) /* End of frame */
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#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
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#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
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#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
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#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
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/*
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* Real Time Clock
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*/
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@ -26,6 +26,48 @@
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#include <mach/irda.h>
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#include <mach/pxa-regs.h>
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#define FICP __REG(0x40800000) /* Start of FICP area */
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#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
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#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
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#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
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#define ICDR __REG(0x4080000c) /* ICP Data Register */
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#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
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#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
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#define ICCR0_AME (1 << 7) /* Address match enable */
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#define ICCR0_TIE (1 << 6) /* Transmit FIFO interrupt enable */
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#define ICCR0_RIE (1 << 5) /* Recieve FIFO interrupt enable */
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#define ICCR0_RXE (1 << 4) /* Receive enable */
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#define ICCR0_TXE (1 << 3) /* Transmit enable */
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#define ICCR0_TUS (1 << 2) /* Transmit FIFO underrun select */
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#define ICCR0_LBM (1 << 1) /* Loopback mode */
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#define ICCR0_ITR (1 << 0) /* IrDA transmission */
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#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
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#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
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#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
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#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
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#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
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#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
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#ifdef CONFIG_PXA27x
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#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */
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#endif
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#define ICSR0_FRE (1 << 5) /* Framing error */
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#define ICSR0_RFS (1 << 4) /* Receive FIFO service request */
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#define ICSR0_TFS (1 << 3) /* Transnit FIFO service request */
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#define ICSR0_RAB (1 << 2) /* Receiver abort */
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#define ICSR0_TUR (1 << 1) /* Trunsmit FIFO underun */
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#define ICSR0_EIF (1 << 0) /* End/Error in FIFO */
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#define ICSR1_ROR (1 << 6) /* Receiver FIFO underrun */
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#define ICSR1_CRE (1 << 5) /* CRC error */
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#define ICSR1_EOF (1 << 4) /* End of frame */
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#define ICSR1_TNF (1 << 3) /* Transmit FIFO not full */
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#define ICSR1_RNE (1 << 2) /* Receive FIFO not empty */
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#define ICSR1_TBY (1 << 1) /* Tramsmiter busy flag */
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#define ICSR1_RSY (1 << 0) /* Recevier synchronized flag */
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#define IrSR_RXPL_NEG_IS_ZERO (1<<4)
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#define IrSR_RXPL_POS_IS_ZERO 0x0
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#define IrSR_TXPL_NEG_IS_ZERO (1<<3)
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