forked from luck/tmp_suning_uos_patched
clk: qcom: smd: Add support for MSM8992/4 rpm clocks
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8992, MSM8994 (and APQ variants) for clients to vote on. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Link: https://lore.kernel.org/r/20200623230018.303776-1-konradybcio@gmail.com [sboyd@kernel.org: Fixed up binding numbers] Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Konrad Dybcio
Stephen Boyd
parent
f0cfcf1ade
commit
b429784499
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@ -18,6 +18,8 @@ Required properties :
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"qcom,rpmcc-msm8976", "qcom,rpmcc"
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"qcom,rpmcc-apq8064", "qcom,rpmcc"
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"qcom,rpmcc-ipq806x", "qcom,rpmcc"
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"qcom,rpmcc-msm8992",·"qcom,rpmcc"
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"qcom,rpmcc-msm8994",·"qcom,rpmcc"
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"qcom,rpmcc-msm8996", "qcom,rpmcc"
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"qcom,rpmcc-msm8998", "qcom,rpmcc"
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"qcom,rpmcc-qcs404", "qcom,rpmcc"
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@ -623,6 +623,175 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8976 = {
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.num_clks = ARRAY_SIZE(msm8976_clks),
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};
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/* msm8992 */
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DEFINE_CLK_SMD_RPM(msm8992, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8992, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8992, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8992, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8992, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8992, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk1, bb_clk1_a, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk1_pin, bb_clk1_a_pin, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, bb_clk2, bb_clk2_a, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, bb_clk2_pin, bb_clk2_a_pin, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk1, div_clk1_a, 11);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk2, div_clk2_a, 12);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, div_clk3, div_clk3_a, 13);
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DEFINE_CLK_SMD_RPM(msm8992, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, ln_bb_clk, ln_bb_a_clk, 8);
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DEFINE_CLK_SMD_RPM(msm8992, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
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QCOM_SMD_RPM_BUS_CLK, 3);
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DEFINE_CLK_SMD_RPM_QDSS(msm8992, qdss_clk, qdss_a_clk,
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QCOM_SMD_RPM_MISC_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk1, rf_clk1_a, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8992, rf_clk2, rf_clk2_a, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk1_pin, rf_clk1_a_pin, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8992, rf_clk2_pin, rf_clk2_a_pin, 5);
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DEFINE_CLK_SMD_RPM(msm8992, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8992, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
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static struct clk_smd_rpm *msm8992_clks[] = {
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[RPM_SMD_PNOC_CLK] = &msm8992_pnoc_clk,
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[RPM_SMD_PNOC_A_CLK] = &msm8992_pnoc_a_clk,
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[RPM_SMD_OCMEMGX_CLK] = &msm8992_ocmemgx_clk,
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[RPM_SMD_OCMEMGX_A_CLK] = &msm8992_ocmemgx_a_clk,
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[RPM_SMD_BIMC_CLK] = &msm8992_bimc_clk,
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[RPM_SMD_BIMC_A_CLK] = &msm8992_bimc_a_clk,
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[RPM_SMD_CNOC_CLK] = &msm8992_cnoc_clk,
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[RPM_SMD_CNOC_A_CLK] = &msm8992_cnoc_a_clk,
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[RPM_SMD_GFX3D_CLK_SRC] = &msm8992_gfx3d_clk_src,
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[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8992_gfx3d_a_clk_src,
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[RPM_SMD_SNOC_CLK] = &msm8992_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8992_snoc_a_clk,
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[RPM_SMD_BB_CLK1] = &msm8992_bb_clk1,
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[RPM_SMD_BB_CLK1_A] = &msm8992_bb_clk1_a,
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[RPM_SMD_BB_CLK1_PIN] = &msm8992_bb_clk1_pin,
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[RPM_SMD_BB_CLK1_A_PIN] = &msm8992_bb_clk1_a_pin,
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[RPM_SMD_BB_CLK2] = &msm8992_bb_clk2,
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[RPM_SMD_BB_CLK2_A] = &msm8992_bb_clk2_a,
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[RPM_SMD_BB_CLK2_PIN] = &msm8992_bb_clk2_pin,
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[RPM_SMD_BB_CLK2_A_PIN] = &msm8992_bb_clk2_a_pin,
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[RPM_SMD_DIV_CLK1] = &msm8992_div_clk1,
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[RPM_SMD_DIV_A_CLK1] = &msm8992_div_clk1_a,
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[RPM_SMD_DIV_CLK2] = &msm8992_div_clk2,
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[RPM_SMD_DIV_A_CLK2] = &msm8992_div_clk2_a,
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[RPM_SMD_DIV_CLK3] = &msm8992_div_clk3,
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[RPM_SMD_DIV_A_CLK3] = &msm8992_div_clk3_a,
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[RPM_SMD_IPA_CLK] = &msm8992_ipa_clk,
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[RPM_SMD_IPA_A_CLK] = &msm8992_ipa_a_clk,
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[RPM_SMD_LN_BB_CLK] = &msm8992_ln_bb_clk,
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[RPM_SMD_LN_BB_A_CLK] = &msm8992_ln_bb_a_clk,
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[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8992_mmssnoc_ahb_clk,
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[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8992_mmssnoc_ahb_a_clk,
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[RPM_SMD_QDSS_CLK] = &msm8992_qdss_clk,
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[RPM_SMD_QDSS_A_CLK] = &msm8992_qdss_a_clk,
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[RPM_SMD_RF_CLK1] = &msm8992_rf_clk1,
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[RPM_SMD_RF_CLK1_A] = &msm8992_rf_clk1_a,
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[RPM_SMD_RF_CLK2] = &msm8992_rf_clk2,
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[RPM_SMD_RF_CLK2_A] = &msm8992_rf_clk2_a,
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[RPM_SMD_RF_CLK1_PIN] = &msm8992_rf_clk1_pin,
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[RPM_SMD_RF_CLK1_A_PIN] = &msm8992_rf_clk1_a_pin,
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[RPM_SMD_RF_CLK2_PIN] = &msm8992_rf_clk2_pin,
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[RPM_SMD_RF_CLK2_A_PIN] = &msm8992_rf_clk2_a_pin,
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[RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
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[RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
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[RPM_SMD_CE2_CLK] = &msm8992_ce2_clk,
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[RPM_SMD_CE2_A_CLK] = &msm8992_ce2_a_clk,
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};
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static const struct rpm_smd_clk_desc rpm_clk_msm8992 = {
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.clks = msm8992_clks,
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.num_clks = ARRAY_SIZE(msm8992_clks),
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};
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/* msm8994 */
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DEFINE_CLK_SMD_RPM(msm8994, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8994, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8994, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8994, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
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DEFINE_CLK_SMD_RPM(msm8994, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8994, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk1, bb_clk1_a, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk1_pin, bb_clk1_a_pin, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, bb_clk2, bb_clk2_a, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, bb_clk2_pin, bb_clk2_a_pin, 2);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk1, div_clk1_a, 11);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk2, div_clk2_a, 12);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, div_clk3, div_clk3_a, 13);
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DEFINE_CLK_SMD_RPM(msm8994, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, ln_bb_clk, ln_bb_a_clk, 8);
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DEFINE_CLK_SMD_RPM(msm8994, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk,
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QCOM_SMD_RPM_BUS_CLK, 3);
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DEFINE_CLK_SMD_RPM_QDSS(msm8994, qdss_clk, qdss_a_clk,
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QCOM_SMD_RPM_MISC_CLK, 1);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk1, rf_clk1_a, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8994, rf_clk2, rf_clk2_a, 5);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk1_pin, rf_clk1_a_pin, 4);
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DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8994, rf_clk2_pin, rf_clk2_a_pin, 5);
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DEFINE_CLK_SMD_RPM(msm8994, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8994, ce2_clk, ce2_a_clk, QCOM_SMD_RPM_CE_CLK, 1);
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DEFINE_CLK_SMD_RPM(msm8994, ce3_clk, ce3_a_clk, QCOM_SMD_RPM_CE_CLK, 2);
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static struct clk_smd_rpm *msm8994_clks[] = {
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[RPM_SMD_PNOC_CLK] = &msm8994_pnoc_clk,
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[RPM_SMD_PNOC_A_CLK] = &msm8994_pnoc_a_clk,
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[RPM_SMD_OCMEMGX_CLK] = &msm8994_ocmemgx_clk,
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[RPM_SMD_OCMEMGX_A_CLK] = &msm8994_ocmemgx_a_clk,
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[RPM_SMD_BIMC_CLK] = &msm8994_bimc_clk,
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[RPM_SMD_BIMC_A_CLK] = &msm8994_bimc_a_clk,
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[RPM_SMD_CNOC_CLK] = &msm8994_cnoc_clk,
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[RPM_SMD_CNOC_A_CLK] = &msm8994_cnoc_a_clk,
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[RPM_SMD_GFX3D_CLK_SRC] = &msm8994_gfx3d_clk_src,
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[RPM_SMD_GFX3D_A_CLK_SRC] = &msm8994_gfx3d_a_clk_src,
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[RPM_SMD_SNOC_CLK] = &msm8994_snoc_clk,
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[RPM_SMD_SNOC_A_CLK] = &msm8994_snoc_a_clk,
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[RPM_SMD_BB_CLK1] = &msm8994_bb_clk1,
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[RPM_SMD_BB_CLK1_A] = &msm8994_bb_clk1_a,
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[RPM_SMD_BB_CLK1_PIN] = &msm8994_bb_clk1_pin,
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[RPM_SMD_BB_CLK1_A_PIN] = &msm8994_bb_clk1_a_pin,
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[RPM_SMD_BB_CLK2] = &msm8994_bb_clk2,
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[RPM_SMD_BB_CLK2_A] = &msm8994_bb_clk2_a,
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[RPM_SMD_BB_CLK2_PIN] = &msm8994_bb_clk2_pin,
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[RPM_SMD_BB_CLK2_A_PIN] = &msm8994_bb_clk2_a_pin,
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[RPM_SMD_DIV_CLK1] = &msm8994_div_clk1,
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[RPM_SMD_DIV_A_CLK1] = &msm8994_div_clk1_a,
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[RPM_SMD_DIV_CLK2] = &msm8994_div_clk2,
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[RPM_SMD_DIV_A_CLK2] = &msm8994_div_clk2_a,
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[RPM_SMD_DIV_CLK3] = &msm8994_div_clk3,
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[RPM_SMD_DIV_A_CLK3] = &msm8994_div_clk3_a,
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[RPM_SMD_IPA_CLK] = &msm8994_ipa_clk,
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[RPM_SMD_IPA_A_CLK] = &msm8994_ipa_a_clk,
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[RPM_SMD_LN_BB_CLK] = &msm8994_ln_bb_clk,
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[RPM_SMD_LN_BB_A_CLK] = &msm8994_ln_bb_a_clk,
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[RPM_SMD_MMSSNOC_AHB_CLK] = &msm8994_mmssnoc_ahb_clk,
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[RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8994_mmssnoc_ahb_a_clk,
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[RPM_SMD_QDSS_CLK] = &msm8994_qdss_clk,
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[RPM_SMD_QDSS_A_CLK] = &msm8994_qdss_a_clk,
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[RPM_SMD_RF_CLK1] = &msm8994_rf_clk1,
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[RPM_SMD_RF_CLK1_A] = &msm8994_rf_clk1_a,
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[RPM_SMD_RF_CLK2] = &msm8994_rf_clk2,
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[RPM_SMD_RF_CLK2_A] = &msm8994_rf_clk2_a,
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[RPM_SMD_RF_CLK1_PIN] = &msm8994_rf_clk1_pin,
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[RPM_SMD_RF_CLK1_A_PIN] = &msm8994_rf_clk1_a_pin,
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[RPM_SMD_RF_CLK2_PIN] = &msm8994_rf_clk2_pin,
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[RPM_SMD_RF_CLK2_A_PIN] = &msm8994_rf_clk2_a_pin,
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[RPM_SMD_CE1_CLK] = &msm8994_ce1_clk,
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[RPM_SMD_CE1_A_CLK] = &msm8994_ce1_a_clk,
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[RPM_SMD_CE2_CLK] = &msm8994_ce2_clk,
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[RPM_SMD_CE2_A_CLK] = &msm8994_ce2_a_clk,
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[RPM_SMD_CE3_CLK] = &msm8994_ce3_clk,
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[RPM_SMD_CE3_A_CLK] = &msm8994_ce3_a_clk,
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};
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static const struct rpm_smd_clk_desc rpm_clk_msm8994 = {
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.clks = msm8994_clks,
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.num_clks = ARRAY_SIZE(msm8994_clks),
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};
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/* msm8996 */
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DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
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DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
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@ -895,6 +1064,8 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
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{ .compatible = "qcom,rpmcc-msm8936", .data = &rpm_clk_msm8936 },
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{ .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
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{ .compatible = "qcom,rpmcc-msm8976", .data = &rpm_clk_msm8976 },
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{ .compatible = "qcom,rpmcc-msm8992", .data = &rpm_clk_msm8992 },
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{ .compatible = "qcom,rpmcc-msm8994", .data = &rpm_clk_msm8994 },
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{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
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{ .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
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{ .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
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@ -145,5 +145,9 @@
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#define RPM_SMD_LN_BB_CLK2_A_PIN 99
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#define RPM_SMD_SYSMMNOC_CLK 100
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#define RPM_SMD_SYSMMNOC_A_CLK 101
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#define RPM_SMD_CE2_CLK 102
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#define RPM_SMD_CE2_A_CLK 103
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#define RPM_SMD_CE3_CLK 104
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#define RPM_SMD_CE3_A_CLK 105
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#endif
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