From 417e24986935f6bd6afa38010cc981cf4d7a7bef Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Jul 2020 18:00:24 +0100 Subject: [PATCH 01/78] pinctrl: sh-pfc: r8a7790: Add USB1 PWEN pin and group Add USB1 PWEN pin and group for USB1 interface. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/1595005225-11519-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index f524401fec5f..39ba1e7cc1c3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3611,6 +3611,13 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +static const unsigned int usb1_pwen_pins[] = { + /* PWEN */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int usb1_pwen_mux[] = { + USB1_PWEN_MARK, +}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3939,7 +3946,7 @@ static const unsigned int vin3_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[289]; + struct sh_pfc_pin_group common[290]; struct sh_pfc_pin_group automotive[1]; } pinmux_groups = { .common = { @@ -4193,6 +4200,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb0_ovc_vbus), SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_pwen), SH_PFC_PIN_GROUP(usb2), VIN_DATA_PIN_GROUP(vin0_data, 24), VIN_DATA_PIN_GROUP(vin0_data, 20), @@ -4640,6 +4648,7 @@ static const char * const usb0_groups[] = { static const char * const usb1_groups[] = { "usb1", + "usb1_pwen", }; static const char * const usb2_groups[] = { From 0e2d769d4b4eb8eb012c430be34b6ca06daf9e1d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 27 Jul 2020 19:12:14 +0300 Subject: [PATCH 02/78] pinctrl: cherryview: Drop stale comment There is no more .groups member in struct chv_pinctrl, drop associated comment because it's not applicable anymore. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 9ef246145bde..41708f7ea65c 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -86,9 +86,6 @@ struct intel_pad_context { * @irq: Our parent irq * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) * @saved_intmask: Interrupt mask saved for system sleep - * - * The first group in @groups is expected to contain all pins that can be - * used as GPIOs. */ struct chv_pinctrl { struct device *dev; From 8a82857077804b03be3a64fc5204ebc49a53dd95 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 27 Jul 2020 19:12:15 +0300 Subject: [PATCH 03/78] pinctrl: cherryview: Move custom community members to separate data struct This is a preparatory patch for bigger clean up pending for Cherryview driver. There is no functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 45 +++++++++++++++------- 1 file changed, 31 insertions(+), 14 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 41708f7ea65c..6b2fbc0ac422 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -72,6 +72,16 @@ struct intel_pad_context { u32 padctrl1; }; +/** + * struct intel_community_context - community context for Cherryview + * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) + * @saved_intmask: Interrupt mask saved for system sleep + */ +struct intel_community_context { + unsigned int intr_lines[16]; + u32 saved_intmask; +}; + /** * struct chv_pinctrl - CHV pinctrl private structure * @dev: Pointer to the parent device @@ -84,8 +94,6 @@ struct intel_pad_context { * @ncommunities: Number of communities in this pin controller * @context: Configuration saved over system sleep * @irq: Our parent irq - * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) - * @saved_intmask: Interrupt mask saved for system sleep */ struct chv_pinctrl { struct device *dev; @@ -98,9 +106,6 @@ struct chv_pinctrl { size_t ncommunities; struct intel_pinctrl_context context; int irq; - - unsigned int intr_lines[16]; - u32 saved_intmask; }; #define PINMODE_INVERT_OE BIT(15) @@ -815,12 +820,13 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, return -EBUSY; } } else { + struct intel_community_context *cctx = &pctrl->context.communities[0]; int i; /* Reset the interrupt mapping */ - for (i = 0; i < ARRAY_SIZE(pctrl->intr_lines); i++) { - if (pctrl->intr_lines[i] == offset) { - pctrl->intr_lines[i] = 0; + for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { + if (cctx->intr_lines[i] == offset) { + cctx->intr_lines[i] = 0; break; } } @@ -1310,6 +1316,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); irq_flow_handler_t handler; unsigned long flags; @@ -1326,9 +1333,9 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) else handler = handle_edge_irq; - if (!pctrl->intr_lines[intsel]) { + if (!cctx->intr_lines[intsel]) { irq_set_handler_locked(d, handler); - pctrl->intr_lines[intsel] = pin; + cctx->intr_lines[intsel] = pin; } raw_spin_unlock_irqrestore(&chv_lock, flags); } @@ -1341,6 +1348,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); unsigned long flags; u32 value; @@ -1385,7 +1393,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) value &= CHV_PADCTRL0_INTSEL_MASK; value >>= CHV_PADCTRL0_INTSEL_SHIFT; - pctrl->intr_lines[value] = pin; + cctx->intr_lines[value] = pin; if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); @@ -1402,6 +1410,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) struct gpio_chip *gc = irq_desc_get_handler_data(desc); struct chv_pinctrl *pctrl = gpiochip_get_data(gc); const struct intel_community *community = &pctrl->communities[0]; + struct intel_community_context *cctx = &pctrl->context.communities[0]; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; unsigned long flags; @@ -1416,7 +1425,7 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) for_each_set_bit(intr_line, &pending, community->nirqs) { unsigned int irq, offset; - offset = pctrl->intr_lines[intr_line]; + offset = cctx->intr_lines[intr_line]; irq = irq_find_mapping(gc->irq.domain, offset); generic_handle_irq(irq); } @@ -1674,6 +1683,12 @@ static int chv_pinctrl_probe(struct platform_device *pdev) return -ENOMEM; #endif + pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities, + sizeof(*pctrl->context.communities), + GFP_KERNEL); + if (!pctrl->context.communities) + return -ENOMEM; + irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; @@ -1722,12 +1737,13 @@ static int chv_pinctrl_remove(struct platform_device *pdev) static int chv_pinctrl_suspend_noirq(struct device *dev) { struct chv_pinctrl *pctrl = dev_get_drvdata(dev); + struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned long flags; int i; raw_spin_lock_irqsave(&chv_lock, flags); - pctrl->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); + cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); for (i = 0; i < pctrl->soc->npins; i++) { const struct pinctrl_pin_desc *desc; @@ -1751,6 +1767,7 @@ static int chv_pinctrl_suspend_noirq(struct device *dev) static int chv_pinctrl_resume_noirq(struct device *dev) { struct chv_pinctrl *pctrl = dev_get_drvdata(dev); + struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned long flags; int i; @@ -1794,7 +1811,7 @@ static int chv_pinctrl_resume_noirq(struct device *dev) * the interrupt mask register as well. */ chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); - chv_pctrl_writel(pctrl, CHV_INTMASK, pctrl->saved_intmask); + chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); raw_spin_unlock_irqrestore(&chv_lock, flags); From 3ea2e2cabd2dc749d866887a8eaab9fd9536ca0b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 27 Jul 2020 19:12:16 +0300 Subject: [PATCH 04/78] pinctrl: cherryview: Switch to use struct intel_pinctrl Now when all preparations are done we may easily switch to use struct intel_pinctrl instead of custom one. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 104 ++++++++------------- 1 file changed, 39 insertions(+), 65 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 6b2fbc0ac422..c18abc1a0d04 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -82,32 +82,6 @@ struct intel_community_context { u32 saved_intmask; }; -/** - * struct chv_pinctrl - CHV pinctrl private structure - * @dev: Pointer to the parent device - * @pctldesc: Pin controller description - * @pctldev: Pointer to the pin controller device - * @chip: GPIO chip in this pin controller - * @irqchip: IRQ chip in this pin controller - * @soc: Community specific pin configuration data - * @communities: All communities in this pin controller - * @ncommunities: Number of communities in this pin controller - * @context: Configuration saved over system sleep - * @irq: Our parent irq - */ -struct chv_pinctrl { - struct device *dev; - struct pinctrl_desc pctldesc; - struct pinctrl_dev *pctldev; - struct gpio_chip chip; - struct irq_chip irqchip; - const struct intel_pinctrl_soc_data *soc; - struct intel_community *communities; - size_t ncommunities; - struct intel_pinctrl_context context; - int irq; -}; - #define PINMODE_INVERT_OE BIT(15) #define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) @@ -589,14 +563,14 @@ static const struct intel_pinctrl_soc_data *chv_soc_data[] = { */ static DEFINE_RAW_SPINLOCK(chv_lock); -static u32 chv_pctrl_readl(struct chv_pinctrl *pctrl, unsigned int offset) +static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) { const struct intel_community *community = &pctrl->communities[0]; return readl(community->regs + offset); } -static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 value) +static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) { const struct intel_community *community = &pctrl->communities[0]; void __iomem *reg = community->regs + offset; @@ -606,7 +580,7 @@ static void chv_pctrl_writel(struct chv_pinctrl *pctrl, unsigned int offset, u32 readl(reg); } -static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset, +static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, unsigned int reg) { const struct intel_community *community = &pctrl->communities[0]; @@ -618,12 +592,12 @@ static void __iomem *chv_padreg(struct chv_pinctrl *pctrl, unsigned int offset, return community->pad_regs + offset + reg; } -static u32 chv_readl(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset) +static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) { return readl(chv_padreg(pctrl, pin, offset)); } -static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) +static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) { void __iomem *reg = chv_padreg(pctrl, pin, offset); @@ -633,14 +607,14 @@ static void chv_writel(struct chv_pinctrl *pctrl, unsigned int pin, unsigned int } /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ -static bool chv_pad_locked(struct chv_pinctrl *pctrl, unsigned int offset) +static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) { return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; } static int chv_get_groups_count(struct pinctrl_dev *pctldev) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->ngroups; } @@ -648,7 +622,7 @@ static int chv_get_groups_count(struct pinctrl_dev *pctldev) static const char *chv_get_group_name(struct pinctrl_dev *pctldev, unsigned int group) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->groups[group].name; } @@ -656,7 +630,7 @@ static const char *chv_get_group_name(struct pinctrl_dev *pctldev, static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, const unsigned int **pins, unsigned int *npins) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); *pins = pctrl->soc->groups[group].pins; *npins = pctrl->soc->groups[group].npins; @@ -666,7 +640,7 @@ static int chv_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group, static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int offset) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; u32 ctrl0, ctrl1; bool locked; @@ -705,7 +679,7 @@ static const struct pinctrl_ops chv_pinctrl_ops = { static int chv_get_functions_count(struct pinctrl_dev *pctldev) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->nfunctions; } @@ -713,7 +687,7 @@ static int chv_get_functions_count(struct pinctrl_dev *pctldev) static const char *chv_get_function_name(struct pinctrl_dev *pctldev, unsigned int function) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); return pctrl->soc->functions[function].name; } @@ -723,7 +697,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev, const char * const **groups, unsigned int * const ngroups) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); *groups = pctrl->soc->functions[function].groups; *ngroups = pctrl->soc->functions[function].ngroups; @@ -733,7 +707,7 @@ static int chv_get_function_groups(struct pinctrl_dev *pctldev, static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); const struct intel_pingroup *grp; unsigned long flags; int i; @@ -791,7 +765,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, return 0; } -static void chv_gpio_clear_triggering(struct chv_pinctrl *pctrl, +static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, unsigned int offset) { u32 value; @@ -806,7 +780,7 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; u32 value; @@ -860,7 +834,7 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; raw_spin_lock_irqsave(&chv_lock, flags); @@ -875,7 +849,7 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned int offset, bool input) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; u32 ctrl0; @@ -906,7 +880,7 @@ static const struct pinmux_ops chv_pinmux_ops = { static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); unsigned long flags; u32 ctrl0, ctrl1; @@ -983,7 +957,7 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, return 0; } -static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin, +static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 arg) { unsigned long flags; @@ -1048,7 +1022,7 @@ static int chv_config_set_pull(struct chv_pinctrl *pctrl, unsigned int pin, return 0; } -static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, +static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, bool enable) { unsigned long flags; @@ -1071,7 +1045,7 @@ static int chv_config_set_oden(struct chv_pinctrl *pctrl, unsigned int pin, static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *configs, unsigned int nconfigs) { - struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param; int i, ret; u32 arg; @@ -1172,7 +1146,7 @@ static struct pinctrl_desc chv_pinctrl_desc = { static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); unsigned long flags; u32 ctrl0, cfg; @@ -1190,7 +1164,7 @@ static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); unsigned long flags; u32 ctrl0; @@ -1210,7 +1184,7 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); u32 ctrl0, direction; unsigned long flags; @@ -1253,7 +1227,7 @@ static const struct gpio_chip chv_gpio_chip = { static void chv_gpio_irq_ack(struct irq_data *d) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); int pin = irqd_to_hwirq(d); u32 intr_line; @@ -1270,7 +1244,7 @@ static void chv_gpio_irq_ack(struct irq_data *d) static void chv_gpio_irq_mask_unmask(struct irq_data *d, bool mask) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); int pin = irqd_to_hwirq(d); u32 value, intr_line; unsigned long flags; @@ -1315,7 +1289,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) */ if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); irq_flow_handler_t handler; @@ -1347,7 +1321,7 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); - struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned int pin = irqd_to_hwirq(d); unsigned long flags; @@ -1408,7 +1382,7 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) static void chv_gpio_irq_handler(struct irq_desc *desc) { struct gpio_chip *gc = irq_desc_get_handler_data(desc); - struct chv_pinctrl *pctrl = gpiochip_get_data(gc); + struct intel_pinctrl *pctrl = gpiochip_get_data(gc); const struct intel_community *community = &pctrl->communities[0]; struct intel_community_context *cctx = &pctrl->context.communities[0]; struct irq_chip *chip = irq_desc_get_chip(desc); @@ -1478,7 +1452,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip, unsigned long *valid_mask, unsigned int ngpios) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); const struct intel_community *community = &pctrl->communities[0]; int i; @@ -1500,7 +1474,7 @@ static void chv_init_irq_valid_mask(struct gpio_chip *chip, static int chv_gpio_irq_init_hw(struct gpio_chip *chip) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); const struct intel_community *community = &pctrl->communities[0]; /* @@ -1526,7 +1500,7 @@ static int chv_gpio_irq_init_hw(struct gpio_chip *chip) static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { - struct chv_pinctrl *pctrl = gpiochip_get_data(chip); + struct intel_pinctrl *pctrl = gpiochip_get_data(chip); const struct intel_community *community = &pctrl->communities[0]; const struct intel_padgroup *gpp; int ret, i; @@ -1545,7 +1519,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) return 0; } -static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) +static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) { const struct intel_community *community = &pctrl->communities[0]; const struct intel_padgroup *gpp; @@ -1611,7 +1585,7 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function, acpi_physical_address address, u32 bits, u64 *value, void *handler_context, void *region_context) { - struct chv_pinctrl *pctrl = region_context; + struct intel_pinctrl *pctrl = region_context; unsigned long flags; acpi_status ret = AE_OK; @@ -1635,7 +1609,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) const struct intel_pinctrl_soc_data **soc_table; struct intel_community *community; struct device *dev = &pdev->dev; - struct chv_pinctrl *pctrl; + struct intel_pinctrl *pctrl; struct acpi_device *adev; acpi_status status; int ret, irq, i; @@ -1723,7 +1697,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) static int chv_pinctrl_remove(struct platform_device *pdev) { - struct chv_pinctrl *pctrl = platform_get_drvdata(pdev); + struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); const struct intel_community *community = &pctrl->communities[0]; acpi_remove_address_space_handler(ACPI_COMPANION(&pdev->dev), @@ -1736,7 +1710,7 @@ static int chv_pinctrl_remove(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static int chv_pinctrl_suspend_noirq(struct device *dev) { - struct chv_pinctrl *pctrl = dev_get_drvdata(dev); + struct intel_pinctrl *pctrl = dev_get_drvdata(dev); struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned long flags; int i; @@ -1766,7 +1740,7 @@ static int chv_pinctrl_suspend_noirq(struct device *dev) static int chv_pinctrl_resume_noirq(struct device *dev) { - struct chv_pinctrl *pctrl = dev_get_drvdata(dev); + struct intel_pinctrl *pctrl = dev_get_drvdata(dev); struct intel_community_context *cctx = &pctrl->context.communities[0]; unsigned long flags; int i; From 359164fa730c45641ec597f48ab33c03d955e824 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2020 15:02:30 +0300 Subject: [PATCH 05/78] pinctrl: cherryview: Utilize temporary variable to hold device pointer By one of the previous clean up change we got a temporary variable to hold a device pointer. It can be utilized in other calls in the ->probe() and save a bit of LOCs. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index c18abc1a0d04..86e954df82d6 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1632,7 +1632,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) if (!pctrl) return -ENOMEM; - pctrl->dev = &pdev->dev; + pctrl->dev = dev; pctrl->soc = soc_data; pctrl->ncommunities = pctrl->soc->ncommunities; @@ -1668,14 +1668,13 @@ static int chv_pinctrl_probe(struct platform_device *pdev) return irq; pctrl->pctldesc = chv_pinctrl_desc; - pctrl->pctldesc.name = dev_name(&pdev->dev); + pctrl->pctldesc.name = dev_name(dev); pctrl->pctldesc.pins = pctrl->soc->pins; pctrl->pctldesc.npins = pctrl->soc->npins; - pctrl->pctldev = devm_pinctrl_register(&pdev->dev, &pctrl->pctldesc, - pctrl); + pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); if (IS_ERR(pctrl->pctldev)) { - dev_err(&pdev->dev, "failed to register pinctrl driver\n"); + dev_err(dev, "failed to register pinctrl driver\n"); return PTR_ERR(pctrl->pctldev); } @@ -1688,7 +1687,7 @@ static int chv_pinctrl_probe(struct platform_device *pdev) chv_pinctrl_mmio_access_handler, NULL, pctrl); if (ACPI_FAILURE(status)) - dev_err(&pdev->dev, "failed to install ACPI addr space handler\n"); + dev_err(dev, "failed to install ACPI addr space handler\n"); platform_set_drvdata(pdev, pctrl); From ff360d62d9fe02081431412e05950a23f71ec98a Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2020 14:57:06 +0300 Subject: [PATCH 06/78] pinctrl: intel: Extract intel_pinctrl_get_soc_data() helper for wider use intel_pinctrl_get_soc_data() helper can be used in few driver instead of open-coded variants. Thus, extract it as a standalone API. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 24 ++++++++++++++++++------ drivers/pinctrl/intel/pinctrl-intel.h | 2 ++ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index b64997b303e0..154ce3f908cd 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1414,9 +1414,6 @@ static int intel_pinctrl_probe(struct platform_device *pdev, struct intel_pinctrl *pctrl; int i, ret, irq; - if (!soc_data) - return -EINVAL; - pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) return -ENOMEM; @@ -1505,11 +1502,26 @@ int intel_pinctrl_probe_by_hid(struct platform_device *pdev) const struct intel_pinctrl_soc_data *data; data = device_get_match_data(&pdev->dev); + if (!data) + return -ENODATA; + return intel_pinctrl_probe(pdev, data); } EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid); int intel_pinctrl_probe_by_uid(struct platform_device *pdev) +{ + const struct intel_pinctrl_soc_data *data; + + data = intel_pinctrl_get_soc_data(pdev); + if (IS_ERR(data)) + return PTR_ERR(data); + + return intel_pinctrl_probe(pdev, data); +} +EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); + +const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev) { const struct intel_pinctrl_soc_data *data = NULL; const struct intel_pinctrl_soc_data **table; @@ -1532,15 +1544,15 @@ int intel_pinctrl_probe_by_uid(struct platform_device *pdev) id = platform_get_device_id(pdev); if (!id) - return -ENODEV; + return ERR_PTR(-ENODEV); table = (const struct intel_pinctrl_soc_data **)id->driver_data; data = table[pdev->id]; } - return intel_pinctrl_probe(pdev, data); + return data ?: ERR_PTR(-ENODATA); } -EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid); +EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data); #ifdef CONFIG_PM_SLEEP static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 4e17308d33e9..3b0564ae9b15 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -194,6 +194,8 @@ struct intel_pinctrl_soc_data { size_t ncommunities; }; +const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev); + struct intel_pad_context; struct intel_community_context; From ce7793e9ef6322d236b722ada386d3bb7ecb7df2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2020 14:57:07 +0300 Subject: [PATCH 07/78] pinctrl: baytrail: Switch to use intel_pinctrl_get_soc_data() Since we have common helper to retrieve SoC data from driver data we may switch to use it. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 6 +----- drivers/pinctrl/intel/pinctrl-baytrail.c | 24 +++++------------------- 2 files changed, 6 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index b3e6060db52d..c7f0d5d9d9d3 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -6,11 +6,7 @@ if (X86 || COMPILE_TEST) config PINCTRL_BAYTRAIL bool "Intel Baytrail GPIO pin control" depends on ACPI - select GPIOLIB - select GPIOLIB_IRQCHIP - select PINMUX - select PINCONF - select GENERIC_PINCONF + select PINCTRL_INTEL help driver for memory mapped GPIO functionality on Intel Baytrail platforms. Supports 3 banks with 102, 28 and 44 gpios. diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index d6e35cba3065..d49aab3cfbaa 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1635,28 +1635,14 @@ static const struct acpi_device_id byt_gpio_acpi_match[] = { static int byt_pinctrl_probe(struct platform_device *pdev) { - const struct intel_pinctrl_soc_data *soc_data = NULL; - const struct intel_pinctrl_soc_data **soc_table; + const struct intel_pinctrl_soc_data *soc_data; struct device *dev = &pdev->dev; - struct acpi_device *acpi_dev; struct intel_pinctrl *vg; - int i, ret; + int ret; - acpi_dev = ACPI_COMPANION(dev); - if (!acpi_dev) - return -ENODEV; - - soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev); - - for (i = 0; soc_table[i]; i++) { - if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) { - soc_data = soc_table[i]; - break; - } - } - - if (!soc_data) - return -ENODEV; + soc_data = intel_pinctrl_get_soc_data(pdev); + if (IS_ERR(soc_data)) + return PTR_ERR(soc_data); vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL); if (!vg) From 10c857f063fc63902160755a6e23fa594290c6d3 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 29 Jul 2020 14:57:08 +0300 Subject: [PATCH 08/78] pinctrl: cherryview: Switch to use intel_pinctrl_get_soc_data() Since we have common helper to retrieve SoC data from driver data we may switch to use it. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 6 +----- drivers/pinctrl/intel/pinctrl-cherryview.c | 23 ++++++---------------- 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index c7f0d5d9d9d3..28e5f824ba45 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -18,11 +18,7 @@ config PINCTRL_BAYTRAIL config PINCTRL_CHERRYVIEW tristate "Intel Cherryview/Braswell pinctrl and GPIO driver" depends on ACPI - select PINMUX - select PINCONF - select GENERIC_PINCONF - select GPIOLIB - select GPIOLIB_IRQCHIP + select PINCTRL_INTEL help Cherryview/Braswell pinctrl driver provides an interface that allows configuring of SoC pins and using them as GPIOs. diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 86e954df82d6..e48d4445e932 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1605,28 +1605,17 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function, static int chv_pinctrl_probe(struct platform_device *pdev) { - const struct intel_pinctrl_soc_data *soc_data = NULL; - const struct intel_pinctrl_soc_data **soc_table; + const struct intel_pinctrl_soc_data *soc_data; struct intel_community *community; struct device *dev = &pdev->dev; + struct acpi_device *adev = ACPI_COMPANION(dev); struct intel_pinctrl *pctrl; - struct acpi_device *adev; acpi_status status; - int ret, irq, i; + int ret, irq; - adev = ACPI_COMPANION(&pdev->dev); - if (!adev) - return -ENODEV; - - soc_table = (const struct intel_pinctrl_soc_data **)device_get_match_data(dev); - for (i = 0; soc_table[i]; i++) { - if (!strcmp(adev->pnp.unique_id, soc_table[i]->uid)) { - soc_data = soc_table[i]; - break; - } - } - if (!soc_data) - return -ENODEV; + soc_data = intel_pinctrl_get_soc_data(pdev); + if (IS_ERR(soc_data)) + return PTR_ERR(soc_data); pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); if (!pctrl) From 04d53068508e1b670a46ed9507aeaec7ef6d4ae4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 18 Aug 2020 17:23:53 +0300 Subject: [PATCH 09/78] pinctrl: intel: Update header block to reflect direct dependencies Update header inclusion block to reflect all direct dependencies that are being involved in pinctrl-intel.h. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 3b0564ae9b15..ad34b7a3f6ed 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -10,12 +10,15 @@ #ifndef PINCTRL_INTEL_H #define PINCTRL_INTEL_H +#include +#include #include #include +#include #include +#include #include -struct pinctrl_pin_desc; struct platform_device; struct device; From fe9c36442769e07aaaf0dce1fb7f083faad4b1e9 Mon Sep 17 00:00:00 2001 From: Andrew Halaney Date: Thu, 6 Aug 2020 10:53:25 -0500 Subject: [PATCH 10/78] pinctrl: nomadik: Fix pull direction debug info The nomadik pinctrl hardware doesn't have any way to determine if the active pull is up or down. Reading the bit currently used to report if the pull is up/down indicates if the gpio input is reading high or low, it doesn't reflect the pull state. For this reason change the output from "pull up"/"pull down" to "pull enabled". This avoids confusing developers who were using the output to determine what the pull state is. Signed-off-by: Andrew Halaney Link: https://lore.kernel.org/r/20200806155322.GA25523@ola-jn9phv2.ad.garmin.com Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ba25c4654391..657e35a75d84 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -931,11 +931,6 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, [NMK_GPIO_ALT_C+3] = "altC3", [NMK_GPIO_ALT_C+4] = "altC4", }; - const char *pulls[] = { - "none ", - "pull down", - "pull up ", - }; clk_enable(nmk_chip->clk); is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); @@ -946,7 +941,7 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, mode = nmk_prcm_gpiocr_get_mode(pctldev, gpio); if (is_out) { - seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", + seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", gpio, label ?: "(none)", data_out ? "hi" : "lo", @@ -954,11 +949,12 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s, } else { int irq = chip->to_irq(chip, offset); struct irq_desc *desc = irq_to_desc(irq); - int pullidx = 0; + const int pullidx = pull ? 1 : 0; int val; - - if (pull) - pullidx = data_out ? 2 : 1; + static const char * const pulls[] = { + "none ", + "pull enabled", + }; seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", gpio, From 0c0a41fb17484c9046faf65739dc77853ca32a0c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= Date: Fri, 24 Jul 2020 15:24:57 +0200 Subject: [PATCH 11/78] pinctrl: armada-37xx: Add comment for pcie1_reset pin group MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group name 'pcie1' is misleading as it controls only PCIe reset pin. Like other PCIe groups it should have been called 'pcie1_reset'. But due to backward compatibility it is not possible to change existing group name. So just add comment describing this PCIe reset functionality. Signed-off-by: Pali Rohár Link: https://lore.kernel.org/r/20200724132457.7094-1-pali@kernel.org Signed-off-by: Linus Walleij --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 2bbc69b4dc99..d5b6c0a1c54a 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -316,7 +316,7 @@ sdio_pins: sdio-pins { }; pcie_reset_pins: pcie-reset-pins { - groups = "pcie1"; + groups = "pcie1"; /* this actually controls "pcie1_reset" */ function = "gpio"; }; diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c index 953126bf6657..68894e9e05d2 100644 --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c @@ -197,7 +197,7 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), - PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), + PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"), From 441717c46fc71e349cf8373392a2afd61332dd4e Mon Sep 17 00:00:00 2001 From: Bartosz Dudziak Date: Thu, 16 Jul 2020 22:55:28 +0200 Subject: [PATCH 12/78] dt-bindings: pinctrl: qcom: Add msm8226 pinctrl bindings Add device tree binding Documentation details for Qualcomm msm8226 pinctrl driver. - Bindings documentation was based on qcom,ipq6018-pinctrl.yaml added by Sricharan R and then modified for msm8226 content Signed-off-by: Bartosz Dudziak Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200716205530.22910-2-bartosz.dudziak@snejp.pl Signed-off-by: Linus Walleij --- .../pinctrl/qcom,msm8226-pinctrl.yaml | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml new file mode 100644 index 000000000000..1f0f5757f9e1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml @@ -0,0 +1,132 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,msm8226-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. MSM8226 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + MSM8226 platform. + +properties: + compatible: + const: qcom,msm8226-pinctrl + + reg: + description: Specifies the base address and size of the TLMM register space + maxItems: 1 + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: Specifies the PIN numbers and Flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + gpio-reserved-ranges: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: "/schemas/pinctrl/pincfg-node.yaml" + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$" + - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. Functions are only valid for gpio pins. + enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5, + blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c5, blsp_spi1, + blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2, + blsp_uart3, blsp_uart5, cam_mclk0, cam_mclk1, wlan ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + msmgpio: pinctrl@fd510000 { + compatible = "qcom,msm8226-pinctrl"; + reg = <0xfd510000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&msmgpio 0 0 117>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + + serial-pins { + pins = "gpio8", "gpio9"; + function = "blsp_uart3"; + drive-strength = <8>; + bias-disable; + }; + }; From db436a7198a78d8d02178dc992ad5ae2de57cd2e Mon Sep 17 00:00:00 2001 From: Bartosz Dudziak Date: Thu, 16 Jul 2020 22:55:29 +0200 Subject: [PATCH 13/78] pinctrl: qcom: Add msm8226 pinctrl driver. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial Qualcomm msm8226 pinctrl driver to support pin configuration with pinctrl framework for msm8226 SoC. - Initial formatting and style was taken from the msm8x74 pinctrl driver added by Björn Andersson Signed-off-by: Bartosz Dudziak Link: https://lore.kernel.org/r/20200716205530.22910-3-bartosz.dudziak@snejp.pl Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-msm8226.c | 630 +++++++++++++++++++++++++ 3 files changed, 640 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8226.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index f8ff30cdafa6..5fe7b8aaf69d 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -62,6 +62,15 @@ config PINCTRL_IPQ6018 Qualcomm Technologies Inc. IPQ6018 platform. Select this for IPQ6018. +config PINCTRL_MSM8226 + tristate "Qualcomm 8226 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc MSM8226 platform. + config PINCTRL_MSM8660 tristate "Qualcomm 8660 pin controller driver" depends on GPIOLIB && OF diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 061ec9fb659b..9e3d9c91a444 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o obj-$(CONFIG_PINCTRL_IPQ6018) += pinctrl-ipq6018.o +obj-$(CONFIG_PINCTRL_MSM8226) += pinctrl-msm8226.o obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o obj-$(CONFIG_PINCTRL_MSM8960) += pinctrl-msm8960.o obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c new file mode 100644 index 000000000000..98779e62e951 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c @@ -0,0 +1,630 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const struct pinctrl_pin_desc msm8226_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + + PINCTRL_PIN(117, "SDC1_CLK"), + PINCTRL_PIN(118, "SDC1_CMD"), + PINCTRL_PIN(119, "SDC1_DATA"), + PINCTRL_PIN(120, "SDC2_CLK"), + PINCTRL_PIN(121, "SDC2_CMD"), + PINCTRL_PIN(122, "SDC2_DATA"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); + +static const unsigned int sdc1_clk_pins[] = { 117 }; +static const unsigned int sdc1_cmd_pins[] = { 118 }; +static const unsigned int sdc1_data_pins[] = { 119 }; +static const unsigned int sdc2_clk_pins[] = { 120 }; +static const unsigned int sdc2_cmd_pins[] = { 121 }; +static const unsigned int sdc2_data_pins[] = { 122 }; + +#define FUNCTION(fname) \ + [MSM_MUX_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + MSM_MUX_gpio, \ + MSM_MUX_##f1, \ + MSM_MUX_##f2, \ + MSM_MUX_##f3, \ + MSM_MUX_##f4, \ + MSM_MUX_##f5, \ + MSM_MUX_##f6, \ + MSM_MUX_##f7 \ + }, \ + .nfuncs = 8, \ + .ctl_reg = 0x1000 + 0x10 * id, \ + .io_reg = 0x1004 + 0x10 * id, \ + .intr_cfg_reg = 0x1008 + 0x10 * id, \ + .intr_status_reg = 0x100c + 0x10 * id, \ + .intr_target_reg = 0x1008 + 0x10 * id, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 4, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_target_kpss_val = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +/* + * TODO: Add the rest of the possible functions and fill out + * the pingroup table below. + */ +enum msm8226_functions { + MSM_MUX_gpio, + MSM_MUX_cci_i2c0, + MSM_MUX_blsp_i2c1, + MSM_MUX_blsp_i2c2, + MSM_MUX_blsp_i2c3, + MSM_MUX_blsp_i2c5, + MSM_MUX_blsp_spi1, + MSM_MUX_blsp_spi2, + MSM_MUX_blsp_spi3, + MSM_MUX_blsp_spi5, + MSM_MUX_blsp_uart1, + MSM_MUX_blsp_uart2, + MSM_MUX_blsp_uart3, + MSM_MUX_blsp_uart5, + MSM_MUX_blsp_uim1, + MSM_MUX_blsp_uim2, + MSM_MUX_blsp_uim3, + MSM_MUX_blsp_uim5, + MSM_MUX_cam_mclk0, + MSM_MUX_cam_mclk1, + MSM_MUX_wlan, + MSM_MUX_NA, +}; + +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", +}; + +static const char * const blsp_uart1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" }; +static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" }; +static const char * const blsp_spi1_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3" +}; + +static const char * const blsp_uart2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" }; +static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" }; +static const char * const blsp_spi2_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7" +}; + +static const char * const blsp_uart3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" }; +static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" }; +static const char * const blsp_spi3_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const char * const blsp_uart5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const blsp_uim5_groups[] = { "gpio16", "gpio17" }; +static const char * const blsp_i2c5_groups[] = { "gpio18", "gpio19" }; +static const char * const blsp_spi5_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19" +}; + +static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" }; + +static const char * const cam_mclk0_groups[] = { "gpio26" }; +static const char * const cam_mclk1_groups[] = { "gpio27" }; + +static const char * const wlan_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44" +}; + +static const struct msm_function msm8226_functions[] = { + FUNCTION(gpio), + FUNCTION(cci_i2c0), + FUNCTION(blsp_uim1), + FUNCTION(blsp_uim2), + FUNCTION(blsp_uim3), + FUNCTION(blsp_uim5), + FUNCTION(blsp_i2c1), + FUNCTION(blsp_i2c2), + FUNCTION(blsp_i2c3), + FUNCTION(blsp_i2c5), + FUNCTION(blsp_spi1), + FUNCTION(blsp_spi2), + FUNCTION(blsp_spi3), + FUNCTION(blsp_spi5), + FUNCTION(blsp_uart1), + FUNCTION(blsp_uart2), + FUNCTION(blsp_uart3), + FUNCTION(blsp_uart5), + FUNCTION(cam_mclk0), + FUNCTION(cam_mclk1), + FUNCTION(wlan), +}; + +static const struct msm_pingroup msm8226_groups[] = { + PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA), + PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA), + PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA), + PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA), + PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA), + PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA), + PINGROUP(12, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(13, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(14, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(15, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(16, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(17, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA), + PINGROUP(18, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(19, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA), + PINGROUP(20, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(21, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(22, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(23, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(24, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(25, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(26, cam_mclk0, NA, NA, NA, NA, NA, NA), + PINGROUP(27, cam_mclk1, NA, NA, NA, NA, NA, NA), + PINGROUP(28, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(29, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(30, cci_i2c0, NA, NA, NA, NA, NA, NA), + PINGROUP(31, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(32, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(33, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(34, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(35, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(36, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(37, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(38, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(39, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(40, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(41, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(42, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(43, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(44, wlan, NA, NA, NA, NA, NA, NA), + PINGROUP(45, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(46, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(47, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(48, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(49, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(50, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(51, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(52, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(53, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(54, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(55, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(56, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(57, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(58, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(59, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(60, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(61, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(62, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(63, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(64, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(65, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(66, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(67, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(68, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(69, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(70, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(71, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(72, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(73, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(74, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(75, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(76, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(77, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(78, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(79, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(80, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(81, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(82, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(83, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(84, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(85, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(86, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(87, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(88, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(89, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(90, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(91, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(92, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(93, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(94, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(95, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(96, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(97, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(98, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(99, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(100, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(101, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(102, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(103, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(104, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(105, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(106, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(107, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(108, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(109, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(110, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(111, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(112, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(113, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(114, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(115, NA, NA, NA, NA, NA, NA, NA), + PINGROUP(116, NA, NA, NA, NA, NA, NA, NA), + SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6), + SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3), + SDC_PINGROUP(sdc1_data, 0x2044, 9, 0), + SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6), + SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3), + SDC_PINGROUP(sdc2_data, 0x2048, 9, 0), +}; + +#define NUM_GPIO_PINGROUPS 117 + +static const struct msm_pinctrl_soc_data msm8226_pinctrl = { + .pins = msm8226_pins, + .npins = ARRAY_SIZE(msm8226_pins), + .functions = msm8226_functions, + .nfunctions = ARRAY_SIZE(msm8226_functions), + .groups = msm8226_groups, + .ngroups = ARRAY_SIZE(msm8226_groups), + .ngpios = NUM_GPIO_PINGROUPS, +}; + +static int msm8226_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &msm8226_pinctrl); +} + +static const struct of_device_id msm8226_pinctrl_of_match[] = { + { .compatible = "qcom,msm8226-pinctrl", }, + { }, +}; + +static struct platform_driver msm8226_pinctrl_driver = { + .driver = { + .name = "msm8226-pinctrl", + .of_match_table = msm8226_pinctrl_of_match, + }, + .probe = msm8226_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init msm8226_pinctrl_init(void) +{ + return platform_driver_register(&msm8226_pinctrl_driver); +} +arch_initcall(msm8226_pinctrl_init); + +static void __exit msm8226_pinctrl_exit(void) +{ + platform_driver_unregister(&msm8226_pinctrl_driver); +} +module_exit(msm8226_pinctrl_exit); + +MODULE_AUTHOR("Bartosz Dudziak "); +MODULE_DESCRIPTION("Qualcomm MSM8226 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, msm8226_pinctrl_of_match); From aebebcf910c4d7b6b98bc7b3b573ec24543861a6 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Mon, 3 Aug 2020 17:20:54 +0300 Subject: [PATCH 14/78] dt-bindings: pinctrl: Add bindings for Actions S500 SoC Add pinctrl and gpio bindings for Actions Semi S500 SoC. Signed-off-by: Cristian Ciocaltea Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/7abf618c446b7b648f512afe72e46704156e9912.1596461275.git.cristian.ciocaltea@gmail.com Signed-off-by: Linus Walleij --- .../pinctrl/actions,s500-pinctrl.yaml | 240 ++++++++++++++++++ 1 file changed, 240 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml new file mode 100644 index 000000000000..33391d30c00c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Actions Semi S500 SoC pinmux & GPIO controller + +maintainers: + - Manivannan Sadhasivam + - Cristian Ciocaltea + +description: | + Pinmux & GPIO controller manages pin multiplexing & configuration including + GPIO function selection & GPIO attributes configuration. Please refer to + pinctrl-bindings.txt in this directory for common binding part and usage. + +properties: + compatible: + const: actions,s500-pinctrl + + reg: + items: + - description: GPIO Output + GPIO Input + GPIO Data + - description: Multiplexing Control + - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control + - description: PAD Drive Capacity Select + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + gpio-controller: true + + gpio-ranges: + maxItems: 1 + + '#gpio-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the pin number and flags, as defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + interrupts: + description: + One interrupt per each of the 5 GPIO ports supported by the controller, + sorted by port number ascending order. + minItems: 5 + maxItems: 5 + +patternProperties: + '-pins$': + type: object + patternProperties: + '^(.*-)?pinmux$': + type: object + description: + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + $ref: pinmux-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the functions specified in + this subnode. + items: + oneOf: + - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp, + rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp, + rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp, + i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp, + ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp, + ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp, + dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp, + dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp, + spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp, + dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp, + uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp, + sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp, + uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, + uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, + pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp, + dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp, + nand_ceb3_mfp] + minItems: 1 + maxItems: 32 + + function: + description: + Specify the alternative function to be configured for the + given gpio pin groups. + enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0, + sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, + i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, + p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m, + mipi_csi, nand, spdif, ts, lcd0] + + required: + - groups + - function + + additionalProperties: false + + '^(.*-)?pinconf$': + type: object + description: + Pinctrl node's client devices specify pin configurations using + subnodes, which in turn use the standard properties below. + $ref: pincfg-node.yaml# + + properties: + groups: + description: + List of gpio pin groups affected by the drive-strength property + specified in this subnode. + items: + oneOf: + - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv, + rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv, + smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, + i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, + lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv, + sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv, + spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv, + i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv, + sens0_ckout_drv, uart3_all_drv] + minItems: 1 + maxItems: 32 + + pins: + description: + List of gpio pins affected by the bias-pull-* and + input-schmitt-* properties specified in this subnode. + items: + oneOf: + - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen, + eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk, + eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0, + i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, + i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1, + ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp, + lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep, + lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp, + lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3, + dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0, + dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0, + sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk, + spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx, + uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk, + sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, + dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb, + uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb, + pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk, + i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0, + csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3, + csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3, + dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb, + dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1, + pkg2, pkg3] + minItems: 1 + maxItems: 64 + + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: + Selects the drive strength for the specified pins, in mA. + enum: [2, 4, 8, 12] + + input-schmitt-enable: true + input-schmitt-disable: true + + additionalProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - clocks + - gpio-controller + - gpio-ranges + - '#gpio-cells' + - interrupt-controller + - '#interrupt-cells' + - interrupts + +additionalProperties: false + +examples: + - | + #include + pinctrl: pinctrl@b01b0000 { + compatible = "actions,s500-pinctrl"; + reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>, + <0xb01b0060 0x18>, <0xb01b0080 0xc>; + clocks = <&cmu 55>; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 132>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + , + ; + + mmc0_pins: mmc0-pins { + pinmux { + groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp", + "sd0_cmd_mfp", "sd0_clk_mfp"; + function = "sd0"; + }; + + drv-pinconf { + groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv"; + drive-strength = <8>; + }; + + bias-pinconf { + pins = "sd0_d0", "sd0_d1", "sd0_d2", + "sd0_d3", "sd0_cmd"; + bias-pull-up; + }; + }; + }; + +... From 45de28e31a6e250cd9e17c8b9f9db5a439fb39b2 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Mon, 3 Aug 2020 17:20:55 +0300 Subject: [PATCH 15/78] pinctrl: actions: Add Actions S500 pinctrl driver Add pinctrl and gpio driver for Actions Semi S500 SoC. The driver supports pinctrl, pinmux, pinconf, gpio and interrupt functions using a set of registers shared between gpio and pinctrl. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/ce11c15f2f72798a8d740f8a7d5cbf1e6d70974a.1596461275.git.cristian.ciocaltea@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/Kconfig | 6 + drivers/pinctrl/actions/Makefile | 1 + drivers/pinctrl/actions/pinctrl-s500.c | 1727 ++++++++++++++++++++++++ 3 files changed, 1734 insertions(+) create mode 100644 drivers/pinctrl/actions/pinctrl-s500.c diff --git a/drivers/pinctrl/actions/Kconfig b/drivers/pinctrl/actions/Kconfig index 966f1c2c89d6..a1d16e8280e5 100644 --- a/drivers/pinctrl/actions/Kconfig +++ b/drivers/pinctrl/actions/Kconfig @@ -10,6 +10,12 @@ config PINCTRL_OWL help Say Y here to enable Actions Semi OWL pinctrl driver +config PINCTRL_S500 + bool "Actions Semi S500 pinctrl driver" + depends on PINCTRL_OWL + help + Say Y here to enable Actions Semi S500 pinctrl driver + config PINCTRL_S700 bool "Actions Semi S700 pinctrl driver" depends on PINCTRL_OWL diff --git a/drivers/pinctrl/actions/Makefile b/drivers/pinctrl/actions/Makefile index 61aa9107a43a..b9e2c527c9d3 100644 --- a/drivers/pinctrl/actions/Makefile +++ b/drivers/pinctrl/actions/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PINCTRL_OWL) += pinctrl-owl.o +obj-$(CONFIG_PINCTRL_S500) += pinctrl-s500.o obj-$(CONFIG_PINCTRL_S700) += pinctrl-s700.o obj-$(CONFIG_PINCTRL_S900) += pinctrl-s900.o diff --git a/drivers/pinctrl/actions/pinctrl-s500.c b/drivers/pinctrl/actions/pinctrl-s500.c new file mode 100644 index 000000000000..38e30914af6e --- /dev/null +++ b/drivers/pinctrl/actions/pinctrl-s500.c @@ -0,0 +1,1727 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Actions Semi S500 SoC Pinctrl driver + * + * Copyright (c) 2014 Actions Semi Inc. + * Copyright (c) 2020 Cristian Ciocaltea + */ + +#include +#include +#include +#include +#include +#include "pinctrl-owl.h" + +/* Pinctrl registers offset */ +#define MFCTL0 (0x0040) +#define MFCTL1 (0x0044) +#define MFCTL2 (0x0048) +#define MFCTL3 (0x004C) +#define PAD_PULLCTL0 (0x0060) +#define PAD_PULLCTL1 (0x0064) +#define PAD_PULLCTL2 (0x0068) +#define PAD_ST0 (0x006C) +#define PAD_ST1 (0x0070) +#define PAD_CTL (0x0074) +#define PAD_DRV0 (0x0080) +#define PAD_DRV1 (0x0084) +#define PAD_DRV2 (0x0088) + +#define _GPIOA(offset) (offset) +#define _GPIOB(offset) (32 + (offset)) +#define _GPIOC(offset) (64 + (offset)) +#define _GPIOD(offset) (96 + (offset)) +#define _GPIOE(offset) (128 + (offset)) + +#define NUM_GPIOS (_GPIOE(3) + 1) +#define _PIN(offset) (NUM_GPIOS + (offset)) + +#define DNAND_DQS _GPIOA(12) +#define DNAND_DQSN _GPIOA(13) +#define ETH_TXD0 _GPIOA(14) +#define ETH_TXD1 _GPIOA(15) +#define ETH_TXEN _GPIOA(16) +#define ETH_RXER _GPIOA(17) +#define ETH_CRS_DV _GPIOA(18) +#define ETH_RXD1 _GPIOA(19) +#define ETH_RXD0 _GPIOA(20) +#define ETH_REF_CLK _GPIOA(21) +#define ETH_MDC _GPIOA(22) +#define ETH_MDIO _GPIOA(23) +#define SIRQ0 _GPIOA(24) +#define SIRQ1 _GPIOA(25) +#define SIRQ2 _GPIOA(26) +#define I2S_D0 _GPIOA(27) +#define I2S_BCLK0 _GPIOA(28) +#define I2S_LRCLK0 _GPIOA(29) +#define I2S_MCLK0 _GPIOA(30) +#define I2S_D1 _GPIOA(31) + +#define I2S_BCLK1 _GPIOB(0) +#define I2S_LRCLK1 _GPIOB(1) +#define I2S_MCLK1 _GPIOB(2) +#define KS_IN0 _GPIOB(3) +#define KS_IN1 _GPIOB(4) +#define KS_IN2 _GPIOB(5) +#define KS_IN3 _GPIOB(6) +#define KS_OUT0 _GPIOB(7) +#define KS_OUT1 _GPIOB(8) +#define KS_OUT2 _GPIOB(9) +#define LVDS_OEP _GPIOB(10) +#define LVDS_OEN _GPIOB(11) +#define LVDS_ODP _GPIOB(12) +#define LVDS_ODN _GPIOB(13) +#define LVDS_OCP _GPIOB(14) +#define LVDS_OCN _GPIOB(15) +#define LVDS_OBP _GPIOB(16) +#define LVDS_OBN _GPIOB(17) +#define LVDS_OAP _GPIOB(18) +#define LVDS_OAN _GPIOB(19) +#define LVDS_EEP _GPIOB(20) +#define LVDS_EEN _GPIOB(21) +#define LVDS_EDP _GPIOB(22) +#define LVDS_EDN _GPIOB(23) +#define LVDS_ECP _GPIOB(24) +#define LVDS_ECN _GPIOB(25) +#define LVDS_EBP _GPIOB(26) +#define LVDS_EBN _GPIOB(27) +#define LVDS_EAP _GPIOB(28) +#define LVDS_EAN _GPIOB(29) +#define LCD0_D18 _GPIOB(30) +#define LCD0_D17 _GPIOB(31) + +#define DSI_DP3 _GPIOC(0) +#define DSI_DN3 _GPIOC(1) +#define DSI_DP1 _GPIOC(2) +#define DSI_DN1 _GPIOC(3) +#define DSI_CP _GPIOC(4) +#define DSI_CN _GPIOC(5) +#define DSI_DP0 _GPIOC(6) +#define DSI_DN0 _GPIOC(7) +#define DSI_DP2 _GPIOC(8) +#define DSI_DN2 _GPIOC(9) +#define SD0_D0 _GPIOC(10) +#define SD0_D1 _GPIOC(11) +#define SD0_D2 _GPIOC(12) +#define SD0_D3 _GPIOC(13) +#define SD1_D0 _GPIOC(14) /* SD0_D4 */ +#define SD1_D1 _GPIOC(15) /* SD0_D5 */ +#define SD1_D2 _GPIOC(16) /* SD0_D6 */ +#define SD1_D3 _GPIOC(17) /* SD0_D7 */ +#define SD0_CMD _GPIOC(18) +#define SD0_CLK _GPIOC(19) +#define SD1_CMD _GPIOC(20) +#define SD1_CLK _GPIOC(21) +#define SPI0_SCLK _GPIOC(22) +#define SPI0_SS _GPIOC(23) +#define SPI0_MISO _GPIOC(24) +#define SPI0_MOSI _GPIOC(25) +#define UART0_RX _GPIOC(26) +#define UART0_TX _GPIOC(27) +#define I2C0_SCLK _GPIOC(28) +#define I2C0_SDATA _GPIOC(29) +#define SENSOR0_PCLK _GPIOC(31) + +#define SENSOR0_CKOUT _GPIOD(10) +#define DNAND_ALE _GPIOD(12) +#define DNAND_CLE _GPIOD(13) +#define DNAND_CEB0 _GPIOD(14) +#define DNAND_CEB1 _GPIOD(15) +#define DNAND_CEB2 _GPIOD(16) +#define DNAND_CEB3 _GPIOD(17) +#define UART2_RX _GPIOD(18) +#define UART2_TX _GPIOD(19) +#define UART2_RTSB _GPIOD(20) +#define UART2_CTSB _GPIOD(21) +#define UART3_RX _GPIOD(22) +#define UART3_TX _GPIOD(23) +#define UART3_RTSB _GPIOD(24) +#define UART3_CTSB _GPIOD(25) +#define PCM1_IN _GPIOD(28) +#define PCM1_CLK _GPIOD(29) +#define PCM1_SYNC _GPIOD(30) +#define PCM1_OUT _GPIOD(31) + +#define I2C1_SCLK _GPIOE(0) +#define I2C1_SDATA _GPIOE(1) +#define I2C2_SCLK _GPIOE(2) +#define I2C2_SDATA _GPIOE(3) + +#define CSI_DN0 _PIN(0) +#define CSI_DP0 _PIN(1) +#define CSI_DN1 _PIN(2) +#define CSI_DP1 _PIN(3) +#define CSI_CN _PIN(4) +#define CSI_CP _PIN(5) +#define CSI_DN2 _PIN(6) +#define CSI_DP2 _PIN(7) +#define CSI_DN3 _PIN(8) +#define CSI_DP3 _PIN(9) + +#define DNAND_D0 _PIN(10) +#define DNAND_D1 _PIN(11) +#define DNAND_D2 _PIN(12) +#define DNAND_D3 _PIN(13) +#define DNAND_D4 _PIN(14) +#define DNAND_D5 _PIN(15) +#define DNAND_D6 _PIN(16) +#define DNAND_D7 _PIN(17) +#define DNAND_WRB _PIN(18) +#define DNAND_RDB _PIN(19) +#define DNAND_RDBN _PIN(20) +#define DNAND_RB _PIN(21) + +#define PORB _PIN(22) +#define CLKO_25M _PIN(23) +#define BSEL _PIN(24) +#define PKG0 _PIN(25) +#define PKG1 _PIN(26) +#define PKG2 _PIN(27) +#define PKG3 _PIN(28) + +#define _FIRSTPAD _GPIOA(0) +#define _LASTPAD PKG3 +#define NUM_PADS (_PIN(28) + 1) + +static const struct pinctrl_pin_desc s500_pads[] = { + PINCTRL_PIN(DNAND_DQS, "dnand_dqs"), + PINCTRL_PIN(DNAND_DQSN, "dnand_dqsn"), + PINCTRL_PIN(ETH_TXD0, "eth_txd0"), + PINCTRL_PIN(ETH_TXD1, "eth_txd1"), + PINCTRL_PIN(ETH_TXEN, "eth_txen"), + PINCTRL_PIN(ETH_RXER, "eth_rxer"), + PINCTRL_PIN(ETH_CRS_DV, "eth_crs_dv"), + PINCTRL_PIN(ETH_RXD1, "eth_rxd1"), + PINCTRL_PIN(ETH_RXD0, "eth_rxd0"), + PINCTRL_PIN(ETH_REF_CLK, "eth_ref_clk"), + PINCTRL_PIN(ETH_MDC, "eth_mdc"), + PINCTRL_PIN(ETH_MDIO, "eth_mdio"), + PINCTRL_PIN(SIRQ0, "sirq0"), + PINCTRL_PIN(SIRQ1, "sirq1"), + PINCTRL_PIN(SIRQ2, "sirq2"), + PINCTRL_PIN(I2S_D0, "i2s_d0"), + PINCTRL_PIN(I2S_BCLK0, "i2s_bclk0"), + PINCTRL_PIN(I2S_LRCLK0, "i2s_lrclk0"), + PINCTRL_PIN(I2S_MCLK0, "i2s_mclk0"), + PINCTRL_PIN(I2S_D1, "i2s_d1"), + PINCTRL_PIN(I2S_BCLK1, "i2s_bclk1"), + PINCTRL_PIN(I2S_LRCLK1, "i2s_lrclk1"), + PINCTRL_PIN(I2S_MCLK1, "i2s_mclk1"), + PINCTRL_PIN(KS_IN0, "ks_in0"), + PINCTRL_PIN(KS_IN1, "ks_in1"), + PINCTRL_PIN(KS_IN2, "ks_in2"), + PINCTRL_PIN(KS_IN3, "ks_in3"), + PINCTRL_PIN(KS_OUT0, "ks_out0"), + PINCTRL_PIN(KS_OUT1, "ks_out1"), + PINCTRL_PIN(KS_OUT2, "ks_out2"), + PINCTRL_PIN(LVDS_OEP, "lvds_oep"), + PINCTRL_PIN(LVDS_OEN, "lvds_oen"), + PINCTRL_PIN(LVDS_ODP, "lvds_odp"), + PINCTRL_PIN(LVDS_ODN, "lvds_odn"), + PINCTRL_PIN(LVDS_OCP, "lvds_ocp"), + PINCTRL_PIN(LVDS_OCN, "lvds_ocn"), + PINCTRL_PIN(LVDS_OBP, "lvds_obp"), + PINCTRL_PIN(LVDS_OBN, "lvds_obn"), + PINCTRL_PIN(LVDS_OAP, "lvds_oap"), + PINCTRL_PIN(LVDS_OAN, "lvds_oan"), + PINCTRL_PIN(LVDS_EEP, "lvds_eep"), + PINCTRL_PIN(LVDS_EEN, "lvds_een"), + PINCTRL_PIN(LVDS_EDP, "lvds_edp"), + PINCTRL_PIN(LVDS_EDN, "lvds_edn"), + PINCTRL_PIN(LVDS_ECP, "lvds_ecp"), + PINCTRL_PIN(LVDS_ECN, "lvds_ecn"), + PINCTRL_PIN(LVDS_EBP, "lvds_ebp"), + PINCTRL_PIN(LVDS_EBN, "lvds_ebn"), + PINCTRL_PIN(LVDS_EAP, "lvds_eap"), + PINCTRL_PIN(LVDS_EAN, "lvds_ean"), + PINCTRL_PIN(LCD0_D18, "lcd0_d18"), + PINCTRL_PIN(LCD0_D17, "lcd0_d17"), + PINCTRL_PIN(DSI_DP3, "dsi_dp3"), + PINCTRL_PIN(DSI_DN3, "dsi_dn3"), + PINCTRL_PIN(DSI_DP1, "dsi_dp1"), + PINCTRL_PIN(DSI_DN1, "dsi_dn1"), + PINCTRL_PIN(DSI_CP, "dsi_cp"), + PINCTRL_PIN(DSI_CN, "dsi_cn"), + PINCTRL_PIN(DSI_DP0, "dsi_dp0"), + PINCTRL_PIN(DSI_DN0, "dsi_dn0"), + PINCTRL_PIN(DSI_DP2, "dsi_dp2"), + PINCTRL_PIN(DSI_DN2, "dsi_dn2"), + PINCTRL_PIN(SD0_D0, "sd0_d0"), + PINCTRL_PIN(SD0_D1, "sd0_d1"), + PINCTRL_PIN(SD0_D2, "sd0_d2"), + PINCTRL_PIN(SD0_D3, "sd0_d3"), + PINCTRL_PIN(SD1_D0, "sd1_d0"), + PINCTRL_PIN(SD1_D1, "sd1_d1"), + PINCTRL_PIN(SD1_D2, "sd1_d2"), + PINCTRL_PIN(SD1_D3, "sd1_d3"), + PINCTRL_PIN(SD0_CMD, "sd0_cmd"), + PINCTRL_PIN(SD0_CLK, "sd0_clk"), + PINCTRL_PIN(SD1_CMD, "sd1_cmd"), + PINCTRL_PIN(SD1_CLK, "sd1_clk"), + PINCTRL_PIN(SPI0_SCLK, "spi0_sclk"), + PINCTRL_PIN(SPI0_SS, "spi0_ss"), + PINCTRL_PIN(SPI0_MISO, "spi0_miso"), + PINCTRL_PIN(SPI0_MOSI, "spi0_mosi"), + PINCTRL_PIN(UART0_RX, "uart0_rx"), + PINCTRL_PIN(UART0_TX, "uart0_tx"), + PINCTRL_PIN(I2C0_SCLK, "i2c0_sclk"), + PINCTRL_PIN(I2C0_SDATA, "i2c0_sdata"), + PINCTRL_PIN(SENSOR0_PCLK, "sensor0_pclk"), + PINCTRL_PIN(SENSOR0_CKOUT, "sensor0_ckout"), + PINCTRL_PIN(DNAND_ALE, "dnand_ale"), + PINCTRL_PIN(DNAND_CLE, "dnand_cle"), + PINCTRL_PIN(DNAND_CEB0, "dnand_ceb0"), + PINCTRL_PIN(DNAND_CEB1, "dnand_ceb1"), + PINCTRL_PIN(DNAND_CEB2, "dnand_ceb2"), + PINCTRL_PIN(DNAND_CEB3, "dnand_ceb3"), + PINCTRL_PIN(UART2_RX, "uart2_rx"), + PINCTRL_PIN(UART2_TX, "uart2_tx"), + PINCTRL_PIN(UART2_RTSB, "uart2_rtsb"), + PINCTRL_PIN(UART2_CTSB, "uart2_ctsb"), + PINCTRL_PIN(UART3_RX, "uart3_rx"), + PINCTRL_PIN(UART3_TX, "uart3_tx"), + PINCTRL_PIN(UART3_RTSB, "uart3_rtsb"), + PINCTRL_PIN(UART3_CTSB, "uart3_ctsb"), + PINCTRL_PIN(PCM1_IN, "pcm1_in"), + PINCTRL_PIN(PCM1_CLK, "pcm1_clk"), + PINCTRL_PIN(PCM1_SYNC, "pcm1_sync"), + PINCTRL_PIN(PCM1_OUT, "pcm1_out"), + PINCTRL_PIN(I2C1_SCLK, "i2c1_sclk"), + PINCTRL_PIN(I2C1_SDATA, "i2c1_sdata"), + PINCTRL_PIN(I2C2_SCLK, "i2c2_sclk"), + PINCTRL_PIN(I2C2_SDATA, "i2c2_sdata"), + PINCTRL_PIN(CSI_DN0, "csi_dn0"), + PINCTRL_PIN(CSI_DP0, "csi_dp0"), + PINCTRL_PIN(CSI_DN1, "csi_dn1"), + PINCTRL_PIN(CSI_DP1, "csi_dp1"), + PINCTRL_PIN(CSI_DN2, "csi_dn2"), + PINCTRL_PIN(CSI_DP2, "csi_dp2"), + PINCTRL_PIN(CSI_DN3, "csi_dn3"), + PINCTRL_PIN(CSI_DP3, "csi_dp3"), + PINCTRL_PIN(CSI_CN, "csi_cn"), + PINCTRL_PIN(CSI_CP, "csi_cp"), + PINCTRL_PIN(DNAND_D0, "dnand_d0"), + PINCTRL_PIN(DNAND_D1, "dnand_d1"), + PINCTRL_PIN(DNAND_D2, "dnand_d2"), + PINCTRL_PIN(DNAND_D3, "dnand_d3"), + PINCTRL_PIN(DNAND_D4, "dnand_d4"), + PINCTRL_PIN(DNAND_D5, "dnand_d5"), + PINCTRL_PIN(DNAND_D6, "dnand_d6"), + PINCTRL_PIN(DNAND_D7, "dnand_d7"), + PINCTRL_PIN(DNAND_RB, "dnand_rb"), + PINCTRL_PIN(DNAND_RDB, "dnand_rdb"), + PINCTRL_PIN(DNAND_RDBN, "dnand_rdbn"), + PINCTRL_PIN(DNAND_WRB, "dnand_wrb"), + PINCTRL_PIN(PORB, "porb"), + PINCTRL_PIN(CLKO_25M, "clko_25m"), + PINCTRL_PIN(BSEL, "bsel"), + PINCTRL_PIN(PKG0, "pkg0"), + PINCTRL_PIN(PKG1, "pkg1"), + PINCTRL_PIN(PKG2, "pkg2"), + PINCTRL_PIN(PKG3, "pkg3"), +}; + +enum s500_pinmux_functions { + S500_MUX_NOR, + S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI0, + S500_MUX_SPI1, + S500_MUX_SPI2, + S500_MUX_SPI3, + S500_MUX_SENS0, + S500_MUX_SENS1, + S500_MUX_UART0, + S500_MUX_UART1, + S500_MUX_UART2, + S500_MUX_UART3, + S500_MUX_UART4, + S500_MUX_UART5, + S500_MUX_UART6, + S500_MUX_I2S0, + S500_MUX_I2S1, + S500_MUX_PCM1, + S500_MUX_PCM0, + S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_PWM0, + S500_MUX_PWM1, + S500_MUX_PWM2, + S500_MUX_PWM3, + S500_MUX_PWM4, + S500_MUX_PWM5, + S500_MUX_P0, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_SD2, + S500_MUX_I2C0, + S500_MUX_I2C1, + /*S500_MUX_I2C2,*/ + S500_MUX_I2C3, + S500_MUX_DSI, + S500_MUX_LVDS, + S500_MUX_USB30, + S500_MUX_CLKO_25M, + S500_MUX_MIPI_CSI, + S500_MUX_NAND, + S500_MUX_SPDIF, + /*S500_MUX_SIRQ0,*/ + /*S500_MUX_SIRQ1,*/ + /*S500_MUX_SIRQ2,*/ + S500_MUX_TS, + S500_MUX_LCD0, + S500_MUX_RESERVED, +}; + +/* MFPCTL group data */ +/* mfp0_31_26 reserved */ +/* mfp0_25_23 */ +static unsigned int lcd0_d18_mfp_pads[] = { LCD0_D18 }; +static unsigned int lcd0_d18_mfp_funcs[] = { S500_MUX_NOR, + S500_MUX_SENS1, + S500_MUX_PWM2, + S500_MUX_PWM4, + S500_MUX_LCD0 }; +/* mfp0_22_20 */ +static unsigned int rmii_crs_dv_mfp_pads[] = { ETH_CRS_DV }; +static unsigned int rmii_crs_dv_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART4, + S500_MUX_PWM4 }; +/* mfp0_18_16_eth_txd0 */ +static unsigned int rmii_txd0_mfp_pads[] = { ETH_TXD0 }; +static unsigned int rmii_txd0_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART6, + S500_MUX_PWM4 }; +/* mfp0_18_16_eth_txd1 */ +static unsigned int rmii_txd1_mfp_pads[] = { ETH_TXD1 }; +static unsigned int rmii_txd1_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_ETH_SMII, + S500_MUX_SPI2, + S500_MUX_UART6, + S500_MUX_PWM5 }; +/* mfp0_15_13_rmii_txen */ +static unsigned int rmii_txen_mfp_pads[] = { ETH_TXEN }; +static unsigned int rmii_txen_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM0 }; +/* mfp0_15_13_rmii_rxen */ +static unsigned int rmii_rxen_mfp_pads[] = { ETH_RXER }; +static unsigned int rmii_rxen_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM1 }; +/* mfp0_12_11 reserved */ + +/* mfp0_10_8_rmii_rxd1 */ +static unsigned int rmii_rxd1_mfp_pads[] = { ETH_RXD1 }; +static unsigned int rmii_rxd1_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM2, + S500_MUX_UART5 }; +/* mfp0_10_8_rmii_rxd0 */ +static unsigned int rmii_rxd0_mfp_pads[] = { ETH_RXD0 }; +static unsigned int rmii_rxd0_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART2, + S500_MUX_SPI3, + S500_MUX_PWM3, + S500_MUX_UART5 }; +/* mfp0_7_6 */ +static unsigned int rmii_ref_clk_mfp_pads[] = { ETH_REF_CLK }; +static unsigned int rmii_ref_clk_mfp_funcs[] = { S500_MUX_ETH_RMII, + S500_MUX_UART4, + S500_MUX_SPI2, + S500_MUX_RESERVED, + S500_MUX_ETH_SMII }; +/* mfp0_5 */ +static unsigned int i2s_d0_mfp_pads[] = { I2S_D0 }; +static unsigned int i2s_d0_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR }; +/* mfp0_4_3 */ +static unsigned int i2s_pcm1_mfp_pads[] = { I2S_LRCLK0, I2S_MCLK0 }; +static unsigned int i2s_pcm1_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR, + S500_MUX_PCM1 }; +/* mfp0_2_1_i2s0 */ +static unsigned int i2s0_pcm0_mfp_pads[] = { I2S_BCLK0 }; +static unsigned int i2s0_pcm0_mfp_funcs[] = { S500_MUX_I2S0, + S500_MUX_NOR, + S500_MUX_PCM0 }; +/* mfp0_2_1_i2s1 */ +static unsigned int i2s1_pcm0_mfp_pads[] = { I2S_BCLK1, I2S_LRCLK1, + I2S_MCLK1 }; +static unsigned int i2s1_pcm0_mfp_funcs[] = { S500_MUX_I2S1, + S500_MUX_NOR, + S500_MUX_PCM0 }; +/* mfp0_0 */ +static unsigned int i2s_d1_mfp_pads[] = { I2S_D1 }; +static unsigned int i2s_d1_mfp_funcs[] = { S500_MUX_I2S1, + S500_MUX_NOR }; +/* mfp1_31_29_ks_in0 */ +static unsigned int ks_in0_mfp_pads[] = { KS_IN0 }; +static unsigned int ks_in0_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM0, + S500_MUX_PWM4, + S500_MUX_SENS1, + S500_MUX_PWM4, + S500_MUX_P0 }; +/* mfp1_31_29_ks_in1 */ +static unsigned int ks_in1_mfp_pads[] = { KS_IN1 }; +static unsigned int ks_in1_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM1, + S500_MUX_PWM5, + S500_MUX_SENS1, + S500_MUX_PWM1, + S500_MUX_USB30 }; +/* mfp1_31_29_ks_in2 */ +static unsigned int ks_in2_mfp_pads[] = { KS_IN2 }; +static unsigned int ks_in2_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM0, + S500_MUX_PWM0, + S500_MUX_SENS1, + S500_MUX_PWM0, + S500_MUX_P0 }; +/* mfp1_28_26_ks_in3 */ +static unsigned int ks_in3_mfp_pads[] = { KS_IN3 }; +static unsigned int ks_in3_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM1, + S500_MUX_RESERVED, + S500_MUX_SENS1 }; +/* mfp1_28_26_ks_out0 */ +static unsigned int ks_out0_mfp_pads[] = { KS_OUT0 }; +static unsigned int ks_out0_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_UART5, + S500_MUX_NOR, + S500_MUX_PWM2, + S500_MUX_RESERVED, + S500_MUX_SENS1, + S500_MUX_SD0 }; +/* mfp1_28_26_ks_out1 */ +static unsigned int ks_out1_mfp_pads[] = { KS_OUT1 }; +static unsigned int ks_out1_mfp_funcs[] = { S500_MUX_KS, + S500_MUX_JTAG, + S500_MUX_NOR, + S500_MUX_PWM3, + S500_MUX_RESERVED, + S500_MUX_SENS1, + S500_MUX_SD0 }; +/* mfp1_25_23 */ +static unsigned int ks_out2_mfp_pads[] = { KS_OUT2 }; +static unsigned int ks_out2_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_KS, + S500_MUX_NOR, + S500_MUX_PWM2, + S500_MUX_UART5, + S500_MUX_SENS1 }; +/* mfp1_22_21 */ +static unsigned int lvds_o_pn_mfp_pads[] = { LVDS_OEP, LVDS_OEN, + LVDS_ODP, LVDS_ODN, + LVDS_OCP, LVDS_OCN, + LVDS_OBP, LVDS_OBN, + LVDS_OAP, LVDS_OAN }; +static unsigned int lvds_o_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_TS, + S500_MUX_LCD0 }; +/* mfp1_20_19 */ +static unsigned int dsi_dn0_mfp_pads[] = { DSI_DN0 }; +static unsigned int dsi_dn0_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp1_18_17 */ +static unsigned int dsi_dp2_mfp_pads[] = { DSI_DP2 }; +static unsigned int dsi_dp2_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_UART2, + S500_MUX_SPI0, + S500_MUX_SD1 }; +/* mfp1_16_14 */ +static unsigned int lcd0_d17_mfp_pads[] = { LCD0_D17 }; +static unsigned int lcd0_d17_mfp_funcs[] = { S500_MUX_NOR, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_PWM3, + S500_MUX_LCD0 }; +/* mfp1_13_12 */ +static unsigned int dsi_dp3_mfp_pads[] = { DSI_DP3 }; +static unsigned int dsi_dp3_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_SD0, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp1_11_10 */ +static unsigned int dsi_dn3_mfp_pads[] = { DSI_DN3 }; +static unsigned int dsi_dn3_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp1_9_7 */ +static unsigned int dsi_dp0_mfp_pads[] = { DSI_DP0 }; +static unsigned int dsi_dp0_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD0, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp1_6_5 */ +static unsigned int lvds_ee_pn_mfp_pads[] = { LVDS_EEP, LVDS_EEN }; +static unsigned int lvds_ee_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_NOR, + S500_MUX_TS, + S500_MUX_LCD0 }; +/* mfp1_4_3 */ +static unsigned int spi0_i2c_pcm_mfp_pads[] = { SPI0_SCLK, SPI0_MOSI }; +static unsigned int spi0_i2c_pcm_mfp_funcs[] = { S500_MUX_SPI0, + S500_MUX_NOR, + S500_MUX_I2C3, + S500_MUX_PCM0 }; +/* mfp1_2_0 */ +static unsigned int spi0_i2s_pcm_mfp_pads[] = { SPI0_SS, SPI0_MISO }; +static unsigned int spi0_i2s_pcm_mfp_funcs[] = { S500_MUX_SPI0, + S500_MUX_NOR, + S500_MUX_I2S1, + S500_MUX_PCM1, + S500_MUX_PCM0 }; +/* mfp2_31 reserved */ +/* mfp2_30_29 */ +static unsigned int dsi_dnp1_cp_mfp_pads[] = { DSI_DP1, DSI_CP, DSI_CN }; +static unsigned int dsi_dnp1_cp_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_SD1, + S500_MUX_LCD0 }; +/* mfp2_28_27 */ +static unsigned int lvds_e_pn_mfp_pads[] = { LVDS_EDP, LVDS_EDN, + LVDS_ECP, LVDS_ECN, + LVDS_EBP, LVDS_EBN, + LVDS_EAP, LVDS_EAN }; +static unsigned int lvds_e_pn_mfp_funcs[] = { S500_MUX_LVDS, + S500_MUX_NOR, + S500_MUX_LCD0 }; +/* mfp2_26_24 */ +static unsigned int dsi_dn2_mfp_pads[] = { DSI_DN2 }; +static unsigned int dsi_dn2_mfp_funcs[] = { S500_MUX_DSI, + S500_MUX_RESERVED, + S500_MUX_SD1, + S500_MUX_UART2, + S500_MUX_SPI0 }; +/* mfp2_23 */ +static unsigned int uart2_rtsb_mfp_pads[] = { UART2_RTSB }; +static unsigned int uart2_rtsb_mfp_funcs[] = { S500_MUX_UART2, + S500_MUX_UART0 }; +/* mfp2_22 */ +static unsigned int uart2_ctsb_mfp_pads[] = { UART2_CTSB }; +static unsigned int uart2_ctsb_mfp_funcs[] = { S500_MUX_UART2, + S500_MUX_UART0 }; +/* mfp2_21 */ +static unsigned int uart3_rtsb_mfp_pads[] = { UART3_RTSB }; +static unsigned int uart3_rtsb_mfp_funcs[] = { S500_MUX_UART3, + S500_MUX_UART5 }; +/* mfp2_20 */ +static unsigned int uart3_ctsb_mfp_pads[] = { UART3_CTSB }; +static unsigned int uart3_ctsb_mfp_funcs[] = { S500_MUX_UART3, + S500_MUX_UART5 }; +/* mfp2_19_17 */ +static unsigned int sd0_d0_mfp_pads[] = { SD0_D0 }; +static unsigned int sd0_d0_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG, + S500_MUX_UART2, + S500_MUX_UART5 }; +/* mfp2_16_14 */ +static unsigned int sd0_d1_mfp_pads[] = { SD0_D1 }; +static unsigned int sd0_d1_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_RESERVED, + S500_MUX_UART2, + S500_MUX_UART5 }; +/* mfp2_13_11 */ +static unsigned int sd0_d2_d3_mfp_pads[] = { SD0_D2, SD0_D3 }; +static unsigned int sd0_d2_d3_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG, + S500_MUX_UART2, + S500_MUX_UART1 }; +/* mfp2_10_9 */ +static unsigned int sd1_d0_d3_mfp_pads[] = { SD1_D0, SD1_D1, + SD1_D2, SD1_D3 }; +static unsigned int sd1_d0_d3_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_SD1 }; +/* mfp2_8_7 */ +static unsigned int sd0_cmd_mfp_pads[] = { SD0_CMD }; +static unsigned int sd0_cmd_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_NOR, + S500_MUX_RESERVED, + S500_MUX_JTAG }; +/* mfp2_6_5 */ +static unsigned int sd0_clk_mfp_pads[] = { SD0_CLK }; +static unsigned int sd0_clk_mfp_funcs[] = { S500_MUX_SD0, + S500_MUX_RESERVED, + S500_MUX_JTAG }; +/* mfp2_4_3 */ +static unsigned int sd1_cmd_mfp_pads[] = { SD1_CMD }; +static unsigned int sd1_cmd_mfp_funcs[] = { S500_MUX_SD1, + S500_MUX_NOR }; +/* mfp2_2_0 */ +static unsigned int uart0_rx_mfp_pads[] = { UART0_RX }; +static unsigned int uart0_rx_mfp_funcs[] = { S500_MUX_UART0, + S500_MUX_UART2, + S500_MUX_SPI1, + S500_MUX_I2C0, + S500_MUX_PCM1, + S500_MUX_I2S1 }; +/* mfp3_31 reserved */ +/* mfp3_30 */ +static unsigned int clko_25m_mfp_pads[] = { CLKO_25M }; +static unsigned int clko_25m_mfp_funcs[] = { S500_MUX_RESERVED, + S500_MUX_CLKO_25M }; +/* mfp3_29_28 */ +static unsigned int csi_cn_cp_mfp_pads[] = { CSI_CN, CSI_CP }; +static unsigned int csi_cn_cp_mfp_funcs[] = { S500_MUX_MIPI_CSI, + S500_MUX_SENS0 }; +/* mfp3_27_24 reserved */ +/* mfp3_23_22 */ +static unsigned int sens0_ckout_mfp_pads[] = { SENSOR0_CKOUT }; +static unsigned int sens0_ckout_mfp_funcs[] = { S500_MUX_SENS0, + S500_MUX_NOR, + S500_MUX_SENS1, + S500_MUX_PWM1 }; +/* mfp3_21_19 */ +static unsigned int uart0_tx_mfp_pads[] = { UART0_TX }; +static unsigned int uart0_tx_mfp_funcs[] = { S500_MUX_UART0, + S500_MUX_UART2, + S500_MUX_SPI1, + S500_MUX_I2C0, + S500_MUX_SPDIF, + S500_MUX_PCM1, + S500_MUX_I2S1 }; +/* mfp3_18_16 */ +static unsigned int i2c0_mfp_pads[] = { I2C0_SCLK, + I2C0_SDATA }; +static unsigned int i2c0_mfp_funcs[] = { S500_MUX_I2C0, + S500_MUX_UART2, + S500_MUX_I2C1, + S500_MUX_UART1, + S500_MUX_SPI1 }; +/* mfp3_15_14 */ +static unsigned int csi_dn_dp_mfp_pads[] = { CSI_DN0, CSI_DN1, + CSI_DN2, CSI_DN3, + CSI_DP0, CSI_DP1, + CSI_DP2, CSI_DP3 }; +static unsigned int csi_dn_dp_mfp_funcs[] = { S500_MUX_MIPI_CSI, + S500_MUX_SENS0 }; +/* mfp3_13_12 */ +static unsigned int sen0_pclk_mfp_pads[] = { SENSOR0_PCLK }; +static unsigned int sen0_pclk_mfp_funcs[] = { S500_MUX_SENS0, + S500_MUX_NOR, + S500_MUX_PWM0 }; +/* mfp3_11_10 */ +static unsigned int pcm1_in_mfp_pads[] = { PCM1_IN }; +static unsigned int pcm1_in_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART4, + S500_MUX_PWM4 }; +/* mfp3_9_8 */ +static unsigned int pcm1_clk_mfp_pads[] = { PCM1_CLK }; +static unsigned int pcm1_clk_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART4, + S500_MUX_PWM5 }; +/* mfp3_7_6 */ +static unsigned int pcm1_sync_mfp_pads[] = { PCM1_SYNC }; +static unsigned int pcm1_sync_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART6, + S500_MUX_I2C3 }; +/* mfp3_5_4 */ +static unsigned int pcm1_out_mfp_pads[] = { PCM1_OUT }; +static unsigned int pcm1_out_mfp_funcs[] = { S500_MUX_PCM1, + S500_MUX_SENS1, + S500_MUX_UART6, + S500_MUX_I2C3 }; +/* mfp3_3 */ +static unsigned int dnand_data_wr_mfp_pads[] = { DNAND_D0, DNAND_D1, + DNAND_D2, DNAND_D3, + DNAND_D4, DNAND_D5, + DNAND_D6, DNAND_D7, + DNAND_RDB, DNAND_RDBN }; +static unsigned int dnand_data_wr_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_SD2 }; +/* mfp3_2 */ +static unsigned int dnand_acle_ce0_mfp_pads[] = { DNAND_ALE, + DNAND_CLE, + DNAND_CEB0, + DNAND_CEB1 }; +static unsigned int dnand_acle_ce0_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_SPI2 }; +/* mfp3_1_0_nand_ceb2 */ +static unsigned int nand_ceb2_mfp_pads[] = { DNAND_CEB2 }; +static unsigned int nand_ceb2_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_PWM5 }; +/* mfp3_1_0_nand_ceb3 */ +static unsigned int nand_ceb3_mfp_pads[] = { DNAND_CEB3 }; +static unsigned int nand_ceb3_mfp_funcs[] = { S500_MUX_NAND, + S500_MUX_PWM4 }; + +/* PADDRV group data */ +/* paddrv0_29_28 */ +static unsigned int sirq_drv_pads[] = { SIRQ0, SIRQ1, SIRQ2 }; +/* paddrv0_23_22 */ +static unsigned int rmii_txd01_txen_drv_pads[] = { ETH_TXD0, ETH_TXD1, + ETH_TXEN }; +/* paddrv0_21_20 */ +static unsigned int rmii_rxer_drv_pads[] = { ETH_RXER }; +/* paddrv0_19_18 */ +static unsigned int rmii_crs_drv_pads[] = { ETH_CRS_DV }; +/* paddrv0_17_16 */ +static unsigned int rmii_rxd10_drv_pads[] = { ETH_RXD0, ETH_RXD1 }; +/* paddrv0_15_14 */ +static unsigned int rmii_ref_clk_drv_pads[] = { ETH_REF_CLK }; +/* paddrv0_13_12 */ +static unsigned int smi_mdc_mdio_drv_pads[] = { ETH_MDC, ETH_MDIO }; +/* paddrv0_11_10 */ +static unsigned int i2s_d0_drv_pads[] = { I2S_D0 }; +/* paddrv0_9_8 */ +static unsigned int i2s_bclk0_drv_pads[] = { I2S_BCLK0 }; +/* paddrv0_7_6 */ +static unsigned int i2s3_drv_pads[] = { I2S_LRCLK0, I2S_MCLK0, + I2S_D1 }; +/* paddrv0_5_4 */ +static unsigned int i2s13_drv_pads[] = { I2S_BCLK1, I2S_LRCLK1, + I2S_MCLK1 }; +/* paddrv0_3_2 */ +static unsigned int pcm1_drv_pads[] = { PCM1_IN, PCM1_CLK, + PCM1_SYNC, PCM1_OUT }; +/* paddrv0_1_0 */ +static unsigned int ks_in_drv_pads[] = { KS_IN0, KS_IN1, + KS_IN2, KS_IN3 }; +/* paddrv1_31_30 */ +static unsigned int ks_out_drv_pads[] = { KS_OUT0, KS_OUT1, KS_OUT2 }; +/* paddrv1_29_28 */ +static unsigned int lvds_all_drv_pads[] = { LVDS_OEP, LVDS_OEN, + LVDS_ODP, LVDS_ODN, + LVDS_OCP, LVDS_OCN, + LVDS_OBP, LVDS_OBN, + LVDS_OAP, LVDS_OAN, + LVDS_EEP, LVDS_EEN, + LVDS_EDP, LVDS_EDN, + LVDS_ECP, LVDS_ECN, + LVDS_EBP, LVDS_EBN, + LVDS_EAP, LVDS_EAN }; +/* paddrv1_27_26 */ +static unsigned int lcd_dsi_drv_pads[] = { DSI_DP3, DSI_DN3, DSI_DP1, + DSI_DN1, DSI_CP, DSI_CN }; +/* paddrv1_25_24 */ +static unsigned int dsi_drv_pads[] = { DSI_DP0, DSI_DN0, + DSI_DP2, DSI_DN2 }; +/* paddrv1_23_22 */ +static unsigned int sd0_d0_d3_drv_pads[] = { SD0_D0, SD0_D1, + SD0_D2, SD0_D3 }; +/* paddrv1_21_20 */ +static unsigned int sd1_d0_d3_drv_pads[] = { SD1_D0, SD1_D1, + SD1_D2, SD1_D3 }; +/* paddrv1_19_18 */ +static unsigned int sd0_cmd_drv_pads[] = { SD0_CMD }; +/* paddrv1_17_16 */ +static unsigned int sd0_clk_drv_pads[] = { SD0_CLK }; +/* paddrv1_15_14 */ +static unsigned int sd1_cmd_drv_pads[] = { SD1_CMD }; +/* paddrv1_13_12 */ +static unsigned int sd1_clk_drv_pads[] = { SD1_CLK }; +/* paddrv1_11_10 */ +static unsigned int spi0_all_drv_pads[] = { SPI0_SCLK, SPI0_SS, + SPI0_MISO, SPI0_MOSI }; +/* paddrv2_31_30 */ +static unsigned int uart0_rx_drv_pads[] = { UART0_RX }; +/* paddrv2_29_28 */ +static unsigned int uart0_tx_drv_pads[] = { UART0_TX }; +/* paddrv2_27_26 */ +static unsigned int uart2_all_drv_pads[] = { UART2_RX, UART2_TX, + UART2_RTSB, UART2_CTSB }; +/* paddrv2_24_23 */ +static unsigned int i2c0_all_drv_pads[] = { I2C0_SCLK, I2C0_SDATA }; +/* paddrv2_22_21 */ +static unsigned int i2c12_all_drv_pads[] = { I2C1_SCLK, I2C1_SDATA, + I2C2_SCLK, I2C2_SDATA }; +/* paddrv2_19_18 */ +static unsigned int sens0_pclk_drv_pads[] = { SENSOR0_PCLK }; +/* paddrv2_13_12 */ +static unsigned int sens0_ckout_drv_pads[] = { SENSOR0_CKOUT }; +/* paddrv2_3_2 */ +static unsigned int uart3_all_drv_pads[] = { UART3_RX, UART3_TX, + UART3_RTSB, UART3_CTSB }; + +/* Pinctrl groups */ +static const struct owl_pingroup s500_groups[] = { + MUX_PG(lcd0_d18_mfp, 0, 23, 3), + MUX_PG(rmii_crs_dv_mfp, 0, 20, 3), + MUX_PG(rmii_txd0_mfp, 0, 16, 3), + MUX_PG(rmii_txd1_mfp, 0, 16, 3), + MUX_PG(rmii_txen_mfp, 0, 13, 3), + MUX_PG(rmii_rxen_mfp, 0, 13, 3), + MUX_PG(rmii_rxd1_mfp, 0, 8, 3), + MUX_PG(rmii_rxd0_mfp, 0, 8, 3), + MUX_PG(rmii_ref_clk_mfp, 0, 6, 2), + MUX_PG(i2s_d0_mfp, 0, 5, 1), + MUX_PG(i2s_pcm1_mfp, 0, 3, 2), + MUX_PG(i2s0_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s1_pcm0_mfp, 0, 1, 2), + MUX_PG(i2s_d1_mfp, 0, 0, 1), + MUX_PG(ks_in2_mfp, 1, 29, 3), + MUX_PG(ks_in1_mfp, 1, 29, 3), + MUX_PG(ks_in0_mfp, 1, 29, 3), + MUX_PG(ks_in3_mfp, 1, 26, 3), + MUX_PG(ks_out0_mfp, 1, 26, 3), + MUX_PG(ks_out1_mfp, 1, 26, 3), + MUX_PG(ks_out2_mfp, 1, 23, 3), + MUX_PG(lvds_o_pn_mfp, 1, 21, 2), + MUX_PG(dsi_dn0_mfp, 1, 19, 2), + MUX_PG(dsi_dp2_mfp, 1, 17, 2), + MUX_PG(lcd0_d17_mfp, 1, 14, 3), + MUX_PG(dsi_dp3_mfp, 1, 12, 2), + MUX_PG(dsi_dn3_mfp, 1, 10, 2), + MUX_PG(dsi_dp0_mfp, 1, 7, 3), + MUX_PG(lvds_ee_pn_mfp, 1, 5, 2), + MUX_PG(spi0_i2c_pcm_mfp, 1, 3, 2), + MUX_PG(spi0_i2s_pcm_mfp, 1, 0, 3), + MUX_PG(dsi_dnp1_cp_mfp, 2, 29, 2), + MUX_PG(lvds_e_pn_mfp, 2, 27, 2), + MUX_PG(dsi_dn2_mfp, 2, 24, 3), + MUX_PG(uart2_rtsb_mfp, 2, 23, 1), + MUX_PG(uart2_ctsb_mfp, 2, 22, 1), + MUX_PG(uart3_rtsb_mfp, 2, 21, 1), + MUX_PG(uart3_ctsb_mfp, 2, 20, 1), + MUX_PG(sd0_d0_mfp, 2, 17, 3), + MUX_PG(sd0_d1_mfp, 2, 14, 3), + MUX_PG(sd0_d2_d3_mfp, 2, 11, 3), + MUX_PG(sd1_d0_d3_mfp, 2, 9, 2), + MUX_PG(sd0_cmd_mfp, 2, 7, 2), + MUX_PG(sd0_clk_mfp, 2, 5, 2), + MUX_PG(sd1_cmd_mfp, 2, 3, 2), + MUX_PG(uart0_rx_mfp, 2, 0, 3), + MUX_PG(clko_25m_mfp, 3, 30, 1), + MUX_PG(csi_cn_cp_mfp, 3, 28, 2), + MUX_PG(sens0_ckout_mfp, 3, 22, 2), + MUX_PG(uart0_tx_mfp, 3, 19, 3), + MUX_PG(i2c0_mfp, 3, 16, 3), + MUX_PG(csi_dn_dp_mfp, 3, 14, 2), + MUX_PG(sen0_pclk_mfp, 3, 12, 2), + MUX_PG(pcm1_in_mfp, 3, 10, 2), + MUX_PG(pcm1_clk_mfp, 3, 8, 2), + MUX_PG(pcm1_sync_mfp, 3, 6, 2), + MUX_PG(pcm1_out_mfp, 3, 4, 2), + MUX_PG(dnand_data_wr_mfp, 3, 3, 1), + MUX_PG(dnand_acle_ce0_mfp, 3, 2, 1), + MUX_PG(nand_ceb2_mfp, 3, 0, 2), + MUX_PG(nand_ceb3_mfp, 3, 0, 2), + + DRV_PG(sirq_drv, 0, 28, 2), + DRV_PG(rmii_txd01_txen_drv, 0, 22, 2), + DRV_PG(rmii_rxer_drv, 0, 20, 2), + DRV_PG(rmii_crs_drv, 0, 18, 2), + DRV_PG(rmii_rxd10_drv, 0, 16, 2), + DRV_PG(rmii_ref_clk_drv, 0, 14, 2), + DRV_PG(smi_mdc_mdio_drv, 0, 12, 2), + DRV_PG(i2s_d0_drv, 0, 10, 2), + DRV_PG(i2s_bclk0_drv, 0, 8, 2), + DRV_PG(i2s3_drv, 0, 6, 2), + DRV_PG(i2s13_drv, 0, 4, 2), + DRV_PG(pcm1_drv, 0, 2, 2), + DRV_PG(ks_in_drv, 0, 0, 2), + DRV_PG(ks_out_drv, 1, 30, 2), + DRV_PG(lvds_all_drv, 1, 28, 2), + DRV_PG(lcd_dsi_drv, 1, 26, 2), + DRV_PG(dsi_drv, 1, 24, 2), + DRV_PG(sd0_d0_d3_drv, 1, 22, 2), + DRV_PG(sd1_d0_d3_drv, 1, 20, 2), + DRV_PG(sd0_cmd_drv, 1, 18, 2), + DRV_PG(sd0_clk_drv, 1, 16, 2), + DRV_PG(sd1_cmd_drv, 1, 14, 2), + DRV_PG(sd1_clk_drv, 1, 12, 2), + DRV_PG(spi0_all_drv, 1, 10, 2), + DRV_PG(uart0_rx_drv, 2, 30, 2), + DRV_PG(uart0_tx_drv, 2, 28, 2), + DRV_PG(uart2_all_drv, 2, 26, 2), + DRV_PG(i2c0_all_drv, 2, 23, 2), + DRV_PG(i2c12_all_drv, 2, 21, 2), + DRV_PG(sens0_pclk_drv, 2, 18, 2), + DRV_PG(sens0_ckout_drv, 2, 12, 2), + DRV_PG(uart3_all_drv, 2, 2, 2), +}; + +static const char * const nor_groups[] = { + "lcd0_d18_mfp", + "i2s_d0_mfp", + "i2s0_pcm0_mfp", + "i2s1_pcm0_mfp", + "i2s_d1_mfp", + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "lcd0_d17_mfp", + "lvds_ee_pn_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", + "lvds_e_pn_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "sd1_d0_d3_mfp", + "sd0_cmd_mfp", + "sd1_cmd_mfp", + "sens0_ckout_mfp", + "sen0_pclk_mfp", +}; + +static const char * const eth_rmii_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "rmii_ref_clk_mfp", +}; + +static const char * const eth_smii_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_ref_clk_mfp", +}; + +static const char * const spi0_groups[] = { + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp0_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", + "dsi_dn2_mfp", +}; + +static const char * const spi1_groups[] = { + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const spi2_groups[] = { + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "rmii_ref_clk_mfp", + "dnand_acle_ce0_mfp", +}; + +static const char * const spi3_groups[] = { + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", +}; + +static const char * const sens0_groups[] = { + "csi_cn_cp_mfp", + "sens0_ckout_mfp", + "csi_dn_dp_mfp", + "sen0_pclk_mfp", +}; + +static const char * const sens1_groups[] = { + "lcd0_d18_mfp", + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "sens0_ckout_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const uart0_groups[] = { + "uart2_rtsb_mfp", + "uart2_ctsb_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", +}; + +static const char * const uart1_groups[] = { + "sd0_d2_d3_mfp", + "i2c0_mfp", +}; + +static const char * const uart2_groups[] = { + "rmii_txen_mfp", + "rmii_rxen_mfp", + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp0_mfp", + "dsi_dn2_mfp", + "uart2_rtsb_mfp", + "uart2_ctsb_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const uart3_groups[] = { + "uart3_rtsb_mfp", + "uart3_ctsb_mfp", +}; + +static const char * const uart4_groups[] = { + "rmii_crs_dv_mfp", + "rmii_ref_clk_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", +}; + +static const char * const uart5_groups[] = { + "rmii_rxd1_mfp", + "rmii_rxd0_mfp", + "ks_out0_mfp", + "ks_out2_mfp", + "uart3_rtsb_mfp", + "uart3_ctsb_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", +}; + +static const char * const uart6_groups[] = { + "rmii_txd0_mfp", + "rmii_txd1_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const i2s0_groups[] = { + "i2s_d0_mfp", + "i2s_pcm1_mfp", + "i2s0_pcm0_mfp", +}; + +static const char * const i2s1_groups[] = { + "i2s1_pcm0_mfp", + "i2s_d1_mfp", + "spi0_i2s_pcm_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", +}; + +static const char * const pcm1_groups[] = { + "i2s_pcm1_mfp", + "spi0_i2s_pcm_mfp", + "uart0_rx_mfp", + "uart0_tx_mfp", + "pcm1_in_mfp", + "pcm1_clk_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const pcm0_groups[] = { + "i2s0_pcm0_mfp", + "i2s1_pcm0_mfp", + "spi0_i2c_pcm_mfp", + "spi0_i2s_pcm_mfp", +}; + +static const char * const ks_groups[] = { + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", +}; + +static const char * const jtag_groups[] = { + "ks_in2_mfp", + "ks_in1_mfp", + "ks_in0_mfp", + "ks_in3_mfp", + "ks_out1_mfp", + "sd0_d0_mfp", + "sd0_d2_d3_mfp", + "sd0_cmd_mfp", + "sd0_clk_mfp", +}; + +static const char * const pwm0_groups[] = { + "ks_in2_mfp", + "ks_in0_mfp", + "rmii_txen_mfp", + "sen0_pclk_mfp", +}; + +static const char * const pwm1_groups[] = { + "rmii_rxen_mfp", + "ks_in1_mfp", + "ks_in3_mfp", + "sens0_ckout_mfp", +}; + +static const char * const pwm2_groups[] = { + "lcd0_d18_mfp", + "rmii_rxd1_mfp", + "ks_out0_mfp", + "ks_out2_mfp", +}; + +static const char * const pwm3_groups[] = { + "rmii_rxd0_mfp", + "ks_out1_mfp", + "lcd0_d17_mfp", +}; + +static const char * const pwm4_groups[] = { + "lcd0_d18_mfp", + "rmii_crs_dv_mfp", + "rmii_txd0_mfp", + "ks_in0_mfp", + "pcm1_in_mfp", + "nand_ceb3_mfp", +}; + +static const char * const pwm5_groups[] = { + "rmii_txd1_mfp", + "ks_in1_mfp", + "pcm1_clk_mfp", + "nand_ceb2_mfp", +}; + +static const char * const p0_groups[] = { + "ks_in2_mfp", + "ks_in0_mfp", +}; + +static const char * const sd0_groups[] = { + "ks_out0_mfp", + "ks_out1_mfp", + "ks_out2_mfp", + "lcd0_d17_mfp", + "dsi_dp3_mfp", + "dsi_dp0_mfp", + "sd0_d0_mfp", + "sd0_d1_mfp", + "sd0_d2_d3_mfp", + "sd1_d0_d3_mfp", + "sd0_cmd_mfp", + "sd0_clk_mfp", +}; + +static const char * const sd1_groups[] = { + "dsi_dp2_mfp", + "lcd0_d17_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "dsi_dnp1_cp_mfp", + "dsi_dn2_mfp", + "sd1_d0_d3_mfp", + "sd1_cmd_mfp", +}; + +static const char * const sd2_groups[] = { + "dnand_data_wr_mfp", +}; + +static const char * const i2c0_groups[] = { + "uart0_rx_mfp", + "uart0_tx_mfp", + "i2c0_mfp", +}; + +static const char * const i2c1_groups[] = { + "i2c0_mfp", +}; + +static const char * const i2c3_groups[] = { + "spi0_i2c_pcm_mfp", + "pcm1_sync_mfp", + "pcm1_out_mfp", +}; + +static const char * const lvds_groups[] = { + "lvds_o_pn_mfp", + "lvds_ee_pn_mfp", + "lvds_e_pn_mfp", +}; + +static const char * const ts_groups[] = { + "lvds_o_pn_mfp", + "lvds_ee_pn_mfp", +}; + +static const char * const lcd0_groups[] = { + "lcd0_d18_mfp", + "lcd0_d17_mfp", + "lvds_o_pn_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "lvds_ee_pn_mfp", + "dsi_dnp1_cp_mfp", + "lvds_e_pn_mfp", +}; + +static const char * const usb30_groups[] = { + "ks_in1_mfp", +}; + +static const char * const clko_25m_groups[] = { + "clko_25m_mfp", +}; + +static const char * const mipi_csi_groups[] = { + "csi_cn_cp_mfp", + "csi_dn_dp_mfp", +}; + +static const char * const dsi_groups[] = { + "dsi_dn0_mfp", + "dsi_dp2_mfp", + "dsi_dp3_mfp", + "dsi_dn3_mfp", + "dsi_dp0_mfp", + "dsi_dnp1_cp_mfp", + "dsi_dn2_mfp", +}; + +static const char * const nand_groups[] = { + "dnand_data_wr_mfp", + "dnand_acle_ce0_mfp", + "nand_ceb2_mfp", + "nand_ceb3_mfp", +}; + +static const char * const spdif_groups[] = { + "uart0_tx_mfp", +}; + +static const struct owl_pinmux_func s500_functions[] = { + [S500_MUX_NOR] = FUNCTION(nor), + [S500_MUX_ETH_RMII] = FUNCTION(eth_rmii), + [S500_MUX_ETH_SMII] = FUNCTION(eth_smii), + [S500_MUX_SPI0] = FUNCTION(spi0), + [S500_MUX_SPI1] = FUNCTION(spi1), + [S500_MUX_SPI2] = FUNCTION(spi2), + [S500_MUX_SPI3] = FUNCTION(spi3), + [S500_MUX_SENS0] = FUNCTION(sens0), + [S500_MUX_SENS1] = FUNCTION(sens1), + [S500_MUX_UART0] = FUNCTION(uart0), + [S500_MUX_UART1] = FUNCTION(uart1), + [S500_MUX_UART2] = FUNCTION(uart2), + [S500_MUX_UART3] = FUNCTION(uart3), + [S500_MUX_UART4] = FUNCTION(uart4), + [S500_MUX_UART5] = FUNCTION(uart5), + [S500_MUX_UART6] = FUNCTION(uart6), + [S500_MUX_I2S0] = FUNCTION(i2s0), + [S500_MUX_I2S1] = FUNCTION(i2s1), + [S500_MUX_PCM1] = FUNCTION(pcm1), + [S500_MUX_PCM0] = FUNCTION(pcm0), + [S500_MUX_KS] = FUNCTION(ks), + [S500_MUX_JTAG] = FUNCTION(jtag), + [S500_MUX_PWM0] = FUNCTION(pwm0), + [S500_MUX_PWM1] = FUNCTION(pwm1), + [S500_MUX_PWM2] = FUNCTION(pwm2), + [S500_MUX_PWM3] = FUNCTION(pwm3), + [S500_MUX_PWM4] = FUNCTION(pwm4), + [S500_MUX_PWM5] = FUNCTION(pwm5), + [S500_MUX_P0] = FUNCTION(p0), + [S500_MUX_SD0] = FUNCTION(sd0), + [S500_MUX_SD1] = FUNCTION(sd1), + [S500_MUX_SD2] = FUNCTION(sd2), + [S500_MUX_I2C0] = FUNCTION(i2c0), + [S500_MUX_I2C1] = FUNCTION(i2c1), + /*[S500_MUX_I2C2] = FUNCTION(i2c2),*/ + [S500_MUX_I2C3] = FUNCTION(i2c3), + [S500_MUX_DSI] = FUNCTION(dsi), + [S500_MUX_LVDS] = FUNCTION(lvds), + [S500_MUX_USB30] = FUNCTION(usb30), + [S500_MUX_CLKO_25M] = FUNCTION(clko_25m), + [S500_MUX_MIPI_CSI] = FUNCTION(mipi_csi), + [S500_MUX_NAND] = FUNCTION(nand), + [S500_MUX_SPDIF] = FUNCTION(spdif), + /*[S500_MUX_SIRQ0] = FUNCTION(sirq0),*/ + /*[S500_MUX_SIRQ1] = FUNCTION(sirq1),*/ + /*[S500_MUX_SIRQ2] = FUNCTION(sirq2),*/ + [S500_MUX_TS] = FUNCTION(ts), + [S500_MUX_LCD0] = FUNCTION(lcd0), +}; + +/* PAD_ST0 */ +static PAD_ST_CONF(I2C0_SDATA, 0, 30, 1); +static PAD_ST_CONF(UART0_RX, 0, 29, 1); +static PAD_ST_CONF(I2S_MCLK1, 0, 23, 1); +static PAD_ST_CONF(ETH_REF_CLK, 0, 22, 1); +static PAD_ST_CONF(ETH_TXEN, 0, 21, 1); +static PAD_ST_CONF(ETH_TXD0, 0, 20, 1); +static PAD_ST_CONF(I2S_LRCLK1, 0, 19, 1); +static PAD_ST_CONF(DSI_DP0, 0, 16, 1); +static PAD_ST_CONF(DSI_DN0, 0, 15, 1); +static PAD_ST_CONF(UART0_TX, 0, 14, 1); +static PAD_ST_CONF(SPI0_SCLK, 0, 13, 1); +static PAD_ST_CONF(SD0_CLK, 0, 12, 1); +static PAD_ST_CONF(KS_IN0, 0, 11, 1); +static PAD_ST_CONF(SENSOR0_PCLK, 0, 9, 1); +static PAD_ST_CONF(I2C0_SCLK, 0, 7, 1); +static PAD_ST_CONF(KS_OUT0, 0, 6, 1); +static PAD_ST_CONF(KS_OUT1, 0, 5, 1); +static PAD_ST_CONF(KS_OUT2, 0, 4, 1); + +/* PAD_ST1 */ +static PAD_ST_CONF(DSI_DP2, 1, 31, 1); +static PAD_ST_CONF(DSI_DN2, 1, 30, 1); +static PAD_ST_CONF(I2S_LRCLK0, 1, 29, 1); +static PAD_ST_CONF(UART3_CTSB, 1, 27, 1); +static PAD_ST_CONF(UART3_RTSB, 1, 26, 1); +static PAD_ST_CONF(UART3_RX, 1, 25, 1); +static PAD_ST_CONF(UART2_RTSB, 1, 24, 1); +static PAD_ST_CONF(UART2_CTSB, 1, 23, 1); +static PAD_ST_CONF(UART2_RX, 1, 22, 1); +static PAD_ST_CONF(ETH_RXD0, 1, 21, 1); +static PAD_ST_CONF(ETH_RXD1, 1, 20, 1); +static PAD_ST_CONF(ETH_CRS_DV, 1, 19, 1); +static PAD_ST_CONF(ETH_RXER, 1, 18, 1); +static PAD_ST_CONF(ETH_TXD1, 1, 17, 1); +static PAD_ST_CONF(LVDS_OAP, 1, 12, 1); +static PAD_ST_CONF(PCM1_CLK, 1, 11, 1); +static PAD_ST_CONF(PCM1_IN, 1, 10, 1); +static PAD_ST_CONF(PCM1_SYNC, 1, 9, 1); +static PAD_ST_CONF(I2C1_SCLK, 1, 8, 1); +static PAD_ST_CONF(I2C1_SDATA, 1, 7, 1); +static PAD_ST_CONF(I2C2_SCLK, 1, 6, 1); +static PAD_ST_CONF(I2C2_SDATA, 1, 5, 1); +static PAD_ST_CONF(SPI0_MOSI, 1, 4, 1); +static PAD_ST_CONF(SPI0_MISO, 1, 3, 1); +static PAD_ST_CONF(SPI0_SS, 1, 2, 1); +static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); +static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); + +/* PAD_PULLCTL0 */ +static PAD_PULLCTL_CONF(PCM1_SYNC, 0, 30, 1); +static PAD_PULLCTL_CONF(PCM1_OUT, 0, 29, 1); +static PAD_PULLCTL_CONF(KS_OUT2, 0, 28, 1); +static PAD_PULLCTL_CONF(LCD0_D17, 0, 27, 1); +static PAD_PULLCTL_CONF(DSI_DN3, 0, 26, 1); +static PAD_PULLCTL_CONF(ETH_RXER, 0, 16, 1); +static PAD_PULLCTL_CONF(SIRQ0, 0, 14, 2); +static PAD_PULLCTL_CONF(SIRQ1, 0, 12, 2); +static PAD_PULLCTL_CONF(SIRQ2, 0, 10, 2); +static PAD_PULLCTL_CONF(I2C0_SDATA, 0, 9, 1); +static PAD_PULLCTL_CONF(I2C0_SCLK, 0, 8, 1); +static PAD_PULLCTL_CONF(KS_IN0, 0, 7, 1); +static PAD_PULLCTL_CONF(KS_IN1, 0, 6, 1); +static PAD_PULLCTL_CONF(KS_IN2, 0, 5, 1); +static PAD_PULLCTL_CONF(KS_IN3, 0, 4, 1); +static PAD_PULLCTL_CONF(KS_OUT0, 0, 2, 1); +static PAD_PULLCTL_CONF(KS_OUT1, 0, 1, 1); +static PAD_PULLCTL_CONF(DSI_DP1, 0, 0, 1); + +/* PAD_PULLCTL1 */ +static PAD_PULLCTL_CONF(DSI_CP, 1, 31, 1); +static PAD_PULLCTL_CONF(DSI_CN, 1, 30, 1); +static PAD_PULLCTL_CONF(DSI_DN2, 1, 28, 1); +static PAD_PULLCTL_CONF(DNAND_RDBN, 1, 25, 1); +static PAD_PULLCTL_CONF(SD0_D0, 1, 17, 1); +static PAD_PULLCTL_CONF(SD0_D1, 1, 16, 1); +static PAD_PULLCTL_CONF(SD0_D2, 1, 15, 1); +static PAD_PULLCTL_CONF(SD0_D3, 1, 14, 1); +static PAD_PULLCTL_CONF(SD0_CMD, 1, 13, 1); +static PAD_PULLCTL_CONF(SD0_CLK, 1, 12, 1); +static PAD_PULLCTL_CONF(SD1_CMD, 1, 11, 1); +static PAD_PULLCTL_CONF(SD1_D0, 1, 6, 1); +static PAD_PULLCTL_CONF(SD1_D1, 1, 5, 1); +static PAD_PULLCTL_CONF(SD1_D2, 1, 4, 1); +static PAD_PULLCTL_CONF(SD1_D3, 1, 3, 1); +static PAD_PULLCTL_CONF(UART0_RX, 1, 2, 1); +static PAD_PULLCTL_CONF(UART0_TX, 1, 1, 1); +static PAD_PULLCTL_CONF(CLKO_25M, 1, 0, 1); + +/* PAD_PULLCTL2 */ +static PAD_PULLCTL_CONF(SPI0_SCLK, 2, 12, 1); +static PAD_PULLCTL_CONF(SPI0_MOSI, 2, 11, 1); +static PAD_PULLCTL_CONF(I2C1_SDATA, 2, 10, 1); +static PAD_PULLCTL_CONF(I2C1_SCLK, 2, 9, 1); +static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1); +static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1); +static PAD_PULLCTL_CONF(DNAND_DQSN, 2, 5, 2); +static PAD_PULLCTL_CONF(DNAND_DQS, 2, 3, 2); +static PAD_PULLCTL_CONF(DNAND_D0, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D1, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D2, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D3, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D4, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D5, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D6, 2, 2, 1); +static PAD_PULLCTL_CONF(DNAND_D7, 2, 2, 1); + +/* Pad info table */ +static struct owl_padinfo s500_padinfo[NUM_PADS] = { + [DNAND_DQS] = PAD_INFO_PULLCTL(DNAND_DQS), + [DNAND_DQSN] = PAD_INFO_PULLCTL(DNAND_DQSN), + [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), + [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), + [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), + [ETH_RXER] = PAD_INFO_PULLCTL_ST(ETH_RXER), + [ETH_CRS_DV] = PAD_INFO_ST(ETH_CRS_DV), + [ETH_RXD1] = PAD_INFO_ST(ETH_RXD1), + [ETH_RXD0] = PAD_INFO_ST(ETH_RXD0), + [ETH_REF_CLK] = PAD_INFO_ST(ETH_REF_CLK), + [ETH_MDC] = PAD_INFO(ETH_MDC), + [ETH_MDIO] = PAD_INFO(ETH_MDIO), + [SIRQ0] = PAD_INFO_PULLCTL(SIRQ0), + [SIRQ1] = PAD_INFO_PULLCTL(SIRQ1), + [SIRQ2] = PAD_INFO_PULLCTL(SIRQ2), + [I2S_D0] = PAD_INFO(I2S_D0), + [I2S_BCLK0] = PAD_INFO_ST(I2S_BCLK0), + [I2S_LRCLK0] = PAD_INFO_ST(I2S_LRCLK0), + [I2S_MCLK0] = PAD_INFO_ST(I2S_MCLK0), + [I2S_D1] = PAD_INFO(I2S_D1), + [I2S_BCLK1] = PAD_INFO(I2S_BCLK1), + [I2S_LRCLK1] = PAD_INFO_ST(I2S_LRCLK1), + [I2S_MCLK1] = PAD_INFO_ST(I2S_MCLK1), + [KS_IN0] = PAD_INFO_PULLCTL_ST(KS_IN0), + [KS_IN1] = PAD_INFO_PULLCTL(KS_IN1), + [KS_IN2] = PAD_INFO_PULLCTL(KS_IN2), + [KS_IN3] = PAD_INFO_PULLCTL(KS_IN3), + [KS_OUT0] = PAD_INFO_PULLCTL_ST(KS_OUT0), + [KS_OUT1] = PAD_INFO_PULLCTL_ST(KS_OUT1), + [KS_OUT2] = PAD_INFO_PULLCTL_ST(KS_OUT2), + [LVDS_OEP] = PAD_INFO(LVDS_OEP), + [LVDS_OEN] = PAD_INFO(LVDS_OEN), + [LVDS_ODP] = PAD_INFO(LVDS_ODP), + [LVDS_ODN] = PAD_INFO(LVDS_ODN), + [LVDS_OCP] = PAD_INFO(LVDS_OCP), + [LVDS_OCN] = PAD_INFO(LVDS_OCN), + [LVDS_OBP] = PAD_INFO(LVDS_OBP), + [LVDS_OBN] = PAD_INFO(LVDS_OBN), + [LVDS_OAP] = PAD_INFO_ST(LVDS_OAP), + [LVDS_OAN] = PAD_INFO(LVDS_OAN), + [LVDS_EEP] = PAD_INFO(LVDS_EEP), + [LVDS_EEN] = PAD_INFO(LVDS_EEN), + [LVDS_EDP] = PAD_INFO(LVDS_EDP), + [LVDS_EDN] = PAD_INFO(LVDS_EDN), + [LVDS_ECP] = PAD_INFO(LVDS_ECP), + [LVDS_ECN] = PAD_INFO(LVDS_ECN), + [LVDS_EBP] = PAD_INFO(LVDS_EBP), + [LVDS_EBN] = PAD_INFO(LVDS_EBN), + [LVDS_EAP] = PAD_INFO(LVDS_EAP), + [LVDS_EAN] = PAD_INFO(LVDS_EAN), + [LCD0_D18] = PAD_INFO(LCD0_D18), + [LCD0_D17] = PAD_INFO_PULLCTL(LCD0_D17), + [DSI_DP3] = PAD_INFO(DSI_DP3), + [DSI_DN3] = PAD_INFO_PULLCTL(DSI_DN3), + [DSI_DP1] = PAD_INFO_PULLCTL(DSI_DP1), + [DSI_DN1] = PAD_INFO(DSI_DN1), + [DSI_CP] = PAD_INFO_PULLCTL(DSI_CP), + [DSI_CN] = PAD_INFO_PULLCTL(DSI_CN), + [DSI_DP0] = PAD_INFO_ST(DSI_DP0), + [DSI_DN0] = PAD_INFO_ST(DSI_DN0), + [DSI_DP2] = PAD_INFO_ST(DSI_DP2), + [DSI_DN2] = PAD_INFO_PULLCTL_ST(DSI_DN2), + [SD0_D0] = PAD_INFO_PULLCTL(SD0_D0), + [SD0_D1] = PAD_INFO_PULLCTL(SD0_D1), + [SD0_D2] = PAD_INFO_PULLCTL(SD0_D2), + [SD0_D3] = PAD_INFO_PULLCTL(SD0_D3), + [SD1_D0] = PAD_INFO_PULLCTL(SD1_D0), + [SD1_D1] = PAD_INFO_PULLCTL(SD1_D1), + [SD1_D2] = PAD_INFO_PULLCTL(SD1_D2), + [SD1_D3] = PAD_INFO_PULLCTL(SD1_D3), + [SD0_CMD] = PAD_INFO_PULLCTL(SD0_CMD), + [SD0_CLK] = PAD_INFO_PULLCTL_ST(SD0_CLK), + [SD1_CMD] = PAD_INFO_PULLCTL(SD1_CMD), + [SD1_CLK] = PAD_INFO(SD1_CLK), + [SPI0_SCLK] = PAD_INFO_PULLCTL_ST(SPI0_SCLK), + [SPI0_SS] = PAD_INFO_ST(SPI0_SS), + [SPI0_MISO] = PAD_INFO_ST(SPI0_MISO), + [SPI0_MOSI] = PAD_INFO_PULLCTL_ST(SPI0_MOSI), + [UART0_RX] = PAD_INFO_PULLCTL_ST(UART0_RX), + [UART0_TX] = PAD_INFO_PULLCTL_ST(UART0_TX), + [I2C0_SCLK] = PAD_INFO_PULLCTL_ST(I2C0_SCLK), + [I2C0_SDATA] = PAD_INFO_PULLCTL_ST(I2C0_SDATA), + [SENSOR0_PCLK] = PAD_INFO_ST(SENSOR0_PCLK), + [SENSOR0_CKOUT] = PAD_INFO(SENSOR0_CKOUT), + [DNAND_ALE] = PAD_INFO(DNAND_ALE), + [DNAND_CLE] = PAD_INFO(DNAND_CLE), + [DNAND_CEB0] = PAD_INFO(DNAND_CEB0), + [DNAND_CEB1] = PAD_INFO(DNAND_CEB1), + [DNAND_CEB2] = PAD_INFO(DNAND_CEB2), + [DNAND_CEB3] = PAD_INFO(DNAND_CEB3), + [UART2_RX] = PAD_INFO_ST(UART2_RX), + [UART2_TX] = PAD_INFO(UART2_TX), + [UART2_RTSB] = PAD_INFO_ST(UART2_RTSB), + [UART2_CTSB] = PAD_INFO_ST(UART2_CTSB), + [UART3_RX] = PAD_INFO_ST(UART3_RX), + [UART3_TX] = PAD_INFO(UART3_TX), + [UART3_RTSB] = PAD_INFO_ST(UART3_RTSB), + [UART3_CTSB] = PAD_INFO_ST(UART3_CTSB), + [PCM1_IN] = PAD_INFO_ST(PCM1_IN), + [PCM1_CLK] = PAD_INFO_ST(PCM1_CLK), + [PCM1_SYNC] = PAD_INFO_PULLCTL_ST(PCM1_SYNC), + [PCM1_OUT] = PAD_INFO_PULLCTL(PCM1_OUT), + [I2C1_SCLK] = PAD_INFO_PULLCTL_ST(I2C1_SCLK), + [I2C1_SDATA] = PAD_INFO_PULLCTL_ST(I2C1_SDATA), + [I2C2_SCLK] = PAD_INFO_PULLCTL_ST(I2C2_SCLK), + [I2C2_SDATA] = PAD_INFO_PULLCTL_ST(I2C2_SDATA), + [CSI_DN0] = PAD_INFO(CSI_DN0), + [CSI_DP0] = PAD_INFO(CSI_DP0), + [CSI_DN1] = PAD_INFO(CSI_DN1), + [CSI_DP1] = PAD_INFO(CSI_DP1), + [CSI_CN] = PAD_INFO(CSI_CN), + [CSI_CP] = PAD_INFO(CSI_CP), + [CSI_DN2] = PAD_INFO(CSI_DN2), + [CSI_DP2] = PAD_INFO(CSI_DP2), + [CSI_DN3] = PAD_INFO(CSI_DN3), + [CSI_DP3] = PAD_INFO(CSI_DP3), + [DNAND_D0] = PAD_INFO_PULLCTL(DNAND_D0), + [DNAND_D1] = PAD_INFO_PULLCTL(DNAND_D1), + [DNAND_D2] = PAD_INFO_PULLCTL(DNAND_D2), + [DNAND_D3] = PAD_INFO_PULLCTL(DNAND_D3), + [DNAND_D4] = PAD_INFO_PULLCTL(DNAND_D4), + [DNAND_D5] = PAD_INFO_PULLCTL(DNAND_D5), + [DNAND_D6] = PAD_INFO_PULLCTL(DNAND_D6), + [DNAND_D7] = PAD_INFO_PULLCTL(DNAND_D7), + [DNAND_WRB] = PAD_INFO(DNAND_WRB), + [DNAND_RDB] = PAD_INFO(DNAND_RDB), + [DNAND_RDBN] = PAD_INFO_PULLCTL(DNAND_RDBN), + [DNAND_RB] = PAD_INFO(DNAND_RB), + [PORB] = PAD_INFO(PORB), + [CLKO_25M] = PAD_INFO_PULLCTL(CLKO_25M), + [BSEL] = PAD_INFO(BSEL), + [PKG0] = PAD_INFO(PKG0), + [PKG1] = PAD_INFO(PKG1), + [PKG2] = PAD_INFO(PKG2), + [PKG3] = PAD_INFO(PKG3), +}; + +static const struct owl_gpio_port s500_gpio_ports[] = { + OWL_GPIO_PORT(A, 0x0000, 32, 0x0, 0x4, 0x8, 0x204, 0x208, 0x20C, 0x230, 0), + OWL_GPIO_PORT(B, 0x000C, 32, 0x0, 0x4, 0x8, 0x1F8, 0x204, 0x208, 0x22C, 1), + OWL_GPIO_PORT(C, 0x0018, 32, 0x0, 0x4, 0x8, 0x1EC, 0x200, 0x204, 0x228, 2), + OWL_GPIO_PORT(D, 0x0024, 32, 0x0, 0x4, 0x8, 0x1E0, 0x1FC, 0x200, 0x224, 3), + OWL_GPIO_PORT(E, 0x0030, 4, 0x0, 0x4, 0x8, 0x1D4, 0x1F8, 0x1FC, 0x220, 4), +}; + +enum s500_pinconf_pull { + OWL_PINCONF_PULL_DOWN, + OWL_PINCONF_PULL_UP, +}; + +static int s500_pad_pinconf_arg2val(const struct owl_padinfo *info, + unsigned int param, u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = (*arg >= 1 ? 1 : 0); + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int s500_pad_pinconf_val2arg(const struct owl_padinfo *padinfo, + unsigned int param, u32 *arg) +{ + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + *arg = *arg == OWL_PINCONF_PULL_DOWN; + break; + case PIN_CONFIG_BIAS_PULL_UP: + *arg = *arg == OWL_PINCONF_PULL_UP; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + *arg = *arg == 1; + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static struct owl_pinctrl_soc_data s500_pinctrl_data = { + .padinfo = s500_padinfo, + .pins = (const struct pinctrl_pin_desc *)s500_pads, + .npins = ARRAY_SIZE(s500_pads), + .functions = s500_functions, + .nfunctions = ARRAY_SIZE(s500_functions), + .groups = s500_groups, + .ngroups = ARRAY_SIZE(s500_groups), + .ngpios = NUM_GPIOS, + .ports = s500_gpio_ports, + .nports = ARRAY_SIZE(s500_gpio_ports), + .padctl_arg2val = s500_pad_pinconf_arg2val, + .padctl_val2arg = s500_pad_pinconf_val2arg, +}; + +static int s500_pinctrl_probe(struct platform_device *pdev) +{ + return owl_pinctrl_probe(pdev, &s500_pinctrl_data); +} + +static const struct of_device_id s500_pinctrl_of_match[] = { + { .compatible = "actions,s500-pinctrl", }, + { } +}; + +static struct platform_driver s500_pinctrl_driver = { + .driver = { + .name = "pinctrl-s500", + .of_match_table = of_match_ptr(s500_pinctrl_of_match), + }, + .probe = s500_pinctrl_probe, +}; + +static int __init s500_pinctrl_init(void) +{ + return platform_driver_register(&s500_pinctrl_driver); +} +arch_initcall(s500_pinctrl_init); + +static void __exit s500_pinctrl_exit(void) +{ + platform_driver_unregister(&s500_pinctrl_driver); +} +module_exit(s500_pinctrl_exit); + +MODULE_AUTHOR("Actions Semi Inc."); +MODULE_AUTHOR("Cristian Ciocaltea "); +MODULE_DESCRIPTION("Actions Semi S500 SoC Pinctrl Driver"); +MODULE_LICENSE("GPL"); From e1c17431855936e25f1077efa8e331122321ddd7 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Mon, 3 Aug 2020 17:20:56 +0300 Subject: [PATCH 16/78] MAINTAINERS: Set pinctrl binding entry for all Actions Semi Owl SoCs Update the pinctrl binding entry to match all members of Actions Semi Owl SoCs. Signed-off-by: Cristian Ciocaltea Link: https://lore.kernel.org/r/1a9eb2b12c151d4d765d2aa74dc9cd58b3c117dc.1596461275.git.cristian.ciocaltea@gmail.com Signed-off-by: Linus Walleij --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..db97d048a92e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1526,7 +1526,7 @@ F: Documentation/devicetree/bindings/clock/actions,owl-cmu.txt F: Documentation/devicetree/bindings/dma/owl-dma.txt F: Documentation/devicetree/bindings/i2c/i2c-owl.txt F: Documentation/devicetree/bindings/mmc/owl-mmc.yaml -F: Documentation/devicetree/bindings/pinctrl/actions,s900-pinctrl.txt +F: Documentation/devicetree/bindings/pinctrl/actions,* F: Documentation/devicetree/bindings/power/actions,owl-sps.txt F: Documentation/devicetree/bindings/timer/actions,owl-timer.txt F: arch/arm/boot/dts/owl-* From 7c81b7199b79e053db7b909e667f2a88e6c437b0 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Mon, 17 Aug 2020 08:17:00 +0800 Subject: [PATCH 17/78] dt-bindings: pinctrl: mt8192: add pinctrl file This patch adds pinctrl file for mt8192. Signed-off-by: Zhiyong Tao Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200817001702.1646-2-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij --- include/dt-bindings/pinctrl/mt8192-pinfunc.h | 1344 ++++++++++++++++++ 1 file changed, 1344 insertions(+) create mode 100644 include/dt-bindings/pinctrl/mt8192-pinfunc.h diff --git a/include/dt-bindings/pinctrl/mt8192-pinfunc.h b/include/dt-bindings/pinctrl/mt8192-pinfunc.h new file mode 100644 index 000000000000..71ffe3a52578 --- /dev/null +++ b/include/dt-bindings/pinctrl/mt8192-pinfunc.h @@ -0,0 +1,1344 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Zhiyong Tao + * + */ + +#ifndef __MT8192_PINFUNC_H +#define __MT8192_PINFUNC_H + +#include "mt65xx.h" + +#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0) +#define PINMUX_GPIO0__FUNC_SPI6_CLK (MTK_PIN_NO(0) | 1) +#define PINMUX_GPIO0__FUNC_I2S5_MCK (MTK_PIN_NO(0) | 2) +#define PINMUX_GPIO0__FUNC_PWM_0 (MTK_PIN_NO(0) | 3) +#define PINMUX_GPIO0__FUNC_TDM_LRCK (MTK_PIN_NO(0) | 4) +#define PINMUX_GPIO0__FUNC_TP_GPIO0_AO (MTK_PIN_NO(0) | 5) +#define PINMUX_GPIO0__FUNC_MD_INT0 (MTK_PIN_NO(0) | 6) + +#define PINMUX_GPIO1__FUNC_GPIO1 (MTK_PIN_NO(1) | 0) +#define PINMUX_GPIO1__FUNC_SPI6_CSB (MTK_PIN_NO(1) | 1) +#define PINMUX_GPIO1__FUNC_I2S5_BCK (MTK_PIN_NO(1) | 2) +#define PINMUX_GPIO1__FUNC_PWM_1 (MTK_PIN_NO(1) | 3) +#define PINMUX_GPIO1__FUNC_TDM_BCK (MTK_PIN_NO(1) | 4) +#define PINMUX_GPIO1__FUNC_TP_GPIO1_AO (MTK_PIN_NO(1) | 5) +#define PINMUX_GPIO1__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(1) | 6) +#define PINMUX_GPIO1__FUNC_DBG_MON_A9 (MTK_PIN_NO(1) | 7) + +#define PINMUX_GPIO2__FUNC_GPIO2 (MTK_PIN_NO(2) | 0) +#define PINMUX_GPIO2__FUNC_SPI6_MI (MTK_PIN_NO(2) | 1) +#define PINMUX_GPIO2__FUNC_I2S5_LRCK (MTK_PIN_NO(2) | 2) +#define PINMUX_GPIO2__FUNC_PWM_2 (MTK_PIN_NO(2) | 3) +#define PINMUX_GPIO2__FUNC_TDM_MCK (MTK_PIN_NO(2) | 4) +#define PINMUX_GPIO2__FUNC_TP_GPIO2_AO (MTK_PIN_NO(2) | 5) +#define PINMUX_GPIO2__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(2) | 6) +#define PINMUX_GPIO2__FUNC_DBG_MON_A10 (MTK_PIN_NO(2) | 7) + +#define PINMUX_GPIO3__FUNC_GPIO3 (MTK_PIN_NO(3) | 0) +#define PINMUX_GPIO3__FUNC_SPI6_MO (MTK_PIN_NO(3) | 1) +#define PINMUX_GPIO3__FUNC_I2S5_DO (MTK_PIN_NO(3) | 2) +#define PINMUX_GPIO3__FUNC_PWM_3 (MTK_PIN_NO(3) | 3) +#define PINMUX_GPIO3__FUNC_TDM_DATA0 (MTK_PIN_NO(3) | 4) +#define PINMUX_GPIO3__FUNC_TP_GPIO3_AO (MTK_PIN_NO(3) | 5) +#define PINMUX_GPIO3__FUNC_CLKM0 (MTK_PIN_NO(3) | 6) +#define PINMUX_GPIO3__FUNC_DBG_MON_A11 (MTK_PIN_NO(3) | 7) + +#define PINMUX_GPIO4__FUNC_GPIO4 (MTK_PIN_NO(4) | 0) +#define PINMUX_GPIO4__FUNC_SPI4_A_CLK (MTK_PIN_NO(4) | 1) +#define PINMUX_GPIO4__FUNC_I2S2_MCK (MTK_PIN_NO(4) | 2) +#define PINMUX_GPIO4__FUNC_DMIC1_CLK (MTK_PIN_NO(4) | 3) +#define PINMUX_GPIO4__FUNC_TDM_DATA1 (MTK_PIN_NO(4) | 4) +#define PINMUX_GPIO4__FUNC_TP_GPIO4_AO (MTK_PIN_NO(4) | 5) +#define PINMUX_GPIO4__FUNC_PCM1_DI (MTK_PIN_NO(4) | 6) +#define PINMUX_GPIO4__FUNC_IDDIG (MTK_PIN_NO(4) | 7) + +#define PINMUX_GPIO5__FUNC_GPIO5 (MTK_PIN_NO(5) | 0) +#define PINMUX_GPIO5__FUNC_SPI4_A_CSB (MTK_PIN_NO(5) | 1) +#define PINMUX_GPIO5__FUNC_I2S2_BCK (MTK_PIN_NO(5) | 2) +#define PINMUX_GPIO5__FUNC_DMIC1_DAT (MTK_PIN_NO(5) | 3) +#define PINMUX_GPIO5__FUNC_TDM_DATA2 (MTK_PIN_NO(5) | 4) +#define PINMUX_GPIO5__FUNC_TP_GPIO5_AO (MTK_PIN_NO(5) | 5) +#define PINMUX_GPIO5__FUNC_PCM1_CLK (MTK_PIN_NO(5) | 6) +#define PINMUX_GPIO5__FUNC_USB_DRVVBUS (MTK_PIN_NO(5) | 7) + +#define PINMUX_GPIO6__FUNC_GPIO6 (MTK_PIN_NO(6) | 0) +#define PINMUX_GPIO6__FUNC_SPI4_A_MI (MTK_PIN_NO(6) | 1) +#define PINMUX_GPIO6__FUNC_I2S2_LRCK (MTK_PIN_NO(6) | 2) +#define PINMUX_GPIO6__FUNC_DMIC_CLK (MTK_PIN_NO(6) | 3) +#define PINMUX_GPIO6__FUNC_TDM_DATA3 (MTK_PIN_NO(6) | 4) +#define PINMUX_GPIO6__FUNC_TP_GPIO6_AO (MTK_PIN_NO(6) | 5) +#define PINMUX_GPIO6__FUNC_PCM1_SYNC (MTK_PIN_NO(6) | 6) + +#define PINMUX_GPIO7__FUNC_GPIO7 (MTK_PIN_NO(7) | 0) +#define PINMUX_GPIO7__FUNC_SPI4_A_MO (MTK_PIN_NO(7) | 1) +#define PINMUX_GPIO7__FUNC_I2S2_DI (MTK_PIN_NO(7) | 2) +#define PINMUX_GPIO7__FUNC_DMIC_DAT (MTK_PIN_NO(7) | 3) +#define PINMUX_GPIO7__FUNC_WIFI_TXD (MTK_PIN_NO(7) | 4) +#define PINMUX_GPIO7__FUNC_TP_GPIO7_AO (MTK_PIN_NO(7) | 5) +#define PINMUX_GPIO7__FUNC_PCM1_DO0 (MTK_PIN_NO(7) | 6) + +#define PINMUX_GPIO8__FUNC_GPIO8 (MTK_PIN_NO(8) | 0) +#define PINMUX_GPIO8__FUNC_SRCLKENAI1 (MTK_PIN_NO(8) | 1) +#define PINMUX_GPIO8__FUNC_I2S2_DI2 (MTK_PIN_NO(8) | 2) +#define PINMUX_GPIO8__FUNC_KPCOL2 (MTK_PIN_NO(8) | 3) +#define PINMUX_GPIO8__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(8) | 4) +#define PINMUX_GPIO8__FUNC_CLKM1 (MTK_PIN_NO(8) | 5) +#define PINMUX_GPIO8__FUNC_PCM1_DO1 (MTK_PIN_NO(8) | 6) +#define PINMUX_GPIO8__FUNC_DBG_MON_A12 (MTK_PIN_NO(8) | 7) + +#define PINMUX_GPIO9__FUNC_GPIO9 (MTK_PIN_NO(9) | 0) +#define PINMUX_GPIO9__FUNC_SRCLKENAI0 (MTK_PIN_NO(9) | 1) +#define PINMUX_GPIO9__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(9) | 2) +#define PINMUX_GPIO9__FUNC_KPROW2 (MTK_PIN_NO(9) | 3) +#define PINMUX_GPIO9__FUNC_CMMCLK4 (MTK_PIN_NO(9) | 4) +#define PINMUX_GPIO9__FUNC_CLKM3 (MTK_PIN_NO(9) | 5) +#define PINMUX_GPIO9__FUNC_PCM1_DO2 (MTK_PIN_NO(9) | 6) +#define PINMUX_GPIO9__FUNC_DBG_MON_A13 (MTK_PIN_NO(9) | 7) + +#define PINMUX_GPIO10__FUNC_GPIO10 (MTK_PIN_NO(10) | 0) +#define PINMUX_GPIO10__FUNC_MSDC2_CLK (MTK_PIN_NO(10) | 1) +#define PINMUX_GPIO10__FUNC_SPI4_B_CLK (MTK_PIN_NO(10) | 2) +#define PINMUX_GPIO10__FUNC_I2S8_MCK (MTK_PIN_NO(10) | 3) +#define PINMUX_GPIO10__FUNC_MD_INT0 (MTK_PIN_NO(10) | 5) +#define PINMUX_GPIO10__FUNC_TP_GPIO8_AO (MTK_PIN_NO(10) | 6) + +#define PINMUX_GPIO11__FUNC_GPIO11 (MTK_PIN_NO(11) | 0) +#define PINMUX_GPIO11__FUNC_MSDC2_CMD (MTK_PIN_NO(11) | 1) +#define PINMUX_GPIO11__FUNC_SPI4_B_CSB (MTK_PIN_NO(11) | 2) +#define PINMUX_GPIO11__FUNC_I2S8_BCK (MTK_PIN_NO(11) | 3) +#define PINMUX_GPIO11__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(11) | 4) +#define PINMUX_GPIO11__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(11) | 5) +#define PINMUX_GPIO11__FUNC_TP_GPIO9_AO (MTK_PIN_NO(11) | 6) + +#define PINMUX_GPIO12__FUNC_GPIO12 (MTK_PIN_NO(12) | 0) +#define PINMUX_GPIO12__FUNC_MSDC2_DAT3 (MTK_PIN_NO(12) | 1) +#define PINMUX_GPIO12__FUNC_SPI4_B_MI (MTK_PIN_NO(12) | 2) +#define PINMUX_GPIO12__FUNC_I2S8_LRCK (MTK_PIN_NO(12) | 3) +#define PINMUX_GPIO12__FUNC_DMIC1_CLK (MTK_PIN_NO(12) | 4) +#define PINMUX_GPIO12__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(12) | 5) +#define PINMUX_GPIO12__FUNC_TP_GPIO10_AO (MTK_PIN_NO(12) | 6) + +#define PINMUX_GPIO13__FUNC_GPIO13 (MTK_PIN_NO(13) | 0) +#define PINMUX_GPIO13__FUNC_MSDC2_DAT0 (MTK_PIN_NO(13) | 1) +#define PINMUX_GPIO13__FUNC_SPI4_B_MO (MTK_PIN_NO(13) | 2) +#define PINMUX_GPIO13__FUNC_I2S8_DI (MTK_PIN_NO(13) | 3) +#define PINMUX_GPIO13__FUNC_DMIC1_DAT (MTK_PIN_NO(13) | 4) +#define PINMUX_GPIO13__FUNC_ANT_SEL10 (MTK_PIN_NO(13) | 5) +#define PINMUX_GPIO13__FUNC_TP_GPIO11_AO (MTK_PIN_NO(13) | 6) + +#define PINMUX_GPIO14__FUNC_GPIO14 (MTK_PIN_NO(14) | 0) +#define PINMUX_GPIO14__FUNC_MSDC2_DAT2 (MTK_PIN_NO(14) | 1) +#define PINMUX_GPIO14__FUNC_IDDIG (MTK_PIN_NO(14) | 2) +#define PINMUX_GPIO14__FUNC_SCL_6306 (MTK_PIN_NO(14) | 3) +#define PINMUX_GPIO14__FUNC_PCIE_PERESET_N (MTK_PIN_NO(14) | 4) +#define PINMUX_GPIO14__FUNC_ANT_SEL11 (MTK_PIN_NO(14) | 5) +#define PINMUX_GPIO14__FUNC_TP_GPIO12_AO (MTK_PIN_NO(14) | 6) + +#define PINMUX_GPIO15__FUNC_GPIO15 (MTK_PIN_NO(15) | 0) +#define PINMUX_GPIO15__FUNC_MSDC2_DAT1 (MTK_PIN_NO(15) | 1) +#define PINMUX_GPIO15__FUNC_USB_DRVVBUS (MTK_PIN_NO(15) | 2) +#define PINMUX_GPIO15__FUNC_SDA_6306 (MTK_PIN_NO(15) | 3) +#define PINMUX_GPIO15__FUNC_PCIE_WAKE_N (MTK_PIN_NO(15) | 4) +#define PINMUX_GPIO15__FUNC_ANT_SEL12 (MTK_PIN_NO(15) | 5) +#define PINMUX_GPIO15__FUNC_TP_GPIO13_AO (MTK_PIN_NO(15) | 6) + +#define PINMUX_GPIO16__FUNC_GPIO16 (MTK_PIN_NO(16) | 0) +#define PINMUX_GPIO16__FUNC_SRCLKENAI1 (MTK_PIN_NO(16) | 1) +#define PINMUX_GPIO16__FUNC_IDDIG (MTK_PIN_NO(16) | 2) +#define PINMUX_GPIO16__FUNC_TP_GPIO14_AO (MTK_PIN_NO(16) | 3) +#define PINMUX_GPIO16__FUNC_KPCOL2 (MTK_PIN_NO(16) | 4) +#define PINMUX_GPIO16__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(16) | 5) +#define PINMUX_GPIO16__FUNC_SPI7_A_MI (MTK_PIN_NO(16) | 6) +#define PINMUX_GPIO16__FUNC_DBG_MON_A0 (MTK_PIN_NO(16) | 7) + +#define PINMUX_GPIO17__FUNC_GPIO17 (MTK_PIN_NO(17) | 0) +#define PINMUX_GPIO17__FUNC_SRCLKENAI0 (MTK_PIN_NO(17) | 1) +#define PINMUX_GPIO17__FUNC_USB_DRVVBUS (MTK_PIN_NO(17) | 2) +#define PINMUX_GPIO17__FUNC_TP_GPIO15_AO (MTK_PIN_NO(17) | 3) +#define PINMUX_GPIO17__FUNC_KPROW2 (MTK_PIN_NO(17) | 4) +#define PINMUX_GPIO17__FUNC_SPI7_A_MO (MTK_PIN_NO(17) | 6) +#define PINMUX_GPIO17__FUNC_DBG_MON_A1 (MTK_PIN_NO(17) | 7) + +#define PINMUX_GPIO18__FUNC_GPIO18 (MTK_PIN_NO(18) | 0) +#define PINMUX_GPIO18__FUNC_SRCLKENAI0 (MTK_PIN_NO(18) | 1) +#define PINMUX_GPIO18__FUNC_SPI4_C_MI (MTK_PIN_NO(18) | 2) +#define PINMUX_GPIO18__FUNC_SPI1_B_MI (MTK_PIN_NO(18) | 3) +#define PINMUX_GPIO18__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(18) | 4) +#define PINMUX_GPIO18__FUNC_ANT_SEL10 (MTK_PIN_NO(18) | 5) +#define PINMUX_GPIO18__FUNC_MD_INT0 (MTK_PIN_NO(18) | 6) +#define PINMUX_GPIO18__FUNC_DBG_MON_B2 (MTK_PIN_NO(18) | 7) + +#define PINMUX_GPIO19__FUNC_GPIO19 (MTK_PIN_NO(19) | 0) +#define PINMUX_GPIO19__FUNC_SRCLKENAI1 (MTK_PIN_NO(19) | 1) +#define PINMUX_GPIO19__FUNC_SPI4_C_MO (MTK_PIN_NO(19) | 2) +#define PINMUX_GPIO19__FUNC_SPI1_B_MO (MTK_PIN_NO(19) | 3) +#define PINMUX_GPIO19__FUNC_ANT_SEL11 (MTK_PIN_NO(19) | 5) +#define PINMUX_GPIO19__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(19) | 6) +#define PINMUX_GPIO19__FUNC_DBG_MON_B3 (MTK_PIN_NO(19) | 7) + +#define PINMUX_GPIO20__FUNC_GPIO20 (MTK_PIN_NO(20) | 0) +#define PINMUX_GPIO20__FUNC_SRCLKENAI0 (MTK_PIN_NO(20) | 1) +#define PINMUX_GPIO20__FUNC_SPI4_C_CLK (MTK_PIN_NO(20) | 2) +#define PINMUX_GPIO20__FUNC_SPI1_B_CLK (MTK_PIN_NO(20) | 3) +#define PINMUX_GPIO20__FUNC_PWM_3 (MTK_PIN_NO(20) | 4) +#define PINMUX_GPIO20__FUNC_ANT_SEL12 (MTK_PIN_NO(20) | 5) +#define PINMUX_GPIO20__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(20) | 6) +#define PINMUX_GPIO20__FUNC_DBG_MON_B4 (MTK_PIN_NO(20) | 7) + +#define PINMUX_GPIO21__FUNC_GPIO21 (MTK_PIN_NO(21) | 0) +#define PINMUX_GPIO21__FUNC_SPI4_C_CSB (MTK_PIN_NO(21) | 2) +#define PINMUX_GPIO21__FUNC_SPI1_B_CSB (MTK_PIN_NO(21) | 3) +#define PINMUX_GPIO21__FUNC_IDDIG (MTK_PIN_NO(21) | 6) +#define PINMUX_GPIO21__FUNC_DBG_MON_B5 (MTK_PIN_NO(21) | 7) + +#define PINMUX_GPIO22__FUNC_GPIO22 (MTK_PIN_NO(22) | 0) +#define PINMUX_GPIO22__FUNC_SPI0_C_CLK (MTK_PIN_NO(22) | 2) +#define PINMUX_GPIO22__FUNC_SPI7_B_CLK (MTK_PIN_NO(22) | 3) +#define PINMUX_GPIO22__FUNC_I2S7_BCK (MTK_PIN_NO(22) | 4) +#define PINMUX_GPIO22__FUNC_I2S9_BCK (MTK_PIN_NO(22) | 5) +#define PINMUX_GPIO22__FUNC_SCL_6306 (MTK_PIN_NO(22) | 6) + +#define PINMUX_GPIO23__FUNC_GPIO23 (MTK_PIN_NO(23) | 0) +#define PINMUX_GPIO23__FUNC_SPI0_C_CSB (MTK_PIN_NO(23) | 2) +#define PINMUX_GPIO23__FUNC_SPI7_B_CSB (MTK_PIN_NO(23) | 3) +#define PINMUX_GPIO23__FUNC_I2S7_LRCK (MTK_PIN_NO(23) | 4) +#define PINMUX_GPIO23__FUNC_I2S9_LRCK (MTK_PIN_NO(23) | 5) +#define PINMUX_GPIO23__FUNC_SDA_6306 (MTK_PIN_NO(23) | 6) + +#define PINMUX_GPIO24__FUNC_GPIO24 (MTK_PIN_NO(24) | 0) +#define PINMUX_GPIO24__FUNC_SRCLKENAI1 (MTK_PIN_NO(24) | 1) +#define PINMUX_GPIO24__FUNC_SPI0_C_MI (MTK_PIN_NO(24) | 2) +#define PINMUX_GPIO24__FUNC_SPI7_B_MI (MTK_PIN_NO(24) | 3) +#define PINMUX_GPIO24__FUNC_I2S6_DI (MTK_PIN_NO(24) | 4) +#define PINMUX_GPIO24__FUNC_I2S8_DI (MTK_PIN_NO(24) | 5) +#define PINMUX_GPIO24__FUNC_SPINOR_CS (MTK_PIN_NO(24) | 6) + +#define PINMUX_GPIO25__FUNC_GPIO25 (MTK_PIN_NO(25) | 0) +#define PINMUX_GPIO25__FUNC_SRCLKENAI0 (MTK_PIN_NO(25) | 1) +#define PINMUX_GPIO25__FUNC_SPI0_C_MO (MTK_PIN_NO(25) | 2) +#define PINMUX_GPIO25__FUNC_SPI7_B_MO (MTK_PIN_NO(25) | 3) +#define PINMUX_GPIO25__FUNC_I2S7_DO (MTK_PIN_NO(25) | 4) +#define PINMUX_GPIO25__FUNC_I2S9_DO (MTK_PIN_NO(25) | 5) +#define PINMUX_GPIO25__FUNC_SPINOR_CK (MTK_PIN_NO(25) | 6) + +#define PINMUX_GPIO26__FUNC_GPIO26 (MTK_PIN_NO(26) | 0) +#define PINMUX_GPIO26__FUNC_PWM_2 (MTK_PIN_NO(26) | 1) +#define PINMUX_GPIO26__FUNC_CLKM0 (MTK_PIN_NO(26) | 2) +#define PINMUX_GPIO26__FUNC_USB_DRVVBUS (MTK_PIN_NO(26) | 3) +#define PINMUX_GPIO26__FUNC_SPI5_C_MI (MTK_PIN_NO(26) | 4) +#define PINMUX_GPIO26__FUNC_I2S9_BCK (MTK_PIN_NO(26) | 5) + +#define PINMUX_GPIO27__FUNC_GPIO27 (MTK_PIN_NO(27) | 0) +#define PINMUX_GPIO27__FUNC_PWM_3 (MTK_PIN_NO(27) | 1) +#define PINMUX_GPIO27__FUNC_CLKM1 (MTK_PIN_NO(27) | 2) +#define PINMUX_GPIO27__FUNC_SPI5_C_MO (MTK_PIN_NO(27) | 4) +#define PINMUX_GPIO27__FUNC_I2S9_LRCK (MTK_PIN_NO(27) | 5) +#define PINMUX_GPIO27__FUNC_SPINOR_IO0 (MTK_PIN_NO(27) | 6) + +#define PINMUX_GPIO28__FUNC_GPIO28 (MTK_PIN_NO(28) | 0) +#define PINMUX_GPIO28__FUNC_PWM_0 (MTK_PIN_NO(28) | 1) +#define PINMUX_GPIO28__FUNC_CLKM2 (MTK_PIN_NO(28) | 2) +#define PINMUX_GPIO28__FUNC_SPI5_C_CSB (MTK_PIN_NO(28) | 4) +#define PINMUX_GPIO28__FUNC_I2S9_MCK (MTK_PIN_NO(28) | 5) +#define PINMUX_GPIO28__FUNC_SPINOR_IO1 (MTK_PIN_NO(28) | 6) + +#define PINMUX_GPIO29__FUNC_GPIO29 (MTK_PIN_NO(29) | 0) +#define PINMUX_GPIO29__FUNC_PWM_1 (MTK_PIN_NO(29) | 1) +#define PINMUX_GPIO29__FUNC_CLKM3 (MTK_PIN_NO(29) | 2) +#define PINMUX_GPIO29__FUNC_SPI5_C_CLK (MTK_PIN_NO(29) | 4) +#define PINMUX_GPIO29__FUNC_I2S9_DO (MTK_PIN_NO(29) | 5) +#define PINMUX_GPIO29__FUNC_SPINOR_IO2 (MTK_PIN_NO(29) | 6) + +#define PINMUX_GPIO30__FUNC_GPIO30 (MTK_PIN_NO(30) | 0) +#define PINMUX_GPIO30__FUNC_PWM_2 (MTK_PIN_NO(30) | 1) +#define PINMUX_GPIO30__FUNC_CLKM0 (MTK_PIN_NO(30) | 2) +#define PINMUX_GPIO30__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(30) | 3) +#define PINMUX_GPIO30__FUNC_I2S7_MCK (MTK_PIN_NO(30) | 4) +#define PINMUX_GPIO30__FUNC_I2S9_MCK (MTK_PIN_NO(30) | 5) +#define PINMUX_GPIO30__FUNC_SPINOR_IO3 (MTK_PIN_NO(30) | 6) + +#define PINMUX_GPIO31__FUNC_GPIO31 (MTK_PIN_NO(31) | 0) +#define PINMUX_GPIO31__FUNC_I2S3_MCK (MTK_PIN_NO(31) | 1) +#define PINMUX_GPIO31__FUNC_I2S1_MCK (MTK_PIN_NO(31) | 2) +#define PINMUX_GPIO31__FUNC_I2S5_MCK (MTK_PIN_NO(31) | 3) +#define PINMUX_GPIO31__FUNC_SRCLKENAI0 (MTK_PIN_NO(31) | 4) +#define PINMUX_GPIO31__FUNC_I2S0_MCK (MTK_PIN_NO(31) | 5) + +#define PINMUX_GPIO32__FUNC_GPIO32 (MTK_PIN_NO(32) | 0) +#define PINMUX_GPIO32__FUNC_I2S3_BCK (MTK_PIN_NO(32) | 1) +#define PINMUX_GPIO32__FUNC_I2S1_BCK (MTK_PIN_NO(32) | 2) +#define PINMUX_GPIO32__FUNC_I2S5_BCK (MTK_PIN_NO(32) | 3) +#define PINMUX_GPIO32__FUNC_PCM0_CLK (MTK_PIN_NO(32) | 4) +#define PINMUX_GPIO32__FUNC_I2S0_BCK (MTK_PIN_NO(32) | 5) + +#define PINMUX_GPIO33__FUNC_GPIO33 (MTK_PIN_NO(33) | 0) +#define PINMUX_GPIO33__FUNC_I2S3_LRCK (MTK_PIN_NO(33) | 1) +#define PINMUX_GPIO33__FUNC_I2S1_LRCK (MTK_PIN_NO(33) | 2) +#define PINMUX_GPIO33__FUNC_I2S5_LRCK (MTK_PIN_NO(33) | 3) +#define PINMUX_GPIO33__FUNC_PCM0_SYNC (MTK_PIN_NO(33) | 4) +#define PINMUX_GPIO33__FUNC_I2S0_LRCK (MTK_PIN_NO(33) | 5) + +#define PINMUX_GPIO34__FUNC_GPIO34 (MTK_PIN_NO(34) | 0) +#define PINMUX_GPIO34__FUNC_I2S0_DI (MTK_PIN_NO(34) | 1) +#define PINMUX_GPIO34__FUNC_I2S2_DI (MTK_PIN_NO(34) | 2) +#define PINMUX_GPIO34__FUNC_I2S2_DI2 (MTK_PIN_NO(34) | 3) +#define PINMUX_GPIO34__FUNC_PCM0_DI (MTK_PIN_NO(34) | 4) +#define PINMUX_GPIO34__FUNC_I2S0_DI_A (MTK_PIN_NO(34) | 5) + +#define PINMUX_GPIO35__FUNC_GPIO35 (MTK_PIN_NO(35) | 0) +#define PINMUX_GPIO35__FUNC_I2S3_DO (MTK_PIN_NO(35) | 1) +#define PINMUX_GPIO35__FUNC_I2S1_DO (MTK_PIN_NO(35) | 2) +#define PINMUX_GPIO35__FUNC_I2S5_DO (MTK_PIN_NO(35) | 3) +#define PINMUX_GPIO35__FUNC_PCM0_DO (MTK_PIN_NO(35) | 4) + +#define PINMUX_GPIO36__FUNC_GPIO36 (MTK_PIN_NO(36) | 0) +#define PINMUX_GPIO36__FUNC_SPI5_A_CLK (MTK_PIN_NO(36) | 1) +#define PINMUX_GPIO36__FUNC_DMIC1_CLK (MTK_PIN_NO(36) | 2) +#define PINMUX_GPIO36__FUNC_MD_URXD0 (MTK_PIN_NO(36) | 4) +#define PINMUX_GPIO36__FUNC_UCTS0 (MTK_PIN_NO(36) | 5) +#define PINMUX_GPIO36__FUNC_URXD1 (MTK_PIN_NO(36) | 6) + +#define PINMUX_GPIO37__FUNC_GPIO37 (MTK_PIN_NO(37) | 0) +#define PINMUX_GPIO37__FUNC_SPI5_A_CSB (MTK_PIN_NO(37) | 1) +#define PINMUX_GPIO37__FUNC_DMIC1_DAT (MTK_PIN_NO(37) | 2) +#define PINMUX_GPIO37__FUNC_MD_UTXD0 (MTK_PIN_NO(37) | 4) +#define PINMUX_GPIO37__FUNC_URTS0 (MTK_PIN_NO(37) | 5) +#define PINMUX_GPIO37__FUNC_UTXD1 (MTK_PIN_NO(37) | 6) + +#define PINMUX_GPIO38__FUNC_GPIO38 (MTK_PIN_NO(38) | 0) +#define PINMUX_GPIO38__FUNC_SPI5_A_MI (MTK_PIN_NO(38) | 1) +#define PINMUX_GPIO38__FUNC_DMIC_CLK (MTK_PIN_NO(38) | 2) +#define PINMUX_GPIO38__FUNC_MD_URXD1 (MTK_PIN_NO(38) | 4) +#define PINMUX_GPIO38__FUNC_URXD0 (MTK_PIN_NO(38) | 5) +#define PINMUX_GPIO38__FUNC_UCTS1 (MTK_PIN_NO(38) | 6) + +#define PINMUX_GPIO39__FUNC_GPIO39 (MTK_PIN_NO(39) | 0) +#define PINMUX_GPIO39__FUNC_SPI5_A_MO (MTK_PIN_NO(39) | 1) +#define PINMUX_GPIO39__FUNC_DMIC_DAT (MTK_PIN_NO(39) | 2) +#define PINMUX_GPIO39__FUNC_MD_UTXD1 (MTK_PIN_NO(39) | 4) +#define PINMUX_GPIO39__FUNC_UTXD0 (MTK_PIN_NO(39) | 5) +#define PINMUX_GPIO39__FUNC_URTS1 (MTK_PIN_NO(39) | 6) + +#define PINMUX_GPIO40__FUNC_GPIO40 (MTK_PIN_NO(40) | 0) +#define PINMUX_GPIO40__FUNC_DISP_PWM (MTK_PIN_NO(40) | 1) +#define PINMUX_GPIO40__FUNC_DBG_MON_A6 (MTK_PIN_NO(40) | 7) + +#define PINMUX_GPIO41__FUNC_GPIO41 (MTK_PIN_NO(41) | 0) +#define PINMUX_GPIO41__FUNC_DSI_TE (MTK_PIN_NO(41) | 1) +#define PINMUX_GPIO41__FUNC_DBG_MON_A7 (MTK_PIN_NO(41) | 7) + +#define PINMUX_GPIO42__FUNC_GPIO42 (MTK_PIN_NO(42) | 0) +#define PINMUX_GPIO42__FUNC_LCM_RST (MTK_PIN_NO(42) | 1) +#define PINMUX_GPIO42__FUNC_DBG_MON_A8 (MTK_PIN_NO(42) | 7) + +#define PINMUX_GPIO43__FUNC_GPIO43 (MTK_PIN_NO(43) | 0) +#define PINMUX_GPIO43__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(43) | 1) +#define PINMUX_GPIO43__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(43) | 2) +#define PINMUX_GPIO43__FUNC_SCL_6306 (MTK_PIN_NO(43) | 3) +#define PINMUX_GPIO43__FUNC_ADSP_URXD0 (MTK_PIN_NO(43) | 4) +#define PINMUX_GPIO43__FUNC_PTA_RXD (MTK_PIN_NO(43) | 5) +#define PINMUX_GPIO43__FUNC_SSPM_URXD_AO (MTK_PIN_NO(43) | 6) +#define PINMUX_GPIO43__FUNC_DBG_MON_B0 (MTK_PIN_NO(43) | 7) + +#define PINMUX_GPIO44__FUNC_GPIO44 (MTK_PIN_NO(44) | 0) +#define PINMUX_GPIO44__FUNC_MD_INT2_C2K_UIM1_HOT_PLUG (MTK_PIN_NO(44) | 1) +#define PINMUX_GPIO44__FUNC_MD_INT1_C2K_UIM0_HOT_PLUG (MTK_PIN_NO(44) | 2) +#define PINMUX_GPIO44__FUNC_SDA_6306 (MTK_PIN_NO(44) | 3) +#define PINMUX_GPIO44__FUNC_ADSP_UTXD0 (MTK_PIN_NO(44) | 4) +#define PINMUX_GPIO44__FUNC_PTA_TXD (MTK_PIN_NO(44) | 5) +#define PINMUX_GPIO44__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(44) | 6) +#define PINMUX_GPIO44__FUNC_DBG_MON_B1 (MTK_PIN_NO(44) | 7) + +#define PINMUX_GPIO45__FUNC_GPIO45 (MTK_PIN_NO(45) | 0) +#define PINMUX_GPIO45__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(45) | 1) +#define PINMUX_GPIO45__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(45) | 2) +#define PINMUX_GPIO45__FUNC_MCUPM_JTAG_TDI (MTK_PIN_NO(45) | 3) +#define PINMUX_GPIO45__FUNC_APU_JTAG_TDI (MTK_PIN_NO(45) | 4) +#define PINMUX_GPIO45__FUNC_CCU_JTAG_TDI (MTK_PIN_NO(45) | 5) +#define PINMUX_GPIO45__FUNC_LVTS_SCK (MTK_PIN_NO(45) | 6) +#define PINMUX_GPIO45__FUNC_CONN_DSP_JDI (MTK_PIN_NO(45) | 7) + +#define PINMUX_GPIO46__FUNC_GPIO46 (MTK_PIN_NO(46) | 0) +#define PINMUX_GPIO46__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(46) | 1) +#define PINMUX_GPIO46__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(46) | 2) +#define PINMUX_GPIO46__FUNC_MCUPM_JTAG_TMS (MTK_PIN_NO(46) | 3) +#define PINMUX_GPIO46__FUNC_APU_JTAG_TMS (MTK_PIN_NO(46) | 4) +#define PINMUX_GPIO46__FUNC_CCU_JTAG_TMS (MTK_PIN_NO(46) | 5) +#define PINMUX_GPIO46__FUNC_LVTS_SDI (MTK_PIN_NO(46) | 6) +#define PINMUX_GPIO46__FUNC_CONN_DSP_JMS (MTK_PIN_NO(46) | 7) + +#define PINMUX_GPIO47__FUNC_GPIO47 (MTK_PIN_NO(47) | 0) +#define PINMUX_GPIO47__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(47) | 1) +#define PINMUX_GPIO47__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(47) | 2) +#define PINMUX_GPIO47__FUNC_MCUPM_JTAG_TDO (MTK_PIN_NO(47) | 3) +#define PINMUX_GPIO47__FUNC_APU_JTAG_TDO (MTK_PIN_NO(47) | 4) +#define PINMUX_GPIO47__FUNC_CCU_JTAG_TDO (MTK_PIN_NO(47) | 5) +#define PINMUX_GPIO47__FUNC_LVTS_SCF (MTK_PIN_NO(47) | 6) +#define PINMUX_GPIO47__FUNC_CONN_DSP_JDO (MTK_PIN_NO(47) | 7) + +#define PINMUX_GPIO48__FUNC_GPIO48 (MTK_PIN_NO(48) | 0) +#define PINMUX_GPIO48__FUNC_MD1_SIM1_SIO (MTK_PIN_NO(48) | 1) +#define PINMUX_GPIO48__FUNC_MD1_SIM2_SIO (MTK_PIN_NO(48) | 2) +#define PINMUX_GPIO48__FUNC_MCUPM_JTAG_TRSTN (MTK_PIN_NO(48) | 3) +#define PINMUX_GPIO48__FUNC_APU_JTAG_TRST (MTK_PIN_NO(48) | 4) +#define PINMUX_GPIO48__FUNC_CCU_JTAG_TRST (MTK_PIN_NO(48) | 5) +#define PINMUX_GPIO48__FUNC_LVTS_FOUT (MTK_PIN_NO(48) | 6) +#define PINMUX_GPIO48__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(48) | 7) + +#define PINMUX_GPIO49__FUNC_GPIO49 (MTK_PIN_NO(49) | 0) +#define PINMUX_GPIO49__FUNC_MD1_SIM1_SRST (MTK_PIN_NO(49) | 1) +#define PINMUX_GPIO49__FUNC_MD1_SIM2_SRST (MTK_PIN_NO(49) | 2) +#define PINMUX_GPIO49__FUNC_MCUPM_JTAG_TCK (MTK_PIN_NO(49) | 3) +#define PINMUX_GPIO49__FUNC_APU_JTAG_TCK (MTK_PIN_NO(49) | 4) +#define PINMUX_GPIO49__FUNC_CCU_JTAG_TCK (MTK_PIN_NO(49) | 5) +#define PINMUX_GPIO49__FUNC_LVTS_SDO (MTK_PIN_NO(49) | 6) +#define PINMUX_GPIO49__FUNC_CONN_DSP_JCK (MTK_PIN_NO(49) | 7) + +#define PINMUX_GPIO50__FUNC_GPIO50 (MTK_PIN_NO(50) | 0) +#define PINMUX_GPIO50__FUNC_MD1_SIM1_SCLK (MTK_PIN_NO(50) | 1) +#define PINMUX_GPIO50__FUNC_MD1_SIM2_SCLK (MTK_PIN_NO(50) | 2) +#define PINMUX_GPIO50__FUNC_LVTS_26M (MTK_PIN_NO(50) | 6) + +#define PINMUX_GPIO51__FUNC_GPIO51 (MTK_PIN_NO(51) | 0) +#define PINMUX_GPIO51__FUNC_MSDC1_CLK (MTK_PIN_NO(51) | 1) +#define PINMUX_GPIO51__FUNC_PCM1_CLK (MTK_PIN_NO(51) | 2) +#define PINMUX_GPIO51__FUNC_CONN_DSP_JCK (MTK_PIN_NO(51) | 3) +#define PINMUX_GPIO51__FUNC_UDI_TCK (MTK_PIN_NO(51) | 4) +#define PINMUX_GPIO51__FUNC_IPU_JTAG_TCK (MTK_PIN_NO(51) | 5) +#define PINMUX_GPIO51__FUNC_SSPM_JTAG_TCK (MTK_PIN_NO(51) | 6) +#define PINMUX_GPIO51__FUNC_JTCK_SEL3 (MTK_PIN_NO(51) | 7) + +#define PINMUX_GPIO52__FUNC_GPIO52 (MTK_PIN_NO(52) | 0) +#define PINMUX_GPIO52__FUNC_MSDC1_CMD (MTK_PIN_NO(52) | 1) +#define PINMUX_GPIO52__FUNC_PCM1_SYNC (MTK_PIN_NO(52) | 2) +#define PINMUX_GPIO52__FUNC_CONN_DSP_JMS (MTK_PIN_NO(52) | 3) +#define PINMUX_GPIO52__FUNC_UDI_TMS (MTK_PIN_NO(52) | 4) +#define PINMUX_GPIO52__FUNC_IPU_JTAG_TMS (MTK_PIN_NO(52) | 5) +#define PINMUX_GPIO52__FUNC_SSPM_JTAG_TMS (MTK_PIN_NO(52) | 6) +#define PINMUX_GPIO52__FUNC_JTMS_SEL3 (MTK_PIN_NO(52) | 7) + +#define PINMUX_GPIO53__FUNC_GPIO53 (MTK_PIN_NO(53) | 0) +#define PINMUX_GPIO53__FUNC_MSDC1_DAT3 (MTK_PIN_NO(53) | 1) +#define PINMUX_GPIO53__FUNC_PCM1_DI (MTK_PIN_NO(53) | 2) +#define PINMUX_GPIO53__FUNC_CONN_DSP_JINTP (MTK_PIN_NO(53) | 3) +#define PINMUX_GPIO53__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(53) | 4) + +#define PINMUX_GPIO54__FUNC_GPIO54 (MTK_PIN_NO(54) | 0) +#define PINMUX_GPIO54__FUNC_MSDC1_DAT0 (MTK_PIN_NO(54) | 1) +#define PINMUX_GPIO54__FUNC_PCM1_DO0 (MTK_PIN_NO(54) | 2) +#define PINMUX_GPIO54__FUNC_CONN_DSP_JDI (MTK_PIN_NO(54) | 3) +#define PINMUX_GPIO54__FUNC_UDI_TDI (MTK_PIN_NO(54) | 4) +#define PINMUX_GPIO54__FUNC_IPU_JTAG_TDI (MTK_PIN_NO(54) | 5) +#define PINMUX_GPIO54__FUNC_SSPM_JTAG_TDI (MTK_PIN_NO(54) | 6) +#define PINMUX_GPIO54__FUNC_JTDI_SEL3 (MTK_PIN_NO(54) | 7) + +#define PINMUX_GPIO55__FUNC_GPIO55 (MTK_PIN_NO(55) | 0) +#define PINMUX_GPIO55__FUNC_MSDC1_DAT2 (MTK_PIN_NO(55) | 1) +#define PINMUX_GPIO55__FUNC_PCM1_DO2 (MTK_PIN_NO(55) | 2) +#define PINMUX_GPIO55__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(55) | 3) +#define PINMUX_GPIO55__FUNC_UDI_NTRST (MTK_PIN_NO(55) | 4) +#define PINMUX_GPIO55__FUNC_IPU_JTAG_TRST (MTK_PIN_NO(55) | 5) +#define PINMUX_GPIO55__FUNC_SSPM_JTAG_TRSTN (MTK_PIN_NO(55) | 6) +#define PINMUX_GPIO55__FUNC_JTRSTN_SEL3 (MTK_PIN_NO(55) | 7) + +#define PINMUX_GPIO56__FUNC_GPIO56 (MTK_PIN_NO(56) | 0) +#define PINMUX_GPIO56__FUNC_MSDC1_DAT1 (MTK_PIN_NO(56) | 1) +#define PINMUX_GPIO56__FUNC_PCM1_DO1 (MTK_PIN_NO(56) | 2) +#define PINMUX_GPIO56__FUNC_CONN_DSP_JDO (MTK_PIN_NO(56) | 3) +#define PINMUX_GPIO56__FUNC_UDI_TDO (MTK_PIN_NO(56) | 4) +#define PINMUX_GPIO56__FUNC_IPU_JTAG_TDO (MTK_PIN_NO(56) | 5) +#define PINMUX_GPIO56__FUNC_SSPM_JTAG_TDO (MTK_PIN_NO(56) | 6) +#define PINMUX_GPIO56__FUNC_JTDO_SEL3 (MTK_PIN_NO(56) | 7) + +#define PINMUX_GPIO57__FUNC_GPIO57 (MTK_PIN_NO(57) | 0) +#define PINMUX_GPIO57__FUNC_MIPI2_D_SCLK (MTK_PIN_NO(57) | 1) + +#define PINMUX_GPIO58__FUNC_GPIO58 (MTK_PIN_NO(58) | 0) +#define PINMUX_GPIO58__FUNC_MIPI2_D_SDATA (MTK_PIN_NO(58) | 1) + +#define PINMUX_GPIO59__FUNC_GPIO59 (MTK_PIN_NO(59) | 0) +#define PINMUX_GPIO59__FUNC_MIPI_M_SCLK (MTK_PIN_NO(59) | 1) + +#define PINMUX_GPIO60__FUNC_GPIO60 (MTK_PIN_NO(60) | 0) +#define PINMUX_GPIO60__FUNC_MIPI_M_SDATA (MTK_PIN_NO(60) | 1) + +#define PINMUX_GPIO61__FUNC_GPIO61 (MTK_PIN_NO(61) | 0) +#define PINMUX_GPIO61__FUNC_MD_UCNT_A_TGL (MTK_PIN_NO(61) | 1) + +#define PINMUX_GPIO62__FUNC_GPIO62 (MTK_PIN_NO(62) | 0) +#define PINMUX_GPIO62__FUNC_DIGRF_IRQ (MTK_PIN_NO(62) | 1) + +#define PINMUX_GPIO63__FUNC_GPIO63 (MTK_PIN_NO(63) | 0) +#define PINMUX_GPIO63__FUNC_BPI_BUS0 (MTK_PIN_NO(63) | 1) +#define PINMUX_GPIO63__FUNC_PCIE_WAKE_N (MTK_PIN_NO(63) | 3) + +#define PINMUX_GPIO64__FUNC_GPIO64 (MTK_PIN_NO(64) | 0) +#define PINMUX_GPIO64__FUNC_BPI_BUS1 (MTK_PIN_NO(64) | 1) +#define PINMUX_GPIO64__FUNC_PCIE_PERESET_N (MTK_PIN_NO(64) | 3) + +#define PINMUX_GPIO65__FUNC_GPIO65 (MTK_PIN_NO(65) | 0) +#define PINMUX_GPIO65__FUNC_BPI_BUS2 (MTK_PIN_NO(65) | 1) +#define PINMUX_GPIO65__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(65) | 3) + +#define PINMUX_GPIO66__FUNC_GPIO66 (MTK_PIN_NO(66) | 0) +#define PINMUX_GPIO66__FUNC_BPI_BUS3 (MTK_PIN_NO(66) | 1) + +#define PINMUX_GPIO67__FUNC_GPIO67 (MTK_PIN_NO(67) | 0) +#define PINMUX_GPIO67__FUNC_BPI_BUS4 (MTK_PIN_NO(67) | 1) + +#define PINMUX_GPIO68__FUNC_GPIO68 (MTK_PIN_NO(68) | 0) +#define PINMUX_GPIO68__FUNC_BPI_BUS5 (MTK_PIN_NO(68) | 1) + +#define PINMUX_GPIO69__FUNC_GPIO69 (MTK_PIN_NO(69) | 0) +#define PINMUX_GPIO69__FUNC_BPI_BUS6 (MTK_PIN_NO(69) | 1) +#define PINMUX_GPIO69__FUNC_CONN_BPI_BUS6 (MTK_PIN_NO(69) | 2) + +#define PINMUX_GPIO70__FUNC_GPIO70 (MTK_PIN_NO(70) | 0) +#define PINMUX_GPIO70__FUNC_BPI_BUS7 (MTK_PIN_NO(70) | 1) +#define PINMUX_GPIO70__FUNC_CONN_BPI_BUS7 (MTK_PIN_NO(70) | 2) + +#define PINMUX_GPIO71__FUNC_GPIO71 (MTK_PIN_NO(71) | 0) +#define PINMUX_GPIO71__FUNC_BPI_BUS8 (MTK_PIN_NO(71) | 1) +#define PINMUX_GPIO71__FUNC_CONN_BPI_BUS8 (MTK_PIN_NO(71) | 2) + +#define PINMUX_GPIO72__FUNC_GPIO72 (MTK_PIN_NO(72) | 0) +#define PINMUX_GPIO72__FUNC_BPI_BUS9 (MTK_PIN_NO(72) | 1) +#define PINMUX_GPIO72__FUNC_CONN_BPI_BUS9 (MTK_PIN_NO(72) | 2) + +#define PINMUX_GPIO73__FUNC_GPIO73 (MTK_PIN_NO(73) | 0) +#define PINMUX_GPIO73__FUNC_BPI_BUS10 (MTK_PIN_NO(73) | 1) +#define PINMUX_GPIO73__FUNC_CONN_BPI_BUS10 (MTK_PIN_NO(73) | 2) + +#define PINMUX_GPIO74__FUNC_GPIO74 (MTK_PIN_NO(74) | 0) +#define PINMUX_GPIO74__FUNC_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 1) +#define PINMUX_GPIO74__FUNC_CONN_BPI_BUS11_OLAT0 (MTK_PIN_NO(74) | 2) + +#define PINMUX_GPIO75__FUNC_GPIO75 (MTK_PIN_NO(75) | 0) +#define PINMUX_GPIO75__FUNC_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 1) +#define PINMUX_GPIO75__FUNC_CONN_BPI_BUS12_OLAT1 (MTK_PIN_NO(75) | 2) + +#define PINMUX_GPIO76__FUNC_GPIO76 (MTK_PIN_NO(76) | 0) +#define PINMUX_GPIO76__FUNC_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 1) +#define PINMUX_GPIO76__FUNC_CONN_BPI_BUS13_OLAT2 (MTK_PIN_NO(76) | 2) + +#define PINMUX_GPIO77__FUNC_GPIO77 (MTK_PIN_NO(77) | 0) +#define PINMUX_GPIO77__FUNC_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 1) +#define PINMUX_GPIO77__FUNC_CONN_BPI_BUS14_OLAT3 (MTK_PIN_NO(77) | 2) + +#define PINMUX_GPIO78__FUNC_GPIO78 (MTK_PIN_NO(78) | 0) +#define PINMUX_GPIO78__FUNC_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 1) +#define PINMUX_GPIO78__FUNC_CONN_BPI_BUS15_OLAT4 (MTK_PIN_NO(78) | 2) + +#define PINMUX_GPIO79__FUNC_GPIO79 (MTK_PIN_NO(79) | 0) +#define PINMUX_GPIO79__FUNC_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 1) +#define PINMUX_GPIO79__FUNC_CONN_BPI_BUS16_OLAT5 (MTK_PIN_NO(79) | 2) + +#define PINMUX_GPIO80__FUNC_GPIO80 (MTK_PIN_NO(80) | 0) +#define PINMUX_GPIO80__FUNC_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 1) +#define PINMUX_GPIO80__FUNC_CONN_BPI_BUS17_ANT0 (MTK_PIN_NO(80) | 2) +#define PINMUX_GPIO80__FUNC_PCIE_WAKE_N (MTK_PIN_NO(80) | 3) + +#define PINMUX_GPIO81__FUNC_GPIO81 (MTK_PIN_NO(81) | 0) +#define PINMUX_GPIO81__FUNC_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 1) +#define PINMUX_GPIO81__FUNC_CONN_BPI_BUS18_ANT1 (MTK_PIN_NO(81) | 2) +#define PINMUX_GPIO81__FUNC_PCIE_PERESET_N (MTK_PIN_NO(81) | 3) + +#define PINMUX_GPIO82__FUNC_GPIO82 (MTK_PIN_NO(82) | 0) +#define PINMUX_GPIO82__FUNC_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 1) +#define PINMUX_GPIO82__FUNC_CONN_BPI_BUS19_ANT2 (MTK_PIN_NO(82) | 2) +#define PINMUX_GPIO82__FUNC_PCIE_CLKREQ_N (MTK_PIN_NO(82) | 3) + +#define PINMUX_GPIO83__FUNC_GPIO83 (MTK_PIN_NO(83) | 0) +#define PINMUX_GPIO83__FUNC_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 1) +#define PINMUX_GPIO83__FUNC_CONN_BPI_BUS20_ANT3 (MTK_PIN_NO(83) | 2) + +#define PINMUX_GPIO84__FUNC_GPIO84 (MTK_PIN_NO(84) | 0) +#define PINMUX_GPIO84__FUNC_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 1) +#define PINMUX_GPIO84__FUNC_CONN_BPI_BUS21_ANT4 (MTK_PIN_NO(84) | 2) + +#define PINMUX_GPIO85__FUNC_GPIO85 (MTK_PIN_NO(85) | 0) +#define PINMUX_GPIO85__FUNC_MIPI1_D_SCLK (MTK_PIN_NO(85) | 1) +#define PINMUX_GPIO85__FUNC_CONN_MIPI1_SCLK (MTK_PIN_NO(85) | 2) + +#define PINMUX_GPIO86__FUNC_GPIO86 (MTK_PIN_NO(86) | 0) +#define PINMUX_GPIO86__FUNC_MIPI1_D_SDATA (MTK_PIN_NO(86) | 1) +#define PINMUX_GPIO86__FUNC_CONN_MIPI1_SDATA (MTK_PIN_NO(86) | 2) + +#define PINMUX_GPIO87__FUNC_GPIO87 (MTK_PIN_NO(87) | 0) +#define PINMUX_GPIO87__FUNC_MIPI0_D_SCLK (MTK_PIN_NO(87) | 1) +#define PINMUX_GPIO87__FUNC_CONN_MIPI0_SCLK (MTK_PIN_NO(87) | 2) + +#define PINMUX_GPIO88__FUNC_GPIO88 (MTK_PIN_NO(88) | 0) +#define PINMUX_GPIO88__FUNC_MIPI0_D_SDATA (MTK_PIN_NO(88) | 1) +#define PINMUX_GPIO88__FUNC_CONN_MIPI0_SDATA (MTK_PIN_NO(88) | 2) + +#define PINMUX_GPIO89__FUNC_GPIO89 (MTK_PIN_NO(89) | 0) +#define PINMUX_GPIO89__FUNC_SPMI_SCL (MTK_PIN_NO(89) | 1) +#define PINMUX_GPIO89__FUNC_SCL10 (MTK_PIN_NO(89) | 2) + +#define PINMUX_GPIO90__FUNC_GPIO90 (MTK_PIN_NO(90) | 0) +#define PINMUX_GPIO90__FUNC_SPMI_SDA (MTK_PIN_NO(90) | 1) +#define PINMUX_GPIO90__FUNC_SDA10 (MTK_PIN_NO(90) | 2) + +#define PINMUX_GPIO91__FUNC_GPIO91 (MTK_PIN_NO(91) | 0) +#define PINMUX_GPIO91__FUNC_AP_GOOD (MTK_PIN_NO(91) | 1) + +#define PINMUX_GPIO92__FUNC_GPIO92 (MTK_PIN_NO(92) | 0) +#define PINMUX_GPIO92__FUNC_URXD0 (MTK_PIN_NO(92) | 1) +#define PINMUX_GPIO92__FUNC_MD_URXD0 (MTK_PIN_NO(92) | 2) +#define PINMUX_GPIO92__FUNC_MD_URXD1 (MTK_PIN_NO(92) | 3) +#define PINMUX_GPIO92__FUNC_SSPM_URXD_AO (MTK_PIN_NO(92) | 4) +#define PINMUX_GPIO92__FUNC_CONN_UART0_RXD (MTK_PIN_NO(92) | 5) + +#define PINMUX_GPIO93__FUNC_GPIO93 (MTK_PIN_NO(93) | 0) +#define PINMUX_GPIO93__FUNC_UTXD0 (MTK_PIN_NO(93) | 1) +#define PINMUX_GPIO93__FUNC_MD_UTXD0 (MTK_PIN_NO(93) | 2) +#define PINMUX_GPIO93__FUNC_MD_UTXD1 (MTK_PIN_NO(93) | 3) +#define PINMUX_GPIO93__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(93) | 4) +#define PINMUX_GPIO93__FUNC_CONN_UART0_TXD (MTK_PIN_NO(93) | 5) +#define PINMUX_GPIO93__FUNC_WIFI_TXD (MTK_PIN_NO(93) | 6) + +#define PINMUX_GPIO94__FUNC_GPIO94 (MTK_PIN_NO(94) | 0) +#define PINMUX_GPIO94__FUNC_URXD1 (MTK_PIN_NO(94) | 1) +#define PINMUX_GPIO94__FUNC_ADSP_URXD0 (MTK_PIN_NO(94) | 2) +#define PINMUX_GPIO94__FUNC_MD32_0_RXD (MTK_PIN_NO(94) | 3) +#define PINMUX_GPIO94__FUNC_SSPM_URXD_AO (MTK_PIN_NO(94) | 4) +#define PINMUX_GPIO94__FUNC_TP_URXD1_AO (MTK_PIN_NO(94) | 5) +#define PINMUX_GPIO94__FUNC_TP_URXD2_AO (MTK_PIN_NO(94) | 6) +#define PINMUX_GPIO94__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(94) | 7) + +#define PINMUX_GPIO95__FUNC_GPIO95 (MTK_PIN_NO(95) | 0) +#define PINMUX_GPIO95__FUNC_UTXD1 (MTK_PIN_NO(95) | 1) +#define PINMUX_GPIO95__FUNC_ADSP_UTXD0 (MTK_PIN_NO(95) | 2) +#define PINMUX_GPIO95__FUNC_MD32_0_TXD (MTK_PIN_NO(95) | 3) +#define PINMUX_GPIO95__FUNC_SSPM_UTXD_AO (MTK_PIN_NO(95) | 4) +#define PINMUX_GPIO95__FUNC_TP_UTXD1_AO (MTK_PIN_NO(95) | 5) +#define PINMUX_GPIO95__FUNC_TP_UTXD2_AO (MTK_PIN_NO(95) | 6) +#define PINMUX_GPIO95__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(95) | 7) + +#define PINMUX_GPIO96__FUNC_GPIO96 (MTK_PIN_NO(96) | 0) +#define PINMUX_GPIO96__FUNC_TDM_LRCK (MTK_PIN_NO(96) | 1) +#define PINMUX_GPIO96__FUNC_I2S7_LRCK (MTK_PIN_NO(96) | 2) +#define PINMUX_GPIO96__FUNC_I2S9_LRCK (MTK_PIN_NO(96) | 3) +#define PINMUX_GPIO96__FUNC_DPI_D0 (MTK_PIN_NO(96) | 4) +#define PINMUX_GPIO96__FUNC_ADSP_JTAG0_TDI (MTK_PIN_NO(96) | 5) +#define PINMUX_GPIO96__FUNC_IO_JTAG_TDI (MTK_PIN_NO(96) | 7) + +#define PINMUX_GPIO97__FUNC_GPIO97 (MTK_PIN_NO(97) | 0) +#define PINMUX_GPIO97__FUNC_TDM_BCK (MTK_PIN_NO(97) | 1) +#define PINMUX_GPIO97__FUNC_I2S7_BCK (MTK_PIN_NO(97) | 2) +#define PINMUX_GPIO97__FUNC_I2S9_BCK (MTK_PIN_NO(97) | 3) +#define PINMUX_GPIO97__FUNC_DPI_D1 (MTK_PIN_NO(97) | 4) +#define PINMUX_GPIO97__FUNC_ADSP_JTAG0_TRSTN (MTK_PIN_NO(97) | 5) +#define PINMUX_GPIO97__FUNC_IO_JTAG_TRSTN (MTK_PIN_NO(97) | 7) + +#define PINMUX_GPIO98__FUNC_GPIO98 (MTK_PIN_NO(98) | 0) +#define PINMUX_GPIO98__FUNC_TDM_MCK (MTK_PIN_NO(98) | 1) +#define PINMUX_GPIO98__FUNC_I2S7_MCK (MTK_PIN_NO(98) | 2) +#define PINMUX_GPIO98__FUNC_I2S9_MCK (MTK_PIN_NO(98) | 3) +#define PINMUX_GPIO98__FUNC_DPI_D2 (MTK_PIN_NO(98) | 4) +#define PINMUX_GPIO98__FUNC_ADSP_JTAG0_TCK (MTK_PIN_NO(98) | 5) +#define PINMUX_GPIO98__FUNC_IO_JTAG_TCK (MTK_PIN_NO(98) | 7) + +#define PINMUX_GPIO99__FUNC_GPIO99 (MTK_PIN_NO(99) | 0) +#define PINMUX_GPIO99__FUNC_TDM_DATA0 (MTK_PIN_NO(99) | 1) +#define PINMUX_GPIO99__FUNC_I2S6_DI (MTK_PIN_NO(99) | 2) +#define PINMUX_GPIO99__FUNC_I2S8_DI (MTK_PIN_NO(99) | 3) +#define PINMUX_GPIO99__FUNC_DPI_D3 (MTK_PIN_NO(99) | 4) +#define PINMUX_GPIO99__FUNC_ADSP_JTAG0_TDO (MTK_PIN_NO(99) | 5) +#define PINMUX_GPIO99__FUNC_IO_JTAG_TDO (MTK_PIN_NO(99) | 7) + +#define PINMUX_GPIO100__FUNC_GPIO100 (MTK_PIN_NO(100) | 0) +#define PINMUX_GPIO100__FUNC_TDM_DATA1 (MTK_PIN_NO(100) | 1) +#define PINMUX_GPIO100__FUNC_I2S7_DO (MTK_PIN_NO(100) | 2) +#define PINMUX_GPIO100__FUNC_I2S9_DO (MTK_PIN_NO(100) | 3) +#define PINMUX_GPIO100__FUNC_DPI_D4 (MTK_PIN_NO(100) | 4) +#define PINMUX_GPIO100__FUNC_ADSP_JTAG0_TMS (MTK_PIN_NO(100) | 5) +#define PINMUX_GPIO100__FUNC_IO_JTAG_TMS (MTK_PIN_NO(100) | 7) + +#define PINMUX_GPIO101__FUNC_GPIO101 (MTK_PIN_NO(101) | 0) +#define PINMUX_GPIO101__FUNC_TDM_DATA2 (MTK_PIN_NO(101) | 1) +#define PINMUX_GPIO101__FUNC_DMIC1_CLK (MTK_PIN_NO(101) | 2) +#define PINMUX_GPIO101__FUNC_SRCLKENAI0 (MTK_PIN_NO(101) | 3) +#define PINMUX_GPIO101__FUNC_DPI_D5 (MTK_PIN_NO(101) | 4) +#define PINMUX_GPIO101__FUNC_CLKM0 (MTK_PIN_NO(101) | 5) +#define PINMUX_GPIO101__FUNC_DAP_MD32_SWD (MTK_PIN_NO(101) | 7) + +#define PINMUX_GPIO102__FUNC_GPIO102 (MTK_PIN_NO(102) | 0) +#define PINMUX_GPIO102__FUNC_TDM_DATA3 (MTK_PIN_NO(102) | 1) +#define PINMUX_GPIO102__FUNC_DMIC1_DAT (MTK_PIN_NO(102) | 2) +#define PINMUX_GPIO102__FUNC_SRCLKENAI1 (MTK_PIN_NO(102) | 3) +#define PINMUX_GPIO102__FUNC_DPI_D6 (MTK_PIN_NO(102) | 4) +#define PINMUX_GPIO102__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(102) | 6) +#define PINMUX_GPIO102__FUNC_DAP_MD32_SWCK (MTK_PIN_NO(102) | 7) + +#define PINMUX_GPIO103__FUNC_GPIO103 (MTK_PIN_NO(103) | 0) +#define PINMUX_GPIO103__FUNC_SPI0_A_MI (MTK_PIN_NO(103) | 1) +#define PINMUX_GPIO103__FUNC_SCP_SPI0_MI (MTK_PIN_NO(103) | 2) +#define PINMUX_GPIO103__FUNC_DPI_D7 (MTK_PIN_NO(103) | 4) +#define PINMUX_GPIO103__FUNC_DFD_TDO (MTK_PIN_NO(103) | 5) +#define PINMUX_GPIO103__FUNC_SPM_JTAG_TDO (MTK_PIN_NO(103) | 6) +#define PINMUX_GPIO103__FUNC_JTDO_SEL1 (MTK_PIN_NO(103) | 7) + +#define PINMUX_GPIO104__FUNC_GPIO104 (MTK_PIN_NO(104) | 0) +#define PINMUX_GPIO104__FUNC_SPI0_A_CSB (MTK_PIN_NO(104) | 1) +#define PINMUX_GPIO104__FUNC_SCP_SPI0_CS (MTK_PIN_NO(104) | 2) +#define PINMUX_GPIO104__FUNC_DPI_D8 (MTK_PIN_NO(104) | 4) +#define PINMUX_GPIO104__FUNC_DFD_TMS (MTK_PIN_NO(104) | 5) +#define PINMUX_GPIO104__FUNC_SPM_JTAG_TMS (MTK_PIN_NO(104) | 6) +#define PINMUX_GPIO104__FUNC_JTMS_SEL1 (MTK_PIN_NO(104) | 7) + +#define PINMUX_GPIO105__FUNC_GPIO105 (MTK_PIN_NO(105) | 0) +#define PINMUX_GPIO105__FUNC_SPI0_A_MO (MTK_PIN_NO(105) | 1) +#define PINMUX_GPIO105__FUNC_SCP_SPI0_MO (MTK_PIN_NO(105) | 2) +#define PINMUX_GPIO105__FUNC_SCP_SDA0 (MTK_PIN_NO(105) | 3) +#define PINMUX_GPIO105__FUNC_DPI_D9 (MTK_PIN_NO(105) | 4) +#define PINMUX_GPIO105__FUNC_DFD_TDI (MTK_PIN_NO(105) | 5) +#define PINMUX_GPIO105__FUNC_SPM_JTAG_TDI (MTK_PIN_NO(105) | 6) +#define PINMUX_GPIO105__FUNC_JTDI_SEL1 (MTK_PIN_NO(105) | 7) + +#define PINMUX_GPIO106__FUNC_GPIO106 (MTK_PIN_NO(106) | 0) +#define PINMUX_GPIO106__FUNC_SPI0_A_CLK (MTK_PIN_NO(106) | 1) +#define PINMUX_GPIO106__FUNC_SCP_SPI0_CK (MTK_PIN_NO(106) | 2) +#define PINMUX_GPIO106__FUNC_SCP_SCL0 (MTK_PIN_NO(106) | 3) +#define PINMUX_GPIO106__FUNC_DPI_D10 (MTK_PIN_NO(106) | 4) +#define PINMUX_GPIO106__FUNC_DFD_TCK_XI (MTK_PIN_NO(106) | 5) +#define PINMUX_GPIO106__FUNC_SPM_JTAG_TCK (MTK_PIN_NO(106) | 6) +#define PINMUX_GPIO106__FUNC_JTCK_SEL1 (MTK_PIN_NO(106) | 7) + +#define PINMUX_GPIO107__FUNC_GPIO107 (MTK_PIN_NO(107) | 0) +#define PINMUX_GPIO107__FUNC_DMIC_CLK (MTK_PIN_NO(107) | 1) +#define PINMUX_GPIO107__FUNC_PWM_0 (MTK_PIN_NO(107) | 2) +#define PINMUX_GPIO107__FUNC_CLKM2 (MTK_PIN_NO(107) | 3) +#define PINMUX_GPIO107__FUNC_SPM_JTAG_TRSTN (MTK_PIN_NO(107) | 6) +#define PINMUX_GPIO107__FUNC_JTRSTN_SEL1 (MTK_PIN_NO(107) | 7) + +#define PINMUX_GPIO108__FUNC_GPIO108 (MTK_PIN_NO(108) | 0) +#define PINMUX_GPIO108__FUNC_DMIC_DAT (MTK_PIN_NO(108) | 1) +#define PINMUX_GPIO108__FUNC_PWM_1 (MTK_PIN_NO(108) | 2) +#define PINMUX_GPIO108__FUNC_CLKM3 (MTK_PIN_NO(108) | 3) +#define PINMUX_GPIO108__FUNC_DAP_SONIC_SWD (MTK_PIN_NO(108) | 7) + +#define PINMUX_GPIO109__FUNC_GPIO109 (MTK_PIN_NO(109) | 0) +#define PINMUX_GPIO109__FUNC_I2S1_MCK (MTK_PIN_NO(109) | 1) +#define PINMUX_GPIO109__FUNC_I2S3_MCK (MTK_PIN_NO(109) | 2) +#define PINMUX_GPIO109__FUNC_I2S2_MCK (MTK_PIN_NO(109) | 3) +#define PINMUX_GPIO109__FUNC_DPI_DE (MTK_PIN_NO(109) | 4) +#define PINMUX_GPIO109__FUNC_I2S2_MCK_A (MTK_PIN_NO(109) | 5) +#define PINMUX_GPIO109__FUNC_SRCLKENAI0 (MTK_PIN_NO(109) | 6) +#define PINMUX_GPIO109__FUNC_DAP_SONIC_SWCK (MTK_PIN_NO(109) | 7) + +#define PINMUX_GPIO110__FUNC_GPIO110 (MTK_PIN_NO(110) | 0) +#define PINMUX_GPIO110__FUNC_I2S1_BCK (MTK_PIN_NO(110) | 1) +#define PINMUX_GPIO110__FUNC_I2S3_BCK (MTK_PIN_NO(110) | 2) +#define PINMUX_GPIO110__FUNC_I2S2_BCK (MTK_PIN_NO(110) | 3) +#define PINMUX_GPIO110__FUNC_DPI_D11 (MTK_PIN_NO(110) | 4) +#define PINMUX_GPIO110__FUNC_I2S2_BCK_A (MTK_PIN_NO(110) | 5) +#define PINMUX_GPIO110__FUNC_CONN_MCU_TDO (MTK_PIN_NO(110) | 6) + +#define PINMUX_GPIO111__FUNC_GPIO111 (MTK_PIN_NO(111) | 0) +#define PINMUX_GPIO111__FUNC_I2S1_LRCK (MTK_PIN_NO(111) | 1) +#define PINMUX_GPIO111__FUNC_I2S3_LRCK (MTK_PIN_NO(111) | 2) +#define PINMUX_GPIO111__FUNC_I2S2_LRCK (MTK_PIN_NO(111) | 3) +#define PINMUX_GPIO111__FUNC_DPI_VSYNC (MTK_PIN_NO(111) | 4) +#define PINMUX_GPIO111__FUNC_I2S2_LRCK_A (MTK_PIN_NO(111) | 5) +#define PINMUX_GPIO111__FUNC_CONN_MCU_TDI (MTK_PIN_NO(111) | 6) + +#define PINMUX_GPIO112__FUNC_GPIO112 (MTK_PIN_NO(112) | 0) +#define PINMUX_GPIO112__FUNC_I2S2_DI (MTK_PIN_NO(112) | 1) +#define PINMUX_GPIO112__FUNC_I2S0_DI (MTK_PIN_NO(112) | 2) +#define PINMUX_GPIO112__FUNC_I2S2_DI2 (MTK_PIN_NO(112) | 3) +#define PINMUX_GPIO112__FUNC_DPI_CK (MTK_PIN_NO(112) | 4) +#define PINMUX_GPIO112__FUNC_I2S2_DI_A (MTK_PIN_NO(112) | 5) +#define PINMUX_GPIO112__FUNC_CONN_MCU_TMS (MTK_PIN_NO(112) | 6) + +#define PINMUX_GPIO113__FUNC_GPIO113 (MTK_PIN_NO(113) | 0) +#define PINMUX_GPIO113__FUNC_I2S1_DO (MTK_PIN_NO(113) | 1) +#define PINMUX_GPIO113__FUNC_I2S3_DO (MTK_PIN_NO(113) | 2) +#define PINMUX_GPIO113__FUNC_I2S5_DO (MTK_PIN_NO(113) | 3) +#define PINMUX_GPIO113__FUNC_DPI_HSYNC (MTK_PIN_NO(113) | 4) +#define PINMUX_GPIO113__FUNC_I2S2_DI2 (MTK_PIN_NO(113) | 5) +#define PINMUX_GPIO113__FUNC_CONN_MCU_TCK (MTK_PIN_NO(113) | 6) + +#define PINMUX_GPIO114__FUNC_GPIO114 (MTK_PIN_NO(114) | 0) +#define PINMUX_GPIO114__FUNC_SPI2_MI (MTK_PIN_NO(114) | 1) +#define PINMUX_GPIO114__FUNC_SCP_SPI2_MI (MTK_PIN_NO(114) | 2) +#define PINMUX_GPIO114__FUNC_PCM0_DI (MTK_PIN_NO(114) | 4) +#define PINMUX_GPIO114__FUNC_CONN_MCU_TRST_B (MTK_PIN_NO(114) | 6) + +#define PINMUX_GPIO115__FUNC_GPIO115 (MTK_PIN_NO(115) | 0) +#define PINMUX_GPIO115__FUNC_SPI2_CSB (MTK_PIN_NO(115) | 1) +#define PINMUX_GPIO115__FUNC_SCP_SPI2_CS (MTK_PIN_NO(115) | 2) +#define PINMUX_GPIO115__FUNC_PCM0_SYNC (MTK_PIN_NO(115) | 4) +#define PINMUX_GPIO115__FUNC_CONN_MCU_DBGI_N (MTK_PIN_NO(115) | 6) + +#define PINMUX_GPIO116__FUNC_GPIO116 (MTK_PIN_NO(116) | 0) +#define PINMUX_GPIO116__FUNC_SPI2_MO (MTK_PIN_NO(116) | 1) +#define PINMUX_GPIO116__FUNC_SCP_SPI2_MO (MTK_PIN_NO(116) | 2) +#define PINMUX_GPIO116__FUNC_SCP_SDA1 (MTK_PIN_NO(116) | 3) +#define PINMUX_GPIO116__FUNC_PCM0_DO (MTK_PIN_NO(116) | 4) +#define PINMUX_GPIO116__FUNC_CONN_MCU_DBGACK_N (MTK_PIN_NO(116) | 6) + +#define PINMUX_GPIO117__FUNC_GPIO117 (MTK_PIN_NO(117) | 0) +#define PINMUX_GPIO117__FUNC_SPI2_CLK (MTK_PIN_NO(117) | 1) +#define PINMUX_GPIO117__FUNC_SCP_SPI2_CK (MTK_PIN_NO(117) | 2) +#define PINMUX_GPIO117__FUNC_SCP_SCL1 (MTK_PIN_NO(117) | 3) +#define PINMUX_GPIO117__FUNC_PCM0_CLK (MTK_PIN_NO(117) | 4) + +#define PINMUX_GPIO118__FUNC_GPIO118 (MTK_PIN_NO(118) | 0) +#define PINMUX_GPIO118__FUNC_SCL1 (MTK_PIN_NO(118) | 1) +#define PINMUX_GPIO118__FUNC_SCP_SCL0 (MTK_PIN_NO(118) | 2) +#define PINMUX_GPIO118__FUNC_SCP_SCL1 (MTK_PIN_NO(118) | 3) + +#define PINMUX_GPIO119__FUNC_GPIO119 (MTK_PIN_NO(119) | 0) +#define PINMUX_GPIO119__FUNC_SDA1 (MTK_PIN_NO(119) | 1) +#define PINMUX_GPIO119__FUNC_SCP_SDA0 (MTK_PIN_NO(119) | 2) +#define PINMUX_GPIO119__FUNC_SCP_SDA1 (MTK_PIN_NO(119) | 3) + +#define PINMUX_GPIO120__FUNC_GPIO120 (MTK_PIN_NO(120) | 0) +#define PINMUX_GPIO120__FUNC_SCL9 (MTK_PIN_NO(120) | 1) +#define PINMUX_GPIO120__FUNC_SCP_SCL0 (MTK_PIN_NO(120) | 2) + +#define PINMUX_GPIO121__FUNC_GPIO121 (MTK_PIN_NO(121) | 0) +#define PINMUX_GPIO121__FUNC_SDA9 (MTK_PIN_NO(121) | 1) +#define PINMUX_GPIO121__FUNC_SCP_SDA0 (MTK_PIN_NO(121) | 2) + +#define PINMUX_GPIO122__FUNC_GPIO122 (MTK_PIN_NO(122) | 0) +#define PINMUX_GPIO122__FUNC_SCL8 (MTK_PIN_NO(122) | 1) +#define PINMUX_GPIO122__FUNC_SCP_SDA0 (MTK_PIN_NO(122) | 2) + +#define PINMUX_GPIO123__FUNC_GPIO123 (MTK_PIN_NO(123) | 0) +#define PINMUX_GPIO123__FUNC_SDA8 (MTK_PIN_NO(123) | 1) +#define PINMUX_GPIO123__FUNC_SCP_SCL0 (MTK_PIN_NO(123) | 2) + +#define PINMUX_GPIO124__FUNC_GPIO124 (MTK_PIN_NO(124) | 0) +#define PINMUX_GPIO124__FUNC_SCL7 (MTK_PIN_NO(124) | 1) +#define PINMUX_GPIO124__FUNC_DMIC1_CLK (MTK_PIN_NO(124) | 2) + +#define PINMUX_GPIO125__FUNC_GPIO125 (MTK_PIN_NO(125) | 0) +#define PINMUX_GPIO125__FUNC_SDA7 (MTK_PIN_NO(125) | 1) +#define PINMUX_GPIO125__FUNC_DMIC1_DAT (MTK_PIN_NO(125) | 2) + +#define PINMUX_GPIO126__FUNC_GPIO126 (MTK_PIN_NO(126) | 0) +#define PINMUX_GPIO126__FUNC_CMFLASH0 (MTK_PIN_NO(126) | 1) +#define PINMUX_GPIO126__FUNC_PWM_2 (MTK_PIN_NO(126) | 2) +#define PINMUX_GPIO126__FUNC_TP_UCTS1_AO (MTK_PIN_NO(126) | 3) +#define PINMUX_GPIO126__FUNC_UCTS0 (MTK_PIN_NO(126) | 4) +#define PINMUX_GPIO126__FUNC_SCL11 (MTK_PIN_NO(126) | 5) +#define PINMUX_GPIO126__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(126) | 6) +#define PINMUX_GPIO126__FUNC_DBG_MON_A14 (MTK_PIN_NO(126) | 7) + +#define PINMUX_GPIO127__FUNC_GPIO127 (MTK_PIN_NO(127) | 0) +#define PINMUX_GPIO127__FUNC_CMFLASH1 (MTK_PIN_NO(127) | 1) +#define PINMUX_GPIO127__FUNC_PWM_3 (MTK_PIN_NO(127) | 2) +#define PINMUX_GPIO127__FUNC_TP_URTS1_AO (MTK_PIN_NO(127) | 3) +#define PINMUX_GPIO127__FUNC_URTS0 (MTK_PIN_NO(127) | 4) +#define PINMUX_GPIO127__FUNC_SDA11 (MTK_PIN_NO(127) | 5) +#define PINMUX_GPIO127__FUNC_DBG_MON_A15 (MTK_PIN_NO(127) | 7) + +#define PINMUX_GPIO128__FUNC_GPIO128 (MTK_PIN_NO(128) | 0) +#define PINMUX_GPIO128__FUNC_CMFLASH2 (MTK_PIN_NO(128) | 1) +#define PINMUX_GPIO128__FUNC_PWM_0 (MTK_PIN_NO(128) | 2) +#define PINMUX_GPIO128__FUNC_TP_UCTS2_AO (MTK_PIN_NO(128) | 3) +#define PINMUX_GPIO128__FUNC_UCTS1 (MTK_PIN_NO(128) | 4) +#define PINMUX_GPIO128__FUNC_SCL_6306 (MTK_PIN_NO(128) | 5) +#define PINMUX_GPIO128__FUNC_DBG_MON_A16 (MTK_PIN_NO(128) | 7) + +#define PINMUX_GPIO129__FUNC_GPIO129 (MTK_PIN_NO(129) | 0) +#define PINMUX_GPIO129__FUNC_CMFLASH3 (MTK_PIN_NO(129) | 1) +#define PINMUX_GPIO129__FUNC_PWM_1 (MTK_PIN_NO(129) | 2) +#define PINMUX_GPIO129__FUNC_TP_URTS2_AO (MTK_PIN_NO(129) | 3) +#define PINMUX_GPIO129__FUNC_URTS1 (MTK_PIN_NO(129) | 4) +#define PINMUX_GPIO129__FUNC_SDA_6306 (MTK_PIN_NO(129) | 5) +#define PINMUX_GPIO129__FUNC_DBG_MON_A17 (MTK_PIN_NO(129) | 7) + +#define PINMUX_GPIO130__FUNC_GPIO130 (MTK_PIN_NO(130) | 0) +#define PINMUX_GPIO130__FUNC_CMVREF0 (MTK_PIN_NO(130) | 1) +#define PINMUX_GPIO130__FUNC_ANT_SEL10 (MTK_PIN_NO(130) | 2) +#define PINMUX_GPIO130__FUNC_SCP_JTAG0_TDO (MTK_PIN_NO(130) | 3) +#define PINMUX_GPIO130__FUNC_MD32_0_JTAG_TDO (MTK_PIN_NO(130) | 4) +#define PINMUX_GPIO130__FUNC_SCL11 (MTK_PIN_NO(130) | 5) +#define PINMUX_GPIO130__FUNC_SPI5_B_CLK (MTK_PIN_NO(130) | 6) +#define PINMUX_GPIO130__FUNC_DBG_MON_A22 (MTK_PIN_NO(130) | 7) + +#define PINMUX_GPIO131__FUNC_GPIO131 (MTK_PIN_NO(131) | 0) +#define PINMUX_GPIO131__FUNC_CMVREF1 (MTK_PIN_NO(131) | 1) +#define PINMUX_GPIO131__FUNC_ANT_SEL11 (MTK_PIN_NO(131) | 2) +#define PINMUX_GPIO131__FUNC_SCP_JTAG0_TDI (MTK_PIN_NO(131) | 3) +#define PINMUX_GPIO131__FUNC_MD32_0_JTAG_TDI (MTK_PIN_NO(131) | 4) +#define PINMUX_GPIO131__FUNC_SDA11 (MTK_PIN_NO(131) | 5) +#define PINMUX_GPIO131__FUNC_SPI5_B_MO (MTK_PIN_NO(131) | 6) +#define PINMUX_GPIO131__FUNC_DBG_MON_A25 (MTK_PIN_NO(131) | 7) + +#define PINMUX_GPIO132__FUNC_GPIO132 (MTK_PIN_NO(132) | 0) +#define PINMUX_GPIO132__FUNC_CMVREF2 (MTK_PIN_NO(132) | 1) +#define PINMUX_GPIO132__FUNC_ANT_SEL12 (MTK_PIN_NO(132) | 2) +#define PINMUX_GPIO132__FUNC_SCP_JTAG0_TMS (MTK_PIN_NO(132) | 3) +#define PINMUX_GPIO132__FUNC_MD32_0_JTAG_TMS (MTK_PIN_NO(132) | 4) +#define PINMUX_GPIO132__FUNC_DBG_MON_A28 (MTK_PIN_NO(132) | 7) + +#define PINMUX_GPIO133__FUNC_GPIO133 (MTK_PIN_NO(133) | 0) +#define PINMUX_GPIO133__FUNC_CMVREF3 (MTK_PIN_NO(133) | 1) +#define PINMUX_GPIO133__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(133) | 2) +#define PINMUX_GPIO133__FUNC_SCP_JTAG0_TCK (MTK_PIN_NO(133) | 3) +#define PINMUX_GPIO133__FUNC_MD32_0_JTAG_TCK (MTK_PIN_NO(133) | 4) +#define PINMUX_GPIO133__FUNC_SPI5_B_CSB (MTK_PIN_NO(133) | 6) +#define PINMUX_GPIO133__FUNC_DBG_MON_A23 (MTK_PIN_NO(133) | 7) + +#define PINMUX_GPIO134__FUNC_GPIO134 (MTK_PIN_NO(134) | 0) +#define PINMUX_GPIO134__FUNC_CMVREF4 (MTK_PIN_NO(134) | 1) +#define PINMUX_GPIO134__FUNC_SCP_JTAG0_TRSTN (MTK_PIN_NO(134) | 3) +#define PINMUX_GPIO134__FUNC_MD32_0_JTAG_TRST (MTK_PIN_NO(134) | 4) +#define PINMUX_GPIO134__FUNC_DBG_MON_A26 (MTK_PIN_NO(134) | 7) + +#define PINMUX_GPIO135__FUNC_GPIO135 (MTK_PIN_NO(135) | 0) +#define PINMUX_GPIO135__FUNC_PWM_0 (MTK_PIN_NO(135) | 1) +#define PINMUX_GPIO135__FUNC_SRCLKENAI1 (MTK_PIN_NO(135) | 2) +#define PINMUX_GPIO135__FUNC_MD_URXD0 (MTK_PIN_NO(135) | 3) +#define PINMUX_GPIO135__FUNC_MD32_0_RXD (MTK_PIN_NO(135) | 4) +#define PINMUX_GPIO135__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(135) | 5) +#define PINMUX_GPIO135__FUNC_DBG_MON_A29 (MTK_PIN_NO(135) | 7) + +#define PINMUX_GPIO136__FUNC_GPIO136 (MTK_PIN_NO(136) | 0) +#define PINMUX_GPIO136__FUNC_CMMCLK3 (MTK_PIN_NO(136) | 1) +#define PINMUX_GPIO136__FUNC_CLKM1 (MTK_PIN_NO(136) | 2) +#define PINMUX_GPIO136__FUNC_MD_UTXD0 (MTK_PIN_NO(136) | 3) +#define PINMUX_GPIO136__FUNC_MD32_0_TXD (MTK_PIN_NO(136) | 4) +#define PINMUX_GPIO136__FUNC_SPI5_B_MI (MTK_PIN_NO(136) | 6) +#define PINMUX_GPIO136__FUNC_DBG_MON_A24 (MTK_PIN_NO(136) | 7) + +#define PINMUX_GPIO137__FUNC_GPIO137 (MTK_PIN_NO(137) | 0) +#define PINMUX_GPIO137__FUNC_CMMCLK4 (MTK_PIN_NO(137) | 1) +#define PINMUX_GPIO137__FUNC_CLKM2 (MTK_PIN_NO(137) | 2) +#define PINMUX_GPIO137__FUNC_MD_URXD1 (MTK_PIN_NO(137) | 3) +#define PINMUX_GPIO137__FUNC_CONN_UART0_RXD (MTK_PIN_NO(137) | 6) +#define PINMUX_GPIO137__FUNC_DBG_MON_A27 (MTK_PIN_NO(137) | 7) + +#define PINMUX_GPIO138__FUNC_GPIO138 (MTK_PIN_NO(138) | 0) +#define PINMUX_GPIO138__FUNC_CMMCLK5 (MTK_PIN_NO(138) | 1) +#define PINMUX_GPIO138__FUNC_CLKM3 (MTK_PIN_NO(138) | 2) +#define PINMUX_GPIO138__FUNC_MD_UTXD1 (MTK_PIN_NO(138) | 3) +#define PINMUX_GPIO138__FUNC_CONN_UART0_TXD (MTK_PIN_NO(138) | 6) +#define PINMUX_GPIO138__FUNC_DBG_MON_A30 (MTK_PIN_NO(138) | 7) + +#define PINMUX_GPIO139__FUNC_GPIO139 (MTK_PIN_NO(139) | 0) +#define PINMUX_GPIO139__FUNC_SCL4 (MTK_PIN_NO(139) | 1) +#define PINMUX_GPIO139__FUNC_DBG_MON_A21 (MTK_PIN_NO(139) | 7) + +#define PINMUX_GPIO140__FUNC_GPIO140 (MTK_PIN_NO(140) | 0) +#define PINMUX_GPIO140__FUNC_SDA4 (MTK_PIN_NO(140) | 1) +#define PINMUX_GPIO140__FUNC_DBG_MON_A20 (MTK_PIN_NO(140) | 7) + +#define PINMUX_GPIO141__FUNC_GPIO141 (MTK_PIN_NO(141) | 0) +#define PINMUX_GPIO141__FUNC_SCL2 (MTK_PIN_NO(141) | 1) +#define PINMUX_GPIO141__FUNC_DBG_MON_A18 (MTK_PIN_NO(141) | 7) + +#define PINMUX_GPIO142__FUNC_GPIO142 (MTK_PIN_NO(142) | 0) +#define PINMUX_GPIO142__FUNC_SDA2 (MTK_PIN_NO(142) | 1) +#define PINMUX_GPIO142__FUNC_DBG_MON_A19 (MTK_PIN_NO(142) | 7) + +#define PINMUX_GPIO143__FUNC_GPIO143 (MTK_PIN_NO(143) | 0) +#define PINMUX_GPIO143__FUNC_CMVREF0 (MTK_PIN_NO(143) | 1) +#define PINMUX_GPIO143__FUNC_SPI3_CLK (MTK_PIN_NO(143) | 2) +#define PINMUX_GPIO143__FUNC_ADSP_JTAG1_TDO (MTK_PIN_NO(143) | 3) +#define PINMUX_GPIO143__FUNC_SCP_JTAG1_TDO (MTK_PIN_NO(143) | 4) +#define PINMUX_GPIO143__FUNC_DBG_MON_A31 (MTK_PIN_NO(143) | 7) + +#define PINMUX_GPIO144__FUNC_GPIO144 (MTK_PIN_NO(144) | 0) +#define PINMUX_GPIO144__FUNC_CMVREF1 (MTK_PIN_NO(144) | 1) +#define PINMUX_GPIO144__FUNC_SPI3_CSB (MTK_PIN_NO(144) | 2) +#define PINMUX_GPIO144__FUNC_ADSP_JTAG1_TDI (MTK_PIN_NO(144) | 3) +#define PINMUX_GPIO144__FUNC_SCP_JTAG1_TDI (MTK_PIN_NO(144) | 4) + +#define PINMUX_GPIO145__FUNC_GPIO145 (MTK_PIN_NO(145) | 0) +#define PINMUX_GPIO145__FUNC_CMVREF2 (MTK_PIN_NO(145) | 1) +#define PINMUX_GPIO145__FUNC_SPI3_MI (MTK_PIN_NO(145) | 2) +#define PINMUX_GPIO145__FUNC_ADSP_JTAG1_TMS (MTK_PIN_NO(145) | 3) +#define PINMUX_GPIO145__FUNC_SCP_JTAG1_TMS (MTK_PIN_NO(145) | 4) + +#define PINMUX_GPIO146__FUNC_GPIO146 (MTK_PIN_NO(146) | 0) +#define PINMUX_GPIO146__FUNC_CMVREF3 (MTK_PIN_NO(146) | 1) +#define PINMUX_GPIO146__FUNC_SPI3_MO (MTK_PIN_NO(146) | 2) +#define PINMUX_GPIO146__FUNC_ADSP_JTAG1_TCK (MTK_PIN_NO(146) | 3) +#define PINMUX_GPIO146__FUNC_SCP_JTAG1_TCK (MTK_PIN_NO(146) | 4) +#define PINMUX_GPIO146__FUNC_DBG_MON_A32 (MTK_PIN_NO(146) | 7) + +#define PINMUX_GPIO147__FUNC_GPIO147 (MTK_PIN_NO(147) | 0) +#define PINMUX_GPIO147__FUNC_CMVREF4 (MTK_PIN_NO(147) | 1) +#define PINMUX_GPIO147__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(147) | 2) +#define PINMUX_GPIO147__FUNC_ADSP_JTAG1_TRSTN (MTK_PIN_NO(147) | 3) +#define PINMUX_GPIO147__FUNC_SCP_JTAG1_TRSTN (MTK_PIN_NO(147) | 4) + +#define PINMUX_GPIO148__FUNC_GPIO148 (MTK_PIN_NO(148) | 0) +#define PINMUX_GPIO148__FUNC_PWM_1 (MTK_PIN_NO(148) | 1) +#define PINMUX_GPIO148__FUNC_AGPS_SYNC (MTK_PIN_NO(148) | 2) +#define PINMUX_GPIO148__FUNC_CMMCLK5 (MTK_PIN_NO(148) | 3) + +#define PINMUX_GPIO149__FUNC_GPIO149 (MTK_PIN_NO(149) | 0) +#define PINMUX_GPIO149__FUNC_CMMCLK0 (MTK_PIN_NO(149) | 1) +#define PINMUX_GPIO149__FUNC_CLKM0 (MTK_PIN_NO(149) | 2) +#define PINMUX_GPIO149__FUNC_MD32_0_GPIO0 (MTK_PIN_NO(149) | 3) + +#define PINMUX_GPIO150__FUNC_GPIO150 (MTK_PIN_NO(150) | 0) +#define PINMUX_GPIO150__FUNC_CMMCLK1 (MTK_PIN_NO(150) | 1) +#define PINMUX_GPIO150__FUNC_CLKM1 (MTK_PIN_NO(150) | 2) +#define PINMUX_GPIO150__FUNC_MD32_0_GPIO1 (MTK_PIN_NO(150) | 3) +#define PINMUX_GPIO150__FUNC_CONN_MCU_AICE_TMSC (MTK_PIN_NO(150) | 7) + +#define PINMUX_GPIO151__FUNC_GPIO151 (MTK_PIN_NO(151) | 0) +#define PINMUX_GPIO151__FUNC_CMMCLK2 (MTK_PIN_NO(151) | 1) +#define PINMUX_GPIO151__FUNC_CLKM2 (MTK_PIN_NO(151) | 2) +#define PINMUX_GPIO151__FUNC_MD32_0_GPIO2 (MTK_PIN_NO(151) | 3) +#define PINMUX_GPIO151__FUNC_CONN_MCU_AICE_TCKC (MTK_PIN_NO(151) | 7) + +#define PINMUX_GPIO152__FUNC_GPIO152 (MTK_PIN_NO(152) | 0) +#define PINMUX_GPIO152__FUNC_KPROW1 (MTK_PIN_NO(152) | 1) +#define PINMUX_GPIO152__FUNC_PWM_2 (MTK_PIN_NO(152) | 2) +#define PINMUX_GPIO152__FUNC_IDDIG (MTK_PIN_NO(152) | 3) +#define PINMUX_GPIO152__FUNC_MBISTREADEN_TRIGGER (MTK_PIN_NO(152) | 6) +#define PINMUX_GPIO152__FUNC_DBG_MON_B9 (MTK_PIN_NO(152) | 7) + +#define PINMUX_GPIO153__FUNC_GPIO153 (MTK_PIN_NO(153) | 0) +#define PINMUX_GPIO153__FUNC_KPROW0 (MTK_PIN_NO(153) | 1) +#define PINMUX_GPIO153__FUNC_DBG_MON_B8 (MTK_PIN_NO(153) | 7) + +#define PINMUX_GPIO154__FUNC_GPIO154 (MTK_PIN_NO(154) | 0) +#define PINMUX_GPIO154__FUNC_KPCOL0 (MTK_PIN_NO(154) | 1) +#define PINMUX_GPIO154__FUNC_DBG_MON_B6 (MTK_PIN_NO(154) | 7) + +#define PINMUX_GPIO155__FUNC_GPIO155 (MTK_PIN_NO(155) | 0) +#define PINMUX_GPIO155__FUNC_KPCOL1 (MTK_PIN_NO(155) | 1) +#define PINMUX_GPIO155__FUNC_PWM_3 (MTK_PIN_NO(155) | 2) +#define PINMUX_GPIO155__FUNC_USB_DRVVBUS (MTK_PIN_NO(155) | 3) +#define PINMUX_GPIO155__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(155) | 4) +#define PINMUX_GPIO155__FUNC_MBISTWRITEEN_TRIGGER (MTK_PIN_NO(155) | 6) +#define PINMUX_GPIO155__FUNC_DBG_MON_B7 (MTK_PIN_NO(155) | 7) + +#define PINMUX_GPIO156__FUNC_GPIO156 (MTK_PIN_NO(156) | 0) +#define PINMUX_GPIO156__FUNC_SPI1_A_CLK (MTK_PIN_NO(156) | 1) +#define PINMUX_GPIO156__FUNC_SCP_SPI1_A_CK (MTK_PIN_NO(156) | 2) +#define PINMUX_GPIO156__FUNC_MRG_CLK (MTK_PIN_NO(156) | 3) +#define PINMUX_GPIO156__FUNC_AGPS_SYNC (MTK_PIN_NO(156) | 4) +#define PINMUX_GPIO156__FUNC_MD_URXD0 (MTK_PIN_NO(156) | 5) +#define PINMUX_GPIO156__FUNC_UDI_TMS (MTK_PIN_NO(156) | 6) +#define PINMUX_GPIO156__FUNC_DBG_MON_B10 (MTK_PIN_NO(156) | 7) + +#define PINMUX_GPIO157__FUNC_GPIO157 (MTK_PIN_NO(157) | 0) +#define PINMUX_GPIO157__FUNC_SPI1_A_CSB (MTK_PIN_NO(157) | 1) +#define PINMUX_GPIO157__FUNC_SCP_SPI1_A_CS (MTK_PIN_NO(157) | 2) +#define PINMUX_GPIO157__FUNC_MRG_SYNC (MTK_PIN_NO(157) | 3) +#define PINMUX_GPIO157__FUNC_EXT_FRAME_SYNC (MTK_PIN_NO(157) | 4) +#define PINMUX_GPIO157__FUNC_MD_UTXD0 (MTK_PIN_NO(157) | 5) +#define PINMUX_GPIO157__FUNC_UDI_TCK (MTK_PIN_NO(157) | 6) +#define PINMUX_GPIO157__FUNC_DBG_MON_B11 (MTK_PIN_NO(157) | 7) + +#define PINMUX_GPIO158__FUNC_GPIO158 (MTK_PIN_NO(158) | 0) +#define PINMUX_GPIO158__FUNC_SPI1_A_MI (MTK_PIN_NO(158) | 1) +#define PINMUX_GPIO158__FUNC_SCP_SPI1_A_MI (MTK_PIN_NO(158) | 2) +#define PINMUX_GPIO158__FUNC_MRG_DI (MTK_PIN_NO(158) | 3) +#define PINMUX_GPIO158__FUNC_PTA_RXD (MTK_PIN_NO(158) | 4) +#define PINMUX_GPIO158__FUNC_MD_URXD1 (MTK_PIN_NO(158) | 5) +#define PINMUX_GPIO158__FUNC_UDI_TDO (MTK_PIN_NO(158) | 6) +#define PINMUX_GPIO158__FUNC_DBG_MON_B12 (MTK_PIN_NO(158) | 7) + +#define PINMUX_GPIO159__FUNC_GPIO159 (MTK_PIN_NO(159) | 0) +#define PINMUX_GPIO159__FUNC_SPI1_A_MO (MTK_PIN_NO(159) | 1) +#define PINMUX_GPIO159__FUNC_SCP_SPI1_A_MO (MTK_PIN_NO(159) | 2) +#define PINMUX_GPIO159__FUNC_MRG_DO (MTK_PIN_NO(159) | 3) +#define PINMUX_GPIO159__FUNC_PTA_TXD (MTK_PIN_NO(159) | 4) +#define PINMUX_GPIO159__FUNC_MD_UTXD1 (MTK_PIN_NO(159) | 5) +#define PINMUX_GPIO159__FUNC_UDI_NTRST (MTK_PIN_NO(159) | 6) +#define PINMUX_GPIO159__FUNC_DBG_MON_B13 (MTK_PIN_NO(159) | 7) + +#define PINMUX_GPIO160__FUNC_GPIO160 (MTK_PIN_NO(160) | 0) +#define PINMUX_GPIO160__FUNC_SCL3 (MTK_PIN_NO(160) | 1) +#define PINMUX_GPIO160__FUNC_SCP_SCL1 (MTK_PIN_NO(160) | 3) +#define PINMUX_GPIO160__FUNC_DBG_MON_B14 (MTK_PIN_NO(160) | 7) + +#define PINMUX_GPIO161__FUNC_GPIO161 (MTK_PIN_NO(161) | 0) +#define PINMUX_GPIO161__FUNC_SDA3 (MTK_PIN_NO(161) | 1) +#define PINMUX_GPIO161__FUNC_SCP_SDA1 (MTK_PIN_NO(161) | 3) +#define PINMUX_GPIO161__FUNC_DBG_MON_B15 (MTK_PIN_NO(161) | 7) + +#define PINMUX_GPIO162__FUNC_GPIO162 (MTK_PIN_NO(162) | 0) +#define PINMUX_GPIO162__FUNC_ANT_SEL0 (MTK_PIN_NO(162) | 1) +#define PINMUX_GPIO162__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(162) | 2) +#define PINMUX_GPIO162__FUNC_UDI_TDI (MTK_PIN_NO(162) | 6) +#define PINMUX_GPIO162__FUNC_DBG_MON_B16 (MTK_PIN_NO(162) | 7) + +#define PINMUX_GPIO163__FUNC_GPIO163 (MTK_PIN_NO(163) | 0) +#define PINMUX_GPIO163__FUNC_ANT_SEL1 (MTK_PIN_NO(163) | 1) +#define PINMUX_GPIO163__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(163) | 2) +#define PINMUX_GPIO163__FUNC_DBG_MON_B17 (MTK_PIN_NO(163) | 7) + +#define PINMUX_GPIO164__FUNC_GPIO164 (MTK_PIN_NO(164) | 0) +#define PINMUX_GPIO164__FUNC_ANT_SEL2 (MTK_PIN_NO(164) | 1) +#define PINMUX_GPIO164__FUNC_SCP_SPI1_B_CK (MTK_PIN_NO(164) | 2) +#define PINMUX_GPIO164__FUNC_TP_URXD1_AO (MTK_PIN_NO(164) | 3) +#define PINMUX_GPIO164__FUNC_UCTS0 (MTK_PIN_NO(164) | 5) +#define PINMUX_GPIO164__FUNC_DBG_MON_B18 (MTK_PIN_NO(164) | 7) + +#define PINMUX_GPIO165__FUNC_GPIO165 (MTK_PIN_NO(165) | 0) +#define PINMUX_GPIO165__FUNC_ANT_SEL3 (MTK_PIN_NO(165) | 1) +#define PINMUX_GPIO165__FUNC_SCP_SPI1_B_CS (MTK_PIN_NO(165) | 2) +#define PINMUX_GPIO165__FUNC_TP_UTXD1_AO (MTK_PIN_NO(165) | 3) +#define PINMUX_GPIO165__FUNC_CONN_TCXOENA_REQ (MTK_PIN_NO(165) | 4) +#define PINMUX_GPIO165__FUNC_URTS0 (MTK_PIN_NO(165) | 5) +#define PINMUX_GPIO165__FUNC_DBG_MON_B19 (MTK_PIN_NO(165) | 7) + +#define PINMUX_GPIO166__FUNC_GPIO166 (MTK_PIN_NO(166) | 0) +#define PINMUX_GPIO166__FUNC_ANT_SEL4 (MTK_PIN_NO(166) | 1) +#define PINMUX_GPIO166__FUNC_SCP_SPI1_B_MI (MTK_PIN_NO(166) | 2) +#define PINMUX_GPIO166__FUNC_TP_URXD2_AO (MTK_PIN_NO(166) | 3) +#define PINMUX_GPIO166__FUNC_SRCLKENAI1 (MTK_PIN_NO(166) | 4) +#define PINMUX_GPIO166__FUNC_UCTS1 (MTK_PIN_NO(166) | 5) +#define PINMUX_GPIO166__FUNC_DBG_MON_B20 (MTK_PIN_NO(166) | 7) + +#define PINMUX_GPIO167__FUNC_GPIO167 (MTK_PIN_NO(167) | 0) +#define PINMUX_GPIO167__FUNC_ANT_SEL5 (MTK_PIN_NO(167) | 1) +#define PINMUX_GPIO167__FUNC_SCP_SPI1_B_MO (MTK_PIN_NO(167) | 2) +#define PINMUX_GPIO167__FUNC_TP_UTXD2_AO (MTK_PIN_NO(167) | 3) +#define PINMUX_GPIO167__FUNC_SRCLKENAI0 (MTK_PIN_NO(167) | 4) +#define PINMUX_GPIO167__FUNC_URTS1 (MTK_PIN_NO(167) | 5) +#define PINMUX_GPIO167__FUNC_DBG_MON_B21 (MTK_PIN_NO(167) | 7) + +#define PINMUX_GPIO168__FUNC_GPIO168 (MTK_PIN_NO(168) | 0) +#define PINMUX_GPIO168__FUNC_ANT_SEL6 (MTK_PIN_NO(168) | 1) +#define PINMUX_GPIO168__FUNC_SPI0_B_CLK (MTK_PIN_NO(168) | 2) +#define PINMUX_GPIO168__FUNC_TP_UCTS1_AO (MTK_PIN_NO(168) | 3) +#define PINMUX_GPIO168__FUNC_KPCOL2 (MTK_PIN_NO(168) | 4) +#define PINMUX_GPIO168__FUNC_MD_UCTS0 (MTK_PIN_NO(168) | 5) +#define PINMUX_GPIO168__FUNC_SCL11 (MTK_PIN_NO(168) | 6) +#define PINMUX_GPIO168__FUNC_DBG_MON_B22 (MTK_PIN_NO(168) | 7) + +#define PINMUX_GPIO169__FUNC_GPIO169 (MTK_PIN_NO(169) | 0) +#define PINMUX_GPIO169__FUNC_ANT_SEL7 (MTK_PIN_NO(169) | 1) +#define PINMUX_GPIO169__FUNC_SPI0_B_CSB (MTK_PIN_NO(169) | 2) +#define PINMUX_GPIO169__FUNC_TP_URTS1_AO (MTK_PIN_NO(169) | 3) +#define PINMUX_GPIO169__FUNC_KPROW2 (MTK_PIN_NO(169) | 4) +#define PINMUX_GPIO169__FUNC_MD_URTS0 (MTK_PIN_NO(169) | 5) +#define PINMUX_GPIO169__FUNC_SDA11 (MTK_PIN_NO(169) | 6) +#define PINMUX_GPIO169__FUNC_DBG_MON_B23 (MTK_PIN_NO(169) | 7) + +#define PINMUX_GPIO170__FUNC_GPIO170 (MTK_PIN_NO(170) | 0) +#define PINMUX_GPIO170__FUNC_ANT_SEL8 (MTK_PIN_NO(170) | 1) +#define PINMUX_GPIO170__FUNC_SPI0_B_MI (MTK_PIN_NO(170) | 2) +#define PINMUX_GPIO170__FUNC_TP_UCTS2_AO (MTK_PIN_NO(170) | 3) +#define PINMUX_GPIO170__FUNC_SRCLKENAI1 (MTK_PIN_NO(170) | 4) +#define PINMUX_GPIO170__FUNC_MD_UCTS1 (MTK_PIN_NO(170) | 5) +#define PINMUX_GPIO170__FUNC_DBG_MON_B24 (MTK_PIN_NO(170) | 7) + +#define PINMUX_GPIO171__FUNC_GPIO171 (MTK_PIN_NO(171) | 0) +#define PINMUX_GPIO171__FUNC_ANT_SEL9 (MTK_PIN_NO(171) | 1) +#define PINMUX_GPIO171__FUNC_SPI0_B_MO (MTK_PIN_NO(171) | 2) +#define PINMUX_GPIO171__FUNC_TP_URTS2_AO (MTK_PIN_NO(171) | 3) +#define PINMUX_GPIO171__FUNC_SRCLKENAI0 (MTK_PIN_NO(171) | 4) +#define PINMUX_GPIO171__FUNC_MD_URTS1 (MTK_PIN_NO(171) | 5) +#define PINMUX_GPIO171__FUNC_DBG_MON_B25 (MTK_PIN_NO(171) | 7) + +#define PINMUX_GPIO172__FUNC_GPIO172 (MTK_PIN_NO(172) | 0) +#define PINMUX_GPIO172__FUNC_CONN_TOP_CLK (MTK_PIN_NO(172) | 1) +#define PINMUX_GPIO172__FUNC_AUXIF_CLK0 (MTK_PIN_NO(172) | 2) +#define PINMUX_GPIO172__FUNC_DBG_MON_B29 (MTK_PIN_NO(172) | 7) + +#define PINMUX_GPIO173__FUNC_GPIO173 (MTK_PIN_NO(173) | 0) +#define PINMUX_GPIO173__FUNC_CONN_TOP_DATA (MTK_PIN_NO(173) | 1) +#define PINMUX_GPIO173__FUNC_AUXIF_ST0 (MTK_PIN_NO(173) | 2) +#define PINMUX_GPIO173__FUNC_DBG_MON_B30 (MTK_PIN_NO(173) | 7) + +#define PINMUX_GPIO174__FUNC_GPIO174 (MTK_PIN_NO(174) | 0) +#define PINMUX_GPIO174__FUNC_CONN_HRST_B (MTK_PIN_NO(174) | 1) +#define PINMUX_GPIO174__FUNC_DBG_MON_B28 (MTK_PIN_NO(174) | 7) + +#define PINMUX_GPIO175__FUNC_GPIO175 (MTK_PIN_NO(175) | 0) +#define PINMUX_GPIO175__FUNC_CONN_WB_PTA (MTK_PIN_NO(175) | 1) +#define PINMUX_GPIO175__FUNC_DBG_MON_B31 (MTK_PIN_NO(175) | 7) + +#define PINMUX_GPIO176__FUNC_GPIO176 (MTK_PIN_NO(176) | 0) +#define PINMUX_GPIO176__FUNC_CONN_BT_CLK (MTK_PIN_NO(176) | 1) +#define PINMUX_GPIO176__FUNC_AUXIF_CLK1 (MTK_PIN_NO(176) | 2) +#define PINMUX_GPIO176__FUNC_DBG_MON_B26 (MTK_PIN_NO(176) | 7) + +#define PINMUX_GPIO177__FUNC_GPIO177 (MTK_PIN_NO(177) | 0) +#define PINMUX_GPIO177__FUNC_CONN_BT_DATA (MTK_PIN_NO(177) | 1) +#define PINMUX_GPIO177__FUNC_AUXIF_ST1 (MTK_PIN_NO(177) | 2) +#define PINMUX_GPIO177__FUNC_DBG_MON_B27 (MTK_PIN_NO(177) | 7) + +#define PINMUX_GPIO178__FUNC_GPIO178 (MTK_PIN_NO(178) | 0) +#define PINMUX_GPIO178__FUNC_CONN_WF_CTRL0 (MTK_PIN_NO(178) | 1) + +#define PINMUX_GPIO179__FUNC_GPIO179 (MTK_PIN_NO(179) | 0) +#define PINMUX_GPIO179__FUNC_CONN_WF_CTRL1 (MTK_PIN_NO(179) | 1) +#define PINMUX_GPIO179__FUNC_UFS_MPHY_SCL (MTK_PIN_NO(179) | 2) + +#define PINMUX_GPIO180__FUNC_GPIO180 (MTK_PIN_NO(180) | 0) +#define PINMUX_GPIO180__FUNC_CONN_WF_CTRL2 (MTK_PIN_NO(180) | 1) +#define PINMUX_GPIO180__FUNC_UFS_MPHY_SDA (MTK_PIN_NO(180) | 2) + +#define PINMUX_GPIO181__FUNC_GPIO181 (MTK_PIN_NO(181) | 0) +#define PINMUX_GPIO181__FUNC_CONN_WF_CTRL3 (MTK_PIN_NO(181) | 1) + +#define PINMUX_GPIO182__FUNC_GPIO182 (MTK_PIN_NO(182) | 0) +#define PINMUX_GPIO182__FUNC_CONN_WF_CTRL4 (MTK_PIN_NO(182) | 1) + +#define PINMUX_GPIO183__FUNC_GPIO183 (MTK_PIN_NO(183) | 0) +#define PINMUX_GPIO183__FUNC_MSDC0_CMD (MTK_PIN_NO(183) | 1) + +#define PINMUX_GPIO184__FUNC_GPIO184 (MTK_PIN_NO(184) | 0) +#define PINMUX_GPIO184__FUNC_MSDC0_DAT0 (MTK_PIN_NO(184) | 1) + +#define PINMUX_GPIO185__FUNC_GPIO185 (MTK_PIN_NO(185) | 0) +#define PINMUX_GPIO185__FUNC_MSDC0_DAT2 (MTK_PIN_NO(185) | 1) + +#define PINMUX_GPIO186__FUNC_GPIO186 (MTK_PIN_NO(186) | 0) +#define PINMUX_GPIO186__FUNC_MSDC0_DAT4 (MTK_PIN_NO(186) | 1) + +#define PINMUX_GPIO187__FUNC_GPIO187 (MTK_PIN_NO(187) | 0) +#define PINMUX_GPIO187__FUNC_MSDC0_DAT6 (MTK_PIN_NO(187) | 1) + +#define PINMUX_GPIO188__FUNC_GPIO188 (MTK_PIN_NO(188) | 0) +#define PINMUX_GPIO188__FUNC_MSDC0_DAT1 (MTK_PIN_NO(188) | 1) + +#define PINMUX_GPIO189__FUNC_GPIO189 (MTK_PIN_NO(189) | 0) +#define PINMUX_GPIO189__FUNC_MSDC0_DAT5 (MTK_PIN_NO(189) | 1) + +#define PINMUX_GPIO190__FUNC_GPIO190 (MTK_PIN_NO(190) | 0) +#define PINMUX_GPIO190__FUNC_MSDC0_DAT7 (MTK_PIN_NO(190) | 1) + +#define PINMUX_GPIO191__FUNC_GPIO191 (MTK_PIN_NO(191) | 0) +#define PINMUX_GPIO191__FUNC_MSDC0_DSL (MTK_PIN_NO(191) | 1) +#define PINMUX_GPIO191__FUNC_GPS_L1_ELNA_EN (MTK_PIN_NO(191) | 2) +#define PINMUX_GPIO191__FUNC_IDDIG (MTK_PIN_NO(191) | 3) +#define PINMUX_GPIO191__FUNC_DMIC_CLK (MTK_PIN_NO(191) | 4) + +#define PINMUX_GPIO192__FUNC_GPIO192 (MTK_PIN_NO(192) | 0) +#define PINMUX_GPIO192__FUNC_MSDC0_CLK (MTK_PIN_NO(192) | 1) +#define PINMUX_GPIO192__FUNC_USB_DRVVBUS (MTK_PIN_NO(192) | 3) +#define PINMUX_GPIO192__FUNC_DMIC_DAT (MTK_PIN_NO(192) | 4) + +#define PINMUX_GPIO193__FUNC_GPIO193 (MTK_PIN_NO(193) | 0) +#define PINMUX_GPIO193__FUNC_MSDC0_DAT3 (MTK_PIN_NO(193) | 1) + +#define PINMUX_GPIO194__FUNC_GPIO194 (MTK_PIN_NO(194) | 0) +#define PINMUX_GPIO194__FUNC_MSDC0_RSTB (MTK_PIN_NO(194) | 1) + +#define PINMUX_GPIO195__FUNC_GPIO195 (MTK_PIN_NO(195) | 0) +#define PINMUX_GPIO195__FUNC_SCP_VREQ_VAO (MTK_PIN_NO(195) | 1) +#define PINMUX_GPIO195__FUNC_DVFSRC_EXT_REQ (MTK_PIN_NO(195) | 2) + +#define PINMUX_GPIO196__FUNC_GPIO196 (MTK_PIN_NO(196) | 0) +#define PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2 (MTK_PIN_NO(196) | 1) + +#define PINMUX_GPIO197__FUNC_GPIO197 (MTK_PIN_NO(197) | 0) +#define PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1 (MTK_PIN_NO(197) | 1) +#define PINMUX_GPIO197__FUNC_AUD_CLK_MISO (MTK_PIN_NO(197) | 2) +#define PINMUX_GPIO197__FUNC_I2S2_MCK (MTK_PIN_NO(197) | 3) +#define PINMUX_GPIO197__FUNC_I2S6_MCK (MTK_PIN_NO(197) | 4) +#define PINMUX_GPIO197__FUNC_I2S8_MCK (MTK_PIN_NO(197) | 5) + +#define PINMUX_GPIO198__FUNC_GPIO198 (MTK_PIN_NO(198) | 0) +#define PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0 (MTK_PIN_NO(198) | 1) +#define PINMUX_GPIO198__FUNC_AUD_SYNC_MISO (MTK_PIN_NO(198) | 2) +#define PINMUX_GPIO198__FUNC_I2S2_BCK (MTK_PIN_NO(198) | 3) +#define PINMUX_GPIO198__FUNC_I2S6_BCK (MTK_PIN_NO(198) | 4) +#define PINMUX_GPIO198__FUNC_I2S8_BCK (MTK_PIN_NO(198) | 5) + +#define PINMUX_GPIO199__FUNC_GPIO199 (MTK_PIN_NO(199) | 0) +#define PINMUX_GPIO199__FUNC_AUD_DAT_MISO2 (MTK_PIN_NO(199) | 1) +#define PINMUX_GPIO199__FUNC_I2S2_DI2 (MTK_PIN_NO(199) | 3) + +#define PINMUX_GPIO200__FUNC_GPIO200 (MTK_PIN_NO(200) | 0) +#define PINMUX_GPIO200__FUNC_SCL6 (MTK_PIN_NO(200) | 1) +#define PINMUX_GPIO200__FUNC_SCP_SCL1 (MTK_PIN_NO(200) | 3) +#define PINMUX_GPIO200__FUNC_SCL_6306 (MTK_PIN_NO(200) | 4) +#define PINMUX_GPIO200__FUNC_DBG_MON_A4 (MTK_PIN_NO(200) | 7) + +#define PINMUX_GPIO201__FUNC_GPIO201 (MTK_PIN_NO(201) | 0) +#define PINMUX_GPIO201__FUNC_SDA6 (MTK_PIN_NO(201) | 1) +#define PINMUX_GPIO201__FUNC_SCP_SDA1 (MTK_PIN_NO(201) | 3) +#define PINMUX_GPIO201__FUNC_SDA_6306 (MTK_PIN_NO(201) | 4) +#define PINMUX_GPIO201__FUNC_DBG_MON_A5 (MTK_PIN_NO(201) | 7) + +#define PINMUX_GPIO202__FUNC_GPIO202 (MTK_PIN_NO(202) | 0) +#define PINMUX_GPIO202__FUNC_SCL5 (MTK_PIN_NO(202) | 1) + +#define PINMUX_GPIO203__FUNC_GPIO203 (MTK_PIN_NO(203) | 0) +#define PINMUX_GPIO203__FUNC_SDA5 (MTK_PIN_NO(203) | 1) + +#define PINMUX_GPIO204__FUNC_GPIO204 (MTK_PIN_NO(204) | 0) +#define PINMUX_GPIO204__FUNC_SCL0 (MTK_PIN_NO(204) | 1) +#define PINMUX_GPIO204__FUNC_SPI7_A_CLK (MTK_PIN_NO(204) | 6) +#define PINMUX_GPIO204__FUNC_DBG_MON_A2 (MTK_PIN_NO(204) | 7) + +#define PINMUX_GPIO205__FUNC_GPIO205 (MTK_PIN_NO(205) | 0) +#define PINMUX_GPIO205__FUNC_SDA0 (MTK_PIN_NO(205) | 1) +#define PINMUX_GPIO205__FUNC_SPI7_A_CSB (MTK_PIN_NO(205) | 6) +#define PINMUX_GPIO205__FUNC_DBG_MON_A3 (MTK_PIN_NO(205) | 7) + +#define PINMUX_GPIO206__FUNC_GPIO206 (MTK_PIN_NO(206) | 0) +#define PINMUX_GPIO206__FUNC_SRCLKENA0 (MTK_PIN_NO(206) | 1) + +#define PINMUX_GPIO207__FUNC_GPIO207 (MTK_PIN_NO(207) | 0) +#define PINMUX_GPIO207__FUNC_SRCLKENA1 (MTK_PIN_NO(207) | 1) + +#define PINMUX_GPIO208__FUNC_GPIO208 (MTK_PIN_NO(208) | 0) +#define PINMUX_GPIO208__FUNC_WATCHDOG (MTK_PIN_NO(208) | 1) + +#define PINMUX_GPIO209__FUNC_GPIO209 (MTK_PIN_NO(209) | 0) +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(209) | 1) +#define PINMUX_GPIO209__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(209) | 2) + +#define PINMUX_GPIO210__FUNC_GPIO210 (MTK_PIN_NO(210) | 0) +#define PINMUX_GPIO210__FUNC_PWRAP_SPI0_CSN (MTK_PIN_NO(210) | 1) + +#define PINMUX_GPIO211__FUNC_GPIO211 (MTK_PIN_NO(211) | 0) +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MO (MTK_PIN_NO(211) | 1) +#define PINMUX_GPIO211__FUNC_PWRAP_SPI0_MI (MTK_PIN_NO(211) | 2) + +#define PINMUX_GPIO212__FUNC_GPIO212 (MTK_PIN_NO(212) | 0) +#define PINMUX_GPIO212__FUNC_PWRAP_SPI0_CK (MTK_PIN_NO(212) | 1) + +#define PINMUX_GPIO213__FUNC_GPIO213 (MTK_PIN_NO(213) | 0) +#define PINMUX_GPIO213__FUNC_RTC32K_CK (MTK_PIN_NO(213) | 1) + +#define PINMUX_GPIO214__FUNC_GPIO214 (MTK_PIN_NO(214) | 0) +#define PINMUX_GPIO214__FUNC_AUD_CLK_MOSI (MTK_PIN_NO(214) | 1) +#define PINMUX_GPIO214__FUNC_I2S1_MCK (MTK_PIN_NO(214) | 3) +#define PINMUX_GPIO214__FUNC_I2S7_MCK (MTK_PIN_NO(214) | 4) +#define PINMUX_GPIO214__FUNC_I2S9_MCK (MTK_PIN_NO(214) | 5) + +#define PINMUX_GPIO215__FUNC_GPIO215 (MTK_PIN_NO(215) | 0) +#define PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI (MTK_PIN_NO(215) | 1) +#define PINMUX_GPIO215__FUNC_I2S1_BCK (MTK_PIN_NO(215) | 3) +#define PINMUX_GPIO215__FUNC_I2S7_BCK (MTK_PIN_NO(215) | 4) +#define PINMUX_GPIO215__FUNC_I2S9_BCK (MTK_PIN_NO(215) | 5) + +#define PINMUX_GPIO216__FUNC_GPIO216 (MTK_PIN_NO(216) | 0) +#define PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0 (MTK_PIN_NO(216) | 1) +#define PINMUX_GPIO216__FUNC_I2S1_LRCK (MTK_PIN_NO(216) | 3) +#define PINMUX_GPIO216__FUNC_I2S7_LRCK (MTK_PIN_NO(216) | 4) +#define PINMUX_GPIO216__FUNC_I2S9_LRCK (MTK_PIN_NO(216) | 5) + +#define PINMUX_GPIO217__FUNC_GPIO217 (MTK_PIN_NO(217) | 0) +#define PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1 (MTK_PIN_NO(217) | 1) +#define PINMUX_GPIO217__FUNC_I2S1_DO (MTK_PIN_NO(217) | 3) +#define PINMUX_GPIO217__FUNC_I2S7_DO (MTK_PIN_NO(217) | 4) +#define PINMUX_GPIO217__FUNC_I2S9_DO (MTK_PIN_NO(217) | 5) + +#define PINMUX_GPIO218__FUNC_GPIO218 (MTK_PIN_NO(218) | 0) +#define PINMUX_GPIO218__FUNC_AUD_DAT_MISO0 (MTK_PIN_NO(218) | 1) +#define PINMUX_GPIO218__FUNC_VOW_DAT_MISO (MTK_PIN_NO(218) | 2) +#define PINMUX_GPIO218__FUNC_I2S2_LRCK (MTK_PIN_NO(218) | 3) +#define PINMUX_GPIO218__FUNC_I2S6_LRCK (MTK_PIN_NO(218) | 4) +#define PINMUX_GPIO218__FUNC_I2S8_LRCK (MTK_PIN_NO(218) | 5) + +#define PINMUX_GPIO219__FUNC_GPIO219 (MTK_PIN_NO(219) | 0) +#define PINMUX_GPIO219__FUNC_AUD_DAT_MISO1 (MTK_PIN_NO(219) | 1) +#define PINMUX_GPIO219__FUNC_VOW_CLK_MISO (MTK_PIN_NO(219) | 2) +#define PINMUX_GPIO219__FUNC_I2S2_DI (MTK_PIN_NO(219) | 3) +#define PINMUX_GPIO219__FUNC_I2S6_DI (MTK_PIN_NO(219) | 4) +#define PINMUX_GPIO219__FUNC_I2S8_DI (MTK_PIN_NO(219) | 5) + +#endif /* __MT8192_PINFUNC_H */ From d2f2f1321c194479c32ac13843a9299568da9304 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Mon, 17 Aug 2020 08:17:01 +0800 Subject: [PATCH 18/78] dt-bindings: pinctrl: mt8192: add binding document The commit adds mt8192 compatible node in binding document. Signed-off-by: Zhiyong Tao Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200817001702.1646-3-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-mt8192.yaml | 155 ++++++++++++++++++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml new file mode 100644 index 000000000000..5556def6b99b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt8192.yaml @@ -0,0 +1,155 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-mt8192.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8192 Pin Controller + +maintainers: + - Sean Wang + +description: | + The Mediatek's Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8192-pinctrl + + gpio-controller: true + + '#gpio-cells': + description: | + Number of cells in GPIO specifier. Since the generic GPIO binding is used, + the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + const: 2 + + gpio-ranges: + description: gpio valid number range. + maxItems: 1 + + reg: + description: | + Physical address base for gpio base registers. There are 11 GPIO + physical address base in mt8192. + maxItems: 11 + + reg-names: + description: | + Gpio base register names. + maxItems: 11 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: The interrupt outputs to sysirq. + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^pins': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and + input schmitt. + An example of using macro: + pincontroller { + /* GPIO0 set as multifunction GPIO0 */ + state_0_node_a { + pinmux = ; + }; + /* GPIO1 set as multifunction PWM */ + state_0_node_b { + pinmux = ; + }; + }; + $ref: "pinmux-node.yaml" + + properties: + pinmux: + description: | + Integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in dt-bindings/pinctrl/-pinfunc.h directly. + + drive-strength: + description: | + It can support some arguments, such as MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See + dt-bindings/pinctrl/mt65xx.h. It can only support 2/4/6/8/10/12/14/16mA in mt8192. + enum: [2, 4, 6, 8, 10, 12, 14, 16] + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + input-enable: true + + input-disable: true + + input-schmitt-enable: true + + input-schmitt-disable: true + + required: + - pinmux + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + #include + pio: pinctrl@10005000 { + compatible = "mediatek,mt8192-pinctrl"; + reg = <0x10005000 0x1000>, + <0x11c20000 0x1000>, + <0x11d10000 0x1000>, + <0x11d30000 0x1000>, + <0x11d40000 0x1000>, + <0x11e20000 0x1000>, + <0x11e70000 0x1000>, + <0x11ea0000 0x1000>, + <0x11f20000 0x1000>, + <0x11f30000 0x1000>, + <0x1000b000 0x1000>; + reg-names = "iocfg0", "iocfg_rm", "iocfg_bm", + "iocfg_bl", "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", "iocfg_lt", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 220>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + + pins { + pinmux = ; + output-low; + }; + }; From d32f38f2a8fc498de8e160ab1f1acb42b64c73b9 Mon Sep 17 00:00:00 2001 From: Zhiyong Tao Date: Mon, 17 Aug 2020 08:17:02 +0800 Subject: [PATCH 19/78] pinctrl: mediatek: Add pinctrl driver for mt8192 This commit includes pinctrl driver for mt8192. Signed-off-by: Zhiyong Tao Acked-by: Sean Wang Link: https://lore.kernel.org/r/20200817001702.1646-4-zhiyong.tao@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8192.c | 1409 ++++++++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h | 2275 +++++++++++++++++ 4 files changed, 3692 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8192.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 1cedc5f2aadb..7d336370d767 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -133,6 +133,13 @@ config PINCTRL_MT8183 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_PARIS +config PINCTRL_MT8192 + bool "Mediatek MT8192 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK_PARIS + config PINCTRL_MT8516 bool "Mediatek MT8516 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index b0b07c541d11..1966a5299da4 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -19,5 +19,6 @@ obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o +obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8192.c b/drivers/pinctrl/mediatek/pinctrl-mt8192.c new file mode 100644 index 000000000000..0c16b2c756bf --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8192.c @@ -0,0 +1,1409 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Zhiyong Tao + * + */ + +#include +#include "pinctrl-mtk-mt8192.h" +#include "pinctrl-paris.h" + +/* MT8192 have multiple bases to program pin configuration listed as the below: + * iocfg0:0x10005000, iocfg_rm:0x11C20000, iocfg_bm:0x11D10000, + * iocfg_bl:0x11D30000, iocfg_br:0x11D40000, iocfg_lm:0x11E20000, + * iocfg_lb:0x11E70000, iocfg_rt:0x11EA0000, iocfg_lt:0x11F20000, + * iocfg_tl:0x11F30000 + * _i_based could be used to indicate what base the pin should be mapped into. + */ + +#define PIN_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 0) + +#define PINS_FIELD_BASE(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits) \ + PIN_FIELD_CALC(s_pin, e_pin, i_base, s_addr, x_addrs, s_bit, x_bits, \ + 32, 1) + +static const struct mtk_pin_field_calc mt8192_pin_mode_range[] = { + PIN_FIELD(0, 228, 0x300, 0x10, 0, 4), +}; + +static const struct mtk_pin_field_calc mt8192_pin_dir_range[] = { + PIN_FIELD(0, 228, 0x0, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_di_range[] = { + PIN_FIELD(0, 228, 0x200, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_do_range[] = { + PIN_FIELD(0, 228, 0x100, 0x10, 0, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_smt_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(1, 1, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(2, 2, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(3, 3, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00f0, 0x10, 8, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(6, 6, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(7, 7, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(8, 8, 4, 0x00f0, 0x10, 9, 1), + PIN_FIELD_BASE(9, 9, 4, 0x00f0, 0x10, 5, 1), + PIN_FIELD_BASE(10, 10, 6, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0100, 0x10, 5, 1), + PIN_FIELD_BASE(22, 22, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(24, 24, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(25, 25, 2, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(26, 26, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(27, 27, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(28, 28, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(29, 29, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(30, 30, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(31, 31, 3, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(32, 32, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(33, 33, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(34, 34, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(35, 35, 3, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(36, 36, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(37, 37, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(38, 38, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(39, 39, 2, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0100, 0x10, 4, 1), + PIN_FIELD_BASE(45, 45, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(46, 46, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(47, 47, 1, 0x00c0, 0x10, 12, 1), + PIN_FIELD_BASE(48, 48, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(49, 49, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(50, 50, 1, 0x00c0, 0x10, 13, 1), + PIN_FIELD_BASE(51, 51, 1, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(52, 52, 1, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(53, 53, 1, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(54, 54, 1, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(55, 55, 1, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(56, 56, 1, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(57, 57, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(58, 58, 3, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(59, 59, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(60, 60, 3, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(61, 61, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(62, 62, 3, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(63, 63, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(65, 65, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(66, 66, 3, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(67, 67, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(68, 68, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(69, 69, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(70, 70, 3, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(71, 71, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(72, 72, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(73, 73, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(75, 75, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(76, 76, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(77, 77, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(78, 78, 3, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(79, 79, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(80, 80, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(81, 81, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(82, 82, 3, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(83, 83, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(84, 84, 3, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(85, 85, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(86, 86, 3, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(87, 87, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(88, 88, 3, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(89, 89, 2, 0x00c0, 0x10, 9, 1), + PIN_FIELD_BASE(90, 90, 2, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(91, 91, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(92, 92, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(93, 93, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x00c0, 0x10, 4, 1), + PIN_FIELD_BASE(95, 95, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(97, 97, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00c0, 0x10, 5, 1), + PIN_FIELD_BASE(99, 99, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(100, 100, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(101, 101, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(102, 102, 2, 0x00c0, 0x10, 6, 1), + PIN_FIELD_BASE(103, 103, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(104, 104, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(105, 105, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(106, 106, 2, 0x00c0, 0x10, 7, 1), + PIN_FIELD_BASE(107, 107, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(108, 108, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(109, 109, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(110, 110, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(111, 111, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(112, 112, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(113, 113, 2, 0x00c0, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(115, 115, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(116, 116, 2, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(117, 117, 2, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00f0, 0x10, 12, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00f0, 0x10, 18, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00f0, 0x10, 17, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00f0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00f0, 0x10, 16, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00f0, 0x10, 22, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00f0, 0x10, 15, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00f0, 0x10, 21, 1), + PIN_FIELD_BASE(126, 126, 4, 0x00f0, 0x10, 6, 1), + PIN_FIELD_BASE(127, 127, 4, 0x00f0, 0x10, 7, 1), + PIN_FIELD_BASE(128, 128, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(129, 129, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00f0, 0x10, 4, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(134, 134, 4, 0x00f0, 0x10, 10, 1), + PIN_FIELD_BASE(135, 135, 4, 0x00f0, 0x10, 11, 1), + PIN_FIELD_BASE(136, 136, 4, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00f0, 0x10, 14, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00f0, 0x10, 20, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00f0, 0x10, 13, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00f0, 0x10, 19, 1), + PIN_FIELD_BASE(143, 143, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(144, 144, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(145, 145, 1, 0x00c0, 0x10, 11, 1), + PIN_FIELD_BASE(146, 146, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(147, 147, 1, 0x00c0, 0x10, 10, 1), + PIN_FIELD_BASE(148, 148, 1, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(149, 149, 1, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0100, 0x10, 6, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0100, 0x10, 7, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0100, 0x10, 12, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0100, 0x10, 13, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0100, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0100, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0100, 0x10, 2, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0100, 0x10, 3, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0100, 0x10, 8, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0100, 0x10, 9, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0100, 0x10, 10, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0100, 0x10, 11, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0080, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_ies_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(10, 10, 6, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0010, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0010, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0010, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0010, 0x10, 5, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0030, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0030, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0030, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0030, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0030, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0030, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0030, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0030, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0030, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0030, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0030, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0020, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0020, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0020, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0020, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0020, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0020, 0x10, 11, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0030, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0030, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0030, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0030, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0030, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0030, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0030, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0030, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0030, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0030, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pu_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x00b0, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x00b0, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x00b0, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x00b0, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x00b0, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x00b0, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x00b0, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x00b0, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x00b0, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x00b0, 0x10, 18, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x00a0, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x00a0, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x00a0, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x00a0, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x00a0, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x00a0, 0x10, 26, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(95, 95, 2, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00b0, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00b0, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00b0, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00b0, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00b0, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x00b0, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x00b0, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x00b0, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x00b0, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x00b0, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x00b0, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x00b0, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x00b0, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x00b0, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x00b0, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x00b0, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x00b0, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00b0, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00b0, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00b0, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00b0, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(156, 156, 7, 0x00a0, 0x10, 29, 1), + PIN_FIELD_BASE(157, 157, 7, 0x00a0, 0x10, 30, 1), + PIN_FIELD_BASE(158, 158, 7, 0x00a0, 0x10, 31, 1), + PIN_FIELD_BASE(159, 159, 7, 0x00b0, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00a0, 0x10, 27, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00a0, 0x10, 28, 1), + PIN_FIELD_BASE(162, 162, 7, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x00a0, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x00a0, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x00a0, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x00a0, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x00a0, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x00a0, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x00a0, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x00a0, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x00a0, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x00a0, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x00a0, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x00a0, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x00a0, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x00a0, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x00a0, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x00a0, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x00a0, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x00a0, 0x10, 20, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0050, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pd_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(1, 1, 4, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(2, 2, 4, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(3, 3, 4, 0x0090, 0x10, 12, 1), + PIN_FIELD_BASE(4, 4, 4, 0x0090, 0x10, 13, 1), + PIN_FIELD_BASE(5, 5, 4, 0x0090, 0x10, 14, 1), + PIN_FIELD_BASE(6, 6, 4, 0x0090, 0x10, 15, 1), + PIN_FIELD_BASE(7, 7, 4, 0x0090, 0x10, 16, 1), + PIN_FIELD_BASE(8, 8, 4, 0x0090, 0x10, 17, 1), + PIN_FIELD_BASE(9, 9, 4, 0x0090, 0x10, 18, 1), + PIN_FIELD_BASE(16, 16, 8, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(17, 17, 8, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(18, 18, 7, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(19, 19, 7, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(20, 20, 7, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(21, 21, 7, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(22, 22, 2, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(23, 23, 2, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(24, 24, 2, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(25, 25, 2, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(26, 26, 3, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(27, 27, 3, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(28, 28, 3, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(29, 29, 3, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(30, 30, 3, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(31, 31, 3, 0x0050, 0x10, 27, 1), + PIN_FIELD_BASE(32, 32, 3, 0x0050, 0x10, 24, 1), + PIN_FIELD_BASE(33, 33, 3, 0x0050, 0x10, 26, 1), + PIN_FIELD_BASE(34, 34, 3, 0x0050, 0x10, 23, 1), + PIN_FIELD_BASE(35, 35, 3, 0x0050, 0x10, 25, 1), + PIN_FIELD_BASE(36, 36, 2, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(37, 37, 2, 0x0070, 0x10, 21, 1), + PIN_FIELD_BASE(38, 38, 2, 0x0070, 0x10, 22, 1), + PIN_FIELD_BASE(39, 39, 2, 0x0070, 0x10, 23, 1), + PIN_FIELD_BASE(40, 40, 8, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(41, 41, 8, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(42, 42, 8, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(43, 43, 7, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(44, 44, 7, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(57, 57, 3, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(58, 58, 3, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(59, 59, 3, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(60, 60, 3, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(61, 61, 3, 0x0050, 0x10, 28, 1), + PIN_FIELD_BASE(62, 62, 3, 0x0050, 0x10, 22, 1), + PIN_FIELD_BASE(63, 63, 3, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(64, 64, 3, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(65, 65, 3, 0x0050, 0x10, 12, 1), + PIN_FIELD_BASE(66, 66, 3, 0x0050, 0x10, 15, 1), + PIN_FIELD_BASE(67, 67, 3, 0x0050, 0x10, 16, 1), + PIN_FIELD_BASE(68, 68, 3, 0x0050, 0x10, 17, 1), + PIN_FIELD_BASE(69, 69, 3, 0x0050, 0x10, 18, 1), + PIN_FIELD_BASE(70, 70, 3, 0x0050, 0x10, 19, 1), + PIN_FIELD_BASE(71, 71, 3, 0x0050, 0x10, 20, 1), + PIN_FIELD_BASE(72, 72, 3, 0x0050, 0x10, 21, 1), + PIN_FIELD_BASE(73, 73, 3, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(74, 74, 3, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(75, 75, 3, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(76, 76, 3, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(77, 77, 3, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(78, 78, 3, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(79, 79, 3, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(80, 80, 3, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(81, 81, 3, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(82, 82, 3, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(83, 83, 3, 0x0050, 0x10, 13, 1), + PIN_FIELD_BASE(84, 84, 3, 0x0050, 0x10, 14, 1), + PIN_FIELD_BASE(85, 85, 3, 0x0050, 0x10, 31, 1), + PIN_FIELD_BASE(86, 86, 3, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(87, 87, 3, 0x0050, 0x10, 29, 1), + PIN_FIELD_BASE(88, 88, 3, 0x0050, 0x10, 30, 1), + PIN_FIELD_BASE(89, 89, 2, 0x0070, 0x10, 24, 1), + PIN_FIELD_BASE(90, 90, 2, 0x0070, 0x10, 25, 1), + PIN_FIELD_BASE(91, 91, 2, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(92, 92, 2, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(93, 93, 2, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(94, 94, 2, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(95, 95, 2, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(96, 96, 2, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(97, 97, 2, 0x0070, 0x10, 26, 1), + PIN_FIELD_BASE(98, 98, 2, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(99, 99, 2, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(100, 100, 2, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(101, 101, 2, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(102, 102, 2, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(103, 103, 2, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(104, 104, 2, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(105, 105, 2, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(106, 106, 2, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(107, 107, 2, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(108, 108, 2, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(109, 109, 2, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(110, 110, 2, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(111, 111, 2, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(112, 112, 2, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(113, 113, 2, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(114, 114, 2, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(115, 115, 2, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(116, 116, 2, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(117, 117, 2, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(118, 118, 4, 0x0090, 0x10, 23, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0090, 0x10, 29, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0090, 0x10, 28, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00a0, 0x10, 2, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0090, 0x10, 27, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00a0, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0090, 0x10, 26, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00a0, 0x10, 0, 1), + PIN_FIELD_BASE(126, 126, 4, 0x0090, 0x10, 19, 1), + PIN_FIELD_BASE(127, 127, 4, 0x0090, 0x10, 20, 1), + PIN_FIELD_BASE(128, 128, 4, 0x0090, 0x10, 21, 1), + PIN_FIELD_BASE(129, 129, 4, 0x0090, 0x10, 22, 1), + PIN_FIELD_BASE(130, 130, 4, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(131, 131, 4, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(132, 132, 4, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(133, 133, 4, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(134, 134, 4, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(135, 135, 4, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(136, 136, 4, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(137, 137, 4, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(138, 138, 4, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0090, 0x10, 25, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0090, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0090, 0x10, 24, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0090, 0x10, 30, 1), + PIN_FIELD_BASE(143, 143, 1, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(144, 144, 1, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(145, 145, 1, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(146, 146, 1, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(147, 147, 1, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(148, 148, 1, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(149, 149, 1, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(150, 150, 1, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(151, 151, 1, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(156, 156, 7, 0x0070, 0x10, 29, 1), + PIN_FIELD_BASE(157, 157, 7, 0x0070, 0x10, 30, 1), + PIN_FIELD_BASE(158, 158, 7, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(159, 159, 7, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0070, 0x10, 27, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0070, 0x10, 28, 1), + PIN_FIELD_BASE(162, 162, 7, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(163, 163, 7, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(164, 164, 7, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(165, 165, 7, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(166, 166, 7, 0x0070, 0x10, 4, 1), + PIN_FIELD_BASE(167, 167, 7, 0x0070, 0x10, 5, 1), + PIN_FIELD_BASE(168, 168, 7, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(169, 169, 7, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(170, 170, 7, 0x0070, 0x10, 8, 1), + PIN_FIELD_BASE(171, 171, 7, 0x0070, 0x10, 9, 1), + PIN_FIELD_BASE(172, 172, 7, 0x0070, 0x10, 13, 1), + PIN_FIELD_BASE(173, 173, 7, 0x0070, 0x10, 14, 1), + PIN_FIELD_BASE(174, 174, 7, 0x0070, 0x10, 12, 1), + PIN_FIELD_BASE(175, 175, 7, 0x0070, 0x10, 15, 1), + PIN_FIELD_BASE(176, 176, 7, 0x0070, 0x10, 10, 1), + PIN_FIELD_BASE(177, 177, 7, 0x0070, 0x10, 11, 1), + PIN_FIELD_BASE(178, 178, 7, 0x0070, 0x10, 16, 1), + PIN_FIELD_BASE(179, 179, 7, 0x0070, 0x10, 17, 1), + PIN_FIELD_BASE(180, 180, 7, 0x0070, 0x10, 18, 1), + PIN_FIELD_BASE(181, 181, 7, 0x0070, 0x10, 19, 1), + PIN_FIELD_BASE(182, 182, 7, 0x0070, 0x10, 20, 1), + PIN_FIELD_BASE(195, 195, 5, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(196, 196, 5, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(197, 197, 5, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(198, 198, 5, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(199, 199, 5, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(206, 206, 5, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(207, 207, 5, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(208, 208, 5, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(209, 209, 5, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(210, 210, 5, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(211, 211, 5, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(212, 212, 5, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(213, 213, 5, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(214, 214, 5, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(215, 215, 5, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(216, 216, 5, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(217, 217, 5, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(218, 218, 5, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(219, 219, 5, 0x0040, 0x10, 2, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_drv_range[] = { + PIN_FIELD_BASE(0, 0, 4, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(1, 1, 4, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(2, 2, 4, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(3, 3, 4, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(4, 4, 4, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(5, 5, 4, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(6, 6, 4, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(7, 7, 4, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(8, 8, 4, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(9, 9, 4, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(10, 10, 6, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(11, 11, 6, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(12, 12, 6, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(13, 13, 6, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(14, 14, 6, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(15, 15, 6, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(16, 16, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(17, 17, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(18, 18, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(19, 19, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(20, 20, 7, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(21, 21, 7, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(22, 22, 2, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(23, 23, 2, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(24, 24, 2, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(25, 25, 2, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(26, 26, 3, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(27, 27, 3, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(28, 28, 3, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(29, 29, 3, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(30, 30, 3, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(31, 31, 3, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(32, 32, 3, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(33, 33, 3, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(34, 34, 3, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(35, 35, 3, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(36, 36, 2, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(37, 37, 2, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(38, 38, 2, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(39, 39, 2, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(40, 40, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(41, 41, 8, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(42, 42, 8, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(43, 43, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(44, 44, 7, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(45, 45, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(46, 46, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(47, 47, 1, 0x0010, 0x10, 6, 2), + PIN_FIELD_BASE(48, 48, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(49, 49, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(50, 50, 1, 0x0010, 0x10, 8, 2), + PIN_FIELD_BASE(51, 51, 1, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(52, 52, 1, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(53, 53, 1, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(54, 54, 1, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(55, 55, 1, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(56, 56, 1, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(57, 57, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(58, 58, 3, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(59, 59, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(60, 60, 3, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(61, 61, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(62, 62, 3, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(63, 63, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(64, 64, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(65, 65, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(66, 66, 3, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(67, 67, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(68, 68, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(69, 69, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(70, 70, 3, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(71, 71, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(72, 72, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(73, 73, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(74, 74, 3, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(75, 75, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(76, 76, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(77, 77, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(78, 78, 3, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(79, 79, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(80, 80, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(81, 81, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(82, 82, 3, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(83, 83, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(84, 84, 3, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(85, 85, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(86, 86, 3, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(87, 87, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(88, 88, 3, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(89, 89, 2, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(90, 90, 2, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(91, 91, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(92, 92, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(93, 93, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(94, 94, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(95, 95, 2, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(96, 96, 2, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(97, 97, 2, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(98, 98, 2, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(99, 99, 2, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(100, 100, 2, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(101, 101, 2, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(102, 102, 2, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(103, 103, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(104, 104, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(105, 105, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(106, 106, 2, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(107, 107, 2, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(108, 108, 2, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(109, 109, 2, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(110, 110, 2, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(111, 111, 2, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(112, 112, 2, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(113, 113, 2, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(114, 114, 2, 0x0010, 0x10, 15, 3), + PIN_FIELD_BASE(115, 115, 2, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(116, 116, 2, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(117, 117, 2, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(118, 118, 4, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(119, 119, 4, 0x0020, 0x10, 21, 3), + PIN_FIELD_BASE(120, 120, 4, 0x0020, 0x10, 18, 3), + PIN_FIELD_BASE(121, 121, 4, 0x0030, 0x10, 6, 3), + PIN_FIELD_BASE(122, 122, 4, 0x0020, 0x10, 15, 3), + PIN_FIELD_BASE(123, 123, 4, 0x0030, 0x10, 3, 3), + PIN_FIELD_BASE(124, 124, 4, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(125, 125, 4, 0x0030, 0x10, 0, 3), + PIN_FIELD_BASE(126, 126, 4, 0x0010, 0x10, 18, 3), + PIN_FIELD_BASE(127, 127, 4, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(128, 128, 4, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(129, 129, 4, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(130, 130, 4, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(131, 131, 4, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(132, 132, 4, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(133, 133, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(134, 134, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(135, 135, 4, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(136, 136, 4, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(137, 137, 4, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(138, 138, 4, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(139, 139, 4, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(140, 140, 4, 0x0020, 0x10, 27, 3), + PIN_FIELD_BASE(141, 141, 4, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(142, 142, 4, 0x0020, 0x10, 24, 3), + PIN_FIELD_BASE(143, 143, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(144, 144, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(145, 145, 1, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(146, 146, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(147, 147, 1, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(148, 148, 1, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(149, 149, 1, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(150, 150, 1, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(151, 151, 1, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(152, 152, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(153, 153, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(154, 154, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(155, 155, 7, 0x0010, 0x10, 21, 3), + PIN_FIELD_BASE(156, 156, 7, 0x0020, 0x10, 3, 3), + PIN_FIELD_BASE(157, 157, 7, 0x0020, 0x10, 6, 3), + PIN_FIELD_BASE(158, 158, 7, 0x0020, 0x10, 9, 3), + PIN_FIELD_BASE(159, 159, 7, 0x0020, 0x10, 12, 3), + PIN_FIELD_BASE(160, 160, 7, 0x0010, 0x10, 27, 3), + PIN_FIELD_BASE(161, 161, 7, 0x0020, 0x10, 0, 3), + PIN_FIELD_BASE(162, 162, 7, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(163, 163, 7, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(164, 164, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(165, 165, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(166, 166, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(167, 167, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(168, 168, 7, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(169, 169, 7, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(170, 170, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(171, 171, 7, 0x0010, 0x10, 24, 3), + PIN_FIELD_BASE(172, 172, 7, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(173, 173, 7, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(174, 174, 7, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(175, 175, 7, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(176, 176, 7, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(177, 177, 7, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(178, 178, 7, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(179, 179, 7, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(180, 180, 7, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(181, 181, 7, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(182, 182, 7, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(183, 183, 9, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(184, 184, 9, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(185, 185, 9, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(186, 186, 9, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(187, 187, 9, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(188, 188, 9, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(189, 189, 9, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(190, 190, 9, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(191, 191, 9, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(192, 192, 9, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(193, 193, 9, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(194, 194, 9, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(195, 195, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(196, 196, 5, 0x0000, 0x10, 18, 3), + PIN_FIELD_BASE(197, 197, 5, 0x0000, 0x10, 24, 3), + PIN_FIELD_BASE(198, 198, 5, 0x0000, 0x10, 21, 3), + PIN_FIELD_BASE(199, 199, 5, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(200, 200, 8, 0x0000, 0x10, 9, 3), + PIN_FIELD_BASE(201, 201, 8, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(202, 202, 5, 0x0010, 0x10, 6, 3), + PIN_FIELD_BASE(203, 203, 5, 0x0010, 0x10, 9, 3), + PIN_FIELD_BASE(204, 204, 8, 0x0000, 0x10, 6, 3), + PIN_FIELD_BASE(205, 205, 8, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(206, 206, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(207, 207, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(208, 208, 5, 0x0010, 0x10, 12, 3), + PIN_FIELD_BASE(209, 209, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(210, 210, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(211, 211, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(212, 212, 5, 0x0010, 0x10, 0, 3), + PIN_FIELD_BASE(213, 213, 5, 0x0010, 0x10, 3, 3), + PIN_FIELD_BASE(214, 214, 5, 0x0000, 0x10, 0, 3), + PIN_FIELD_BASE(215, 215, 5, 0x0000, 0x10, 27, 3), + PIN_FIELD_BASE(216, 216, 5, 0x0000, 0x10, 12, 3), + PIN_FIELD_BASE(217, 217, 5, 0x0000, 0x10, 15, 3), + PIN_FIELD_BASE(218, 218, 5, 0x0000, 0x10, 3, 3), + PIN_FIELD_BASE(219, 219, 5, 0x0000, 0x10, 6, 3), +}; + +static const struct mtk_pin_field_calc mt8192_pin_pupd_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0060, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0060, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0060, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0060, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0060, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0060, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0060, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0060, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0060, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0060, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0060, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0060, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 31, 1), + PIN_FIELD_BASE(152, 152, 7, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 31, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 31, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0030, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0030, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0030, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0030, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0030, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0030, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 31, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 31, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_r0_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0080, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0080, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0080, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0080, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0080, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0080, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0080, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0080, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0080, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0080, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0080, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0080, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 0, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 12, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 10, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 22, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 8, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 20, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 6, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 18, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 4, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 16, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 2, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 14, 1), + PIN_FIELD_BASE(152, 152, 7, 0x00c0, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x00c0, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x00c0, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x00c0, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 2, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 6, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 2, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 0, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 4, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_r1_range[] = { + PIN_FIELD_BASE(10, 10, 6, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(11, 11, 6, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(12, 12, 6, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(13, 13, 6, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(14, 14, 6, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(15, 15, 6, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(45, 45, 1, 0x0090, 0x10, 9, 1), + PIN_FIELD_BASE(46, 46, 1, 0x0090, 0x10, 11, 1), + PIN_FIELD_BASE(47, 47, 1, 0x0090, 0x10, 10, 1), + PIN_FIELD_BASE(48, 48, 1, 0x0090, 0x10, 7, 1), + PIN_FIELD_BASE(49, 49, 1, 0x0090, 0x10, 8, 1), + PIN_FIELD_BASE(50, 50, 1, 0x0090, 0x10, 6, 1), + PIN_FIELD_BASE(51, 51, 1, 0x0090, 0x10, 0, 1), + PIN_FIELD_BASE(52, 52, 1, 0x0090, 0x10, 1, 1), + PIN_FIELD_BASE(53, 53, 1, 0x0090, 0x10, 5, 1), + PIN_FIELD_BASE(54, 54, 1, 0x0090, 0x10, 2, 1), + PIN_FIELD_BASE(55, 55, 1, 0x0090, 0x10, 4, 1), + PIN_FIELD_BASE(56, 56, 1, 0x0090, 0x10, 3, 1), + PIN_FIELD_BASE(118, 118, 4, 0x00e0, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x00e0, 0x10, 13, 1), + PIN_FIELD_BASE(120, 120, 4, 0x00e0, 0x10, 11, 1), + PIN_FIELD_BASE(121, 121, 4, 0x00e0, 0x10, 23, 1), + PIN_FIELD_BASE(122, 122, 4, 0x00e0, 0x10, 9, 1), + PIN_FIELD_BASE(123, 123, 4, 0x00e0, 0x10, 21, 1), + PIN_FIELD_BASE(124, 124, 4, 0x00e0, 0x10, 7, 1), + PIN_FIELD_BASE(125, 125, 4, 0x00e0, 0x10, 19, 1), + PIN_FIELD_BASE(139, 139, 4, 0x00e0, 0x10, 5, 1), + PIN_FIELD_BASE(140, 140, 4, 0x00e0, 0x10, 17, 1), + PIN_FIELD_BASE(141, 141, 4, 0x00e0, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 4, 0x00e0, 0x10, 15, 1), + PIN_FIELD_BASE(152, 152, 7, 0x00d0, 0x10, 3, 1), + PIN_FIELD_BASE(153, 153, 7, 0x00d0, 0x10, 2, 1), + PIN_FIELD_BASE(154, 154, 7, 0x00d0, 0x10, 0, 1), + PIN_FIELD_BASE(155, 155, 7, 0x00d0, 0x10, 1, 1), + PIN_FIELD_BASE(160, 160, 7, 0x00f0, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 7, 0x00f0, 0x10, 3, 1), + PIN_FIELD_BASE(183, 183, 9, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(184, 184, 9, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(185, 185, 9, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(186, 186, 9, 0x0050, 0x10, 6, 1), + PIN_FIELD_BASE(187, 187, 9, 0x0050, 0x10, 8, 1), + PIN_FIELD_BASE(188, 188, 9, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(189, 189, 9, 0x0050, 0x10, 7, 1), + PIN_FIELD_BASE(190, 190, 9, 0x0050, 0x10, 9, 1), + PIN_FIELD_BASE(191, 191, 9, 0x0050, 0x10, 10, 1), + PIN_FIELD_BASE(192, 192, 9, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(193, 193, 9, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(194, 194, 9, 0x0050, 0x10, 11, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0070, 0x10, 7, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0070, 0x10, 3, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0070, 0x10, 1, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0070, 0x10, 5, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e1e0en_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 0, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 18, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 15, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 3, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 12, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 0, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 9, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 27, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 6, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 24, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 3, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 21, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 0, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 3, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 3, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 9, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 0, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 3, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 0, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 6, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e0_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 1, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 19, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 16, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 4, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 13, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 1, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 10, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 28, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 7, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 25, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 4, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 22, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 1, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 4, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 4, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 10, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 1, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 4, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 1, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 7, 1), +}; + +static const struct mtk_pin_field_calc mt8192_pin_e1_range[] = { + PIN_FIELD_BASE(118, 118, 4, 0x0040, 0x10, 2, 1), + PIN_FIELD_BASE(119, 119, 4, 0x0040, 0x10, 20, 1), + PIN_FIELD_BASE(120, 120, 4, 0x0040, 0x10, 17, 1), + PIN_FIELD_BASE(121, 121, 4, 0x0050, 0x10, 5, 1), + PIN_FIELD_BASE(122, 122, 4, 0x0040, 0x10, 14, 1), + PIN_FIELD_BASE(123, 123, 4, 0x0050, 0x10, 2, 1), + PIN_FIELD_BASE(124, 124, 4, 0x0040, 0x10, 11, 1), + PIN_FIELD_BASE(125, 125, 4, 0x0040, 0x10, 29, 1), + PIN_FIELD_BASE(139, 139, 4, 0x0040, 0x10, 8, 1), + PIN_FIELD_BASE(140, 140, 4, 0x0040, 0x10, 26, 1), + PIN_FIELD_BASE(141, 141, 4, 0x0040, 0x10, 5, 1), + PIN_FIELD_BASE(142, 142, 4, 0x0040, 0x10, 23, 1), + PIN_FIELD_BASE(160, 160, 7, 0x0030, 0x10, 2, 1), + PIN_FIELD_BASE(161, 161, 7, 0x0030, 0x10, 5, 1), + PIN_FIELD_BASE(200, 200, 8, 0x0010, 0x10, 5, 1), + PIN_FIELD_BASE(201, 201, 8, 0x0010, 0x10, 11, 1), + PIN_FIELD_BASE(202, 202, 5, 0x0020, 0x10, 2, 1), + PIN_FIELD_BASE(203, 203, 5, 0x0020, 0x10, 5, 1), + PIN_FIELD_BASE(204, 204, 8, 0x0010, 0x10, 2, 1), + PIN_FIELD_BASE(205, 205, 8, 0x0010, 0x10, 8, 1), +}; + + +static const char * const mt8192_pinctrl_register_base_names[] = { + "iocfg0", "iocfg_rm", "iocfg_bm", "iocfg_bl", "iocfg_br", + "iocfg_lm", "iocfg_lb", "iocfg_rt", "iocfg_lt", "iocfg_tl", +}; + +static const struct mtk_eint_hw mt8192_eint_hw = { + .port_mask = 7, + .ports = 7, + .ap_num = 224, + .db_cnt = 32, +}; + +static const struct mtk_pin_reg_calc mt8192_reg_cals[PINCTRL_PIN_REG_MAX] = { + [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt8192_pin_mode_range), + [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt8192_pin_dir_range), + [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt8192_pin_di_range), + [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt8192_pin_do_range), + [PINCTRL_PIN_REG_SR] = MTK_RANGE(mt8192_pin_dir_range), + [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt8192_pin_smt_range), + [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt8192_pin_ies_range), + [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt8192_pin_pu_range), + [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt8192_pin_pd_range), + [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt8192_pin_drv_range), + [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt8192_pin_pupd_range), + [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt8192_pin_r0_range), + [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt8192_pin_r1_range), + [PINCTRL_PIN_REG_DRV_EN] = MTK_RANGE(mt8192_pin_e1e0en_range), + [PINCTRL_PIN_REG_DRV_E0] = MTK_RANGE(mt8192_pin_e0_range), + [PINCTRL_PIN_REG_DRV_E1] = MTK_RANGE(mt8192_pin_e1_range), +}; + +static const struct mtk_pin_soc mt8192_data = { + .reg_cal = mt8192_reg_cals, + .pins = mtk_pins_mt8192, + .npins = ARRAY_SIZE(mtk_pins_mt8192), + .ngrps = ARRAY_SIZE(mtk_pins_mt8192), + .base_names = mt8192_pinctrl_register_base_names, + .nbase_names = ARRAY_SIZE(mt8192_pinctrl_register_base_names), + .eint_hw = &mt8192_eint_hw, + .nfuncs = 8, + .gpio_m = 0, + .bias_set_combo = mtk_pinconf_bias_set_combo, + .bias_get_combo = mtk_pinconf_bias_get_combo, + .drive_set = mtk_pinconf_drive_set_raw, + .drive_get = mtk_pinconf_drive_get_raw, + .adv_pull_get = mtk_pinconf_adv_pull_get, + .adv_pull_set = mtk_pinconf_adv_pull_set, + .adv_drive_get = mtk_pinconf_adv_drive_get, + .adv_drive_set = mtk_pinconf_adv_drive_set, +}; + +static const struct of_device_id mt8192_pinctrl_of_match[] = { + { .compatible = "mediatek,mt8192-pinctrl", }, + { } +}; + +static int mt8192_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_paris_pinctrl_probe(pdev, &mt8192_data); +} + +static struct platform_driver mt8192_pinctrl_driver = { + .driver = { + .name = "mt8192-pinctrl", + .of_match_table = mt8192_pinctrl_of_match, + .pm = &mtk_paris_pinctrl_pm_ops, + }, + .probe = mt8192_pinctrl_probe, +}; + +static int __init mt8192_pinctrl_init(void) +{ + return platform_driver_register(&mt8192_pinctrl_driver); +} +arch_initcall(mt8192_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT8192 Pinctrl Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h new file mode 100644 index 000000000000..071162141376 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8192.h @@ -0,0 +1,2275 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 MediaTek Inc. + * Author: Andy Teng + * + */ + +#ifndef __PINCTRL_MTK_MT8192_H +#define __PINCTRL_MTK_MT8192_H + +#include "pinctrl-paris.h" + +static const struct mtk_pin_desc mtk_pins_mt8192[] = { + MTK_PIN( + 0, "GPIO0", + MTK_EINT_FUNCTION(0, 0), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "SPI6_CLK"), + MTK_FUNCTION(2, "I2S5_MCK"), + MTK_FUNCTION(3, "PWM_0"), + MTK_FUNCTION(4, "TDM_LRCK"), + MTK_FUNCTION(5, "TP_GPIO0_AO"), + MTK_FUNCTION(6, "MD_INT0") + ), + MTK_PIN( + 1, "GPIO1", + MTK_EINT_FUNCTION(0, 1), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "SPI6_CSB"), + MTK_FUNCTION(2, "I2S5_BCK"), + MTK_FUNCTION(3, "PWM_1"), + MTK_FUNCTION(4, "TDM_BCK"), + MTK_FUNCTION(5, "TP_GPIO1_AO"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_A9") + ), + MTK_PIN( + 2, "GPIO2", + MTK_EINT_FUNCTION(0, 2), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "SPI6_MI"), + MTK_FUNCTION(2, "I2S5_LRCK"), + MTK_FUNCTION(3, "PWM_2"), + MTK_FUNCTION(4, "TDM_MCK"), + MTK_FUNCTION(5, "TP_GPIO2_AO"), + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_A10") + ), + MTK_PIN( + 3, "GPIO3", + MTK_EINT_FUNCTION(0, 3), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "SPI6_MO"), + MTK_FUNCTION(2, "I2S5_DO"), + MTK_FUNCTION(3, "PWM_3"), + MTK_FUNCTION(4, "TDM_DATA0"), + MTK_FUNCTION(5, "TP_GPIO3_AO"), + MTK_FUNCTION(6, "CLKM0"), + MTK_FUNCTION(7, "DBG_MON_A11") + ), + MTK_PIN( + 4, "GPIO4", + MTK_EINT_FUNCTION(0, 4), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "SPI4_A_CLK"), + MTK_FUNCTION(2, "I2S2_MCK"), + MTK_FUNCTION(3, "DMIC1_CLK"), + MTK_FUNCTION(4, "TDM_DATA1"), + MTK_FUNCTION(5, "TP_GPIO4_AO"), + MTK_FUNCTION(6, "PCM1_DI"), + MTK_FUNCTION(7, "IDDIG") + ), + MTK_PIN( + 5, "GPIO5", + MTK_EINT_FUNCTION(0, 5), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "SPI4_A_CSB"), + MTK_FUNCTION(2, "I2S2_BCK"), + MTK_FUNCTION(3, "DMIC1_DAT"), + MTK_FUNCTION(4, "TDM_DATA2"), + MTK_FUNCTION(5, "TP_GPIO5_AO"), + MTK_FUNCTION(6, "PCM1_CLK"), + MTK_FUNCTION(7, "USB_DRVVBUS") + ), + MTK_PIN( + 6, "GPIO6", + MTK_EINT_FUNCTION(0, 6), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "SPI4_A_MI"), + MTK_FUNCTION(2, "I2S2_LRCK"), + MTK_FUNCTION(3, "DMIC_CLK"), + MTK_FUNCTION(4, "TDM_DATA3"), + MTK_FUNCTION(5, "TP_GPIO6_AO"), + MTK_FUNCTION(6, "PCM1_SYNC") + ), + MTK_PIN( + 7, "GPIO7", + MTK_EINT_FUNCTION(0, 7), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SPI4_A_MO"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "DMIC_DAT"), + MTK_FUNCTION(4, "WIFI_TXD"), + MTK_FUNCTION(5, "TP_GPIO7_AO"), + MTK_FUNCTION(6, "PCM1_DO0") + ), + MTK_PIN( + 8, "GPIO8", + MTK_EINT_FUNCTION(0, 8), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "I2S2_DI2"), + MTK_FUNCTION(3, "KPCOL2"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "CLKM1"), + MTK_FUNCTION(6, "PCM1_DO1"), + MTK_FUNCTION(7, "DBG_MON_A12") + ), + MTK_PIN( + 9, "GPIO9", + MTK_EINT_FUNCTION(0, 9), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(3, "KPROW2"), + MTK_FUNCTION(4, "CMMCLK4"), + MTK_FUNCTION(5, "CLKM3"), + MTK_FUNCTION(6, "PCM1_DO2"), + MTK_FUNCTION(7, "DBG_MON_A13") + ), + MTK_PIN( + 10, "GPIO10", + MTK_EINT_FUNCTION(0, 10), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "SPI4_B_CLK"), + MTK_FUNCTION(3, "I2S8_MCK"), + MTK_FUNCTION(5, "MD_INT0"), + MTK_FUNCTION(6, "TP_GPIO8_AO") + ), + MTK_PIN( + 11, "GPIO11", + MTK_EINT_FUNCTION(0, 11), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "SPI4_B_CSB"), + MTK_FUNCTION(3, "I2S8_BCK"), + MTK_FUNCTION(4, "PCIE_CLKREQ_N"), + MTK_FUNCTION(5, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO9_AO") + ), + MTK_PIN( + 12, "GPIO12", + MTK_EINT_FUNCTION(0, 12), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "SPI4_B_MI"), + MTK_FUNCTION(3, "I2S8_LRCK"), + MTK_FUNCTION(4, "DMIC1_CLK"), + MTK_FUNCTION(5, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(6, "TP_GPIO10_AO") + ), + MTK_PIN( + 13, "GPIO13", + MTK_EINT_FUNCTION(0, 13), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "SPI4_B_MO"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "DMIC1_DAT"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "TP_GPIO11_AO") + ), + MTK_PIN( + 14, "GPIO14", + MTK_EINT_FUNCTION(0, 14), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "SCL_6306"), + MTK_FUNCTION(4, "PCIE_PERESET_N"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "TP_GPIO12_AO") + ), + MTK_PIN( + 15, "GPIO15", + MTK_EINT_FUNCTION(0, 15), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "PCIE_WAKE_N"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "TP_GPIO13_AO") + ), + MTK_PIN( + 16, "GPIO16", + MTK_EINT_FUNCTION(0, 16), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "TP_GPIO14_AO"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "SPI7_A_MI"), + MTK_FUNCTION(7, "DBG_MON_A0") + ), + MTK_PIN( + 17, "GPIO17", + MTK_EINT_FUNCTION(0, 17), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "TP_GPIO15_AO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(6, "SPI7_A_MO"), + MTK_FUNCTION(7, "DBG_MON_A1") + ), + MTK_PIN( + 18, "GPIO18", + MTK_EINT_FUNCTION(0, 18), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI4_C_MI"), + MTK_FUNCTION(3, "SPI1_B_MI"), + MTK_FUNCTION(4, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(5, "ANT_SEL10"), + MTK_FUNCTION(6, "MD_INT0"), + MTK_FUNCTION(7, "DBG_MON_B2") + ), + MTK_PIN( + 19, "GPIO19", + MTK_EINT_FUNCTION(0, 19), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI4_C_MO"), + MTK_FUNCTION(3, "SPI1_B_MO"), + MTK_FUNCTION(5, "ANT_SEL11"), + MTK_FUNCTION(6, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_B3") + ), + MTK_PIN( + 20, "GPIO20", + MTK_EINT_FUNCTION(0, 20), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI4_C_CLK"), + MTK_FUNCTION(3, "SPI1_B_CLK"), + MTK_FUNCTION(4, "PWM_3"), + MTK_FUNCTION(5, "ANT_SEL12"), + MTK_FUNCTION(6, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(7, "DBG_MON_B4") + ), + MTK_PIN( + 21, "GPIO21", + MTK_EINT_FUNCTION(0, 21), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(2, "SPI4_C_CSB"), + MTK_FUNCTION(3, "SPI1_B_CSB"), + MTK_FUNCTION(6, "IDDIG"), + MTK_FUNCTION(7, "DBG_MON_B5") + ), + MTK_PIN( + 22, "GPIO22", + MTK_EINT_FUNCTION(0, 22), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(2, "SPI0_C_CLK"), + MTK_FUNCTION(3, "SPI7_B_CLK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK"), + MTK_FUNCTION(6, "SCL_6306") + ), + MTK_PIN( + 23, "GPIO23", + MTK_EINT_FUNCTION(0, 23), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(2, "SPI0_C_CSB"), + MTK_FUNCTION(3, "SPI7_B_CSB"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(6, "SDA_6306") + ), + MTK_PIN( + 24, "GPIO24", + MTK_EINT_FUNCTION(0, 24), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "SRCLKENAI1"), + MTK_FUNCTION(2, "SPI0_C_MI"), + MTK_FUNCTION(3, "SPI7_B_MI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI"), + MTK_FUNCTION(6, "SPINOR_CS") + ), + MTK_PIN( + 25, "GPIO25", + MTK_EINT_FUNCTION(0, 25), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "SRCLKENAI0"), + MTK_FUNCTION(2, "SPI0_C_MO"), + MTK_FUNCTION(3, "SPI7_B_MO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "SPINOR_CK") + ), + MTK_PIN( + 26, "GPIO26", + MTK_EINT_FUNCTION(0, 26), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "SPI5_C_MI"), + MTK_FUNCTION(5, "I2S9_BCK") + ), + MTK_PIN( + 27, "GPIO27", + MTK_EINT_FUNCTION(0, 27), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "PWM_3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(4, "SPI5_C_MO"), + MTK_FUNCTION(5, "I2S9_LRCK"), + MTK_FUNCTION(6, "SPINOR_IO0") + ), + MTK_PIN( + 28, "GPIO28", + MTK_EINT_FUNCTION(0, 28), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(4, "SPI5_C_CSB"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "SPINOR_IO1") + ), + MTK_PIN( + 29, "GPIO29", + MTK_EINT_FUNCTION(0, 29), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(4, "SPI5_C_CLK"), + MTK_FUNCTION(5, "I2S9_DO"), + MTK_FUNCTION(6, "SPINOR_IO2") + ), + MTK_PIN( + 30, "GPIO30", + MTK_EINT_FUNCTION(0, 30), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWM_2"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK"), + MTK_FUNCTION(6, "SPINOR_IO3") + ), + MTK_PIN( + 31, "GPIO31", + MTK_EINT_FUNCTION(0, 31), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "I2S3_MCK"), + MTK_FUNCTION(2, "I2S1_MCK"), + MTK_FUNCTION(3, "I2S5_MCK"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "I2S0_MCK") + ), + MTK_PIN( + 32, "GPIO32", + MTK_EINT_FUNCTION(0, 32), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "I2S3_BCK"), + MTK_FUNCTION(2, "I2S1_BCK"), + MTK_FUNCTION(3, "I2S5_BCK"), + MTK_FUNCTION(4, "PCM0_CLK"), + MTK_FUNCTION(5, "I2S0_BCK") + ), + MTK_PIN( + 33, "GPIO33", + MTK_EINT_FUNCTION(0, 33), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "I2S3_LRCK"), + MTK_FUNCTION(2, "I2S1_LRCK"), + MTK_FUNCTION(3, "I2S5_LRCK"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(5, "I2S0_LRCK") + ), + MTK_PIN( + 34, "GPIO34", + MTK_EINT_FUNCTION(0, 34), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "I2S2_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(5, "I2S0_DI") + ), + MTK_PIN( + 35, "GPIO35", + MTK_EINT_FUNCTION(0, 35), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "I2S3_DO"), + MTK_FUNCTION(2, "I2S1_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "PCM0_DO") + ), + MTK_PIN( + 36, "GPIO36", + MTK_EINT_FUNCTION(0, 36), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "SPI5_A_CLK"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(4, "MD_URXD0"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(6, "URXD1") + ), + MTK_PIN( + 37, "GPIO37", + MTK_EINT_FUNCTION(0, 37), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "SPI5_A_CSB"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(4, "MD_UTXD0"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(6, "UTXD1") + ), + MTK_PIN( + 38, "GPIO38", + MTK_EINT_FUNCTION(0, 38), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "SPI5_A_MI"), + MTK_FUNCTION(2, "DMIC_CLK"), + MTK_FUNCTION(4, "MD_URXD1"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "UCTS1") + ), + MTK_PIN( + 39, "GPIO39", + MTK_EINT_FUNCTION(0, 39), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "SPI5_A_MO"), + MTK_FUNCTION(2, "DMIC_DAT"), + MTK_FUNCTION(4, "MD_UTXD1"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "URTS1") + ), + MTK_PIN( + 40, "GPIO40", + MTK_EINT_FUNCTION(0, 40), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(7, "DBG_MON_A6") + ), + MTK_PIN( + 41, "GPIO41", + MTK_EINT_FUNCTION(0, 41), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(7, "DBG_MON_A7") + ), + MTK_PIN( + 42, "GPIO42", + MTK_EINT_FUNCTION(0, 42), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(7, "DBG_MON_A8") + ), + MTK_PIN( + 43, "GPIO43", + MTK_EINT_FUNCTION(0, 43), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(3, "SCL_6306"), + MTK_FUNCTION(4, "ADSP_URXD0"), + MTK_FUNCTION(5, "PTA_RXD"), + MTK_FUNCTION(6, "SSPM_URXD_AO"), + MTK_FUNCTION(7, "DBG_MON_B0") + ), + MTK_PIN( + 44, "GPIO44", + MTK_EINT_FUNCTION(0, 44), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "MD_INT2_C2K_UIM1_HOT_PLUG"), + MTK_FUNCTION(2, "MD_INT1_C2K_UIM0_HOT_PLUG"), + MTK_FUNCTION(3, "SDA_6306"), + MTK_FUNCTION(4, "ADSP_UTXD0"), + MTK_FUNCTION(5, "PTA_TXD"), + MTK_FUNCTION(6, "SSPM_UTXD_AO"), + MTK_FUNCTION(7, "DBG_MON_B1") + ), + MTK_PIN( + 45, "GPIO45", + MTK_EINT_FUNCTION(0, 45), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "MD1_SIM2_SCLK"), + MTK_FUNCTION(2, "MD1_SIM1_SCLK"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDI"), + MTK_FUNCTION(4, "APU_JTAG_TDI"), + MTK_FUNCTION(5, "CCU_JTAG_TDI"), + MTK_FUNCTION(6, "LVTS_SCK"), + MTK_FUNCTION(7, "CONN_DSP_JDI") + ), + MTK_PIN( + 46, "GPIO46", + MTK_EINT_FUNCTION(0, 46), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "MD1_SIM2_SRST"), + MTK_FUNCTION(2, "MD1_SIM1_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TMS"), + MTK_FUNCTION(4, "APU_JTAG_TMS"), + MTK_FUNCTION(5, "CCU_JTAG_TMS"), + MTK_FUNCTION(6, "LVTS_SDI"), + MTK_FUNCTION(7, "CONN_DSP_JMS") + ), + MTK_PIN( + 47, "GPIO47", + MTK_EINT_FUNCTION(0, 47), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "MD1_SIM2_SIO"), + MTK_FUNCTION(2, "MD1_SIM1_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TDO"), + MTK_FUNCTION(4, "APU_JTAG_TDO"), + MTK_FUNCTION(5, "CCU_JTAG_TDO"), + MTK_FUNCTION(6, "LVTS_SCF"), + MTK_FUNCTION(7, "CONN_DSP_JDO") + ), + MTK_PIN( + 48, "GPIO48", + MTK_EINT_FUNCTION(0, 48), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "MD1_SIM1_SIO"), + MTK_FUNCTION(2, "MD1_SIM2_SIO"), + MTK_FUNCTION(3, "MCUPM_JTAG_TRSTN"), + MTK_FUNCTION(4, "APU_JTAG_TRST"), + MTK_FUNCTION(5, "CCU_JTAG_TRST"), + MTK_FUNCTION(6, "LVTS_FOUT"), + MTK_FUNCTION(7, "CONN_DSP_JINTP") + ), + MTK_PIN( + 49, "GPIO49", + MTK_EINT_FUNCTION(0, 49), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "MD1_SIM1_SRST"), + MTK_FUNCTION(2, "MD1_SIM2_SRST"), + MTK_FUNCTION(3, "MCUPM_JTAG_TCK"), + MTK_FUNCTION(4, "APU_JTAG_TCK"), + MTK_FUNCTION(5, "CCU_JTAG_TCK"), + MTK_FUNCTION(6, "LVTS_SDO"), + MTK_FUNCTION(7, "CONN_DSP_JCK") + ), + MTK_PIN( + 50, "GPIO50", + MTK_EINT_FUNCTION(0, 50), + DRV_GRP0, + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "MD1_SIM1_SCLK"), + MTK_FUNCTION(2, "MD1_SIM2_SCLK"), + MTK_FUNCTION(6, "LVTS_26M") + ), + MTK_PIN( + 51, "GPIO51", + MTK_EINT_FUNCTION(0, 51), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "PCM1_CLK"), + MTK_FUNCTION(3, "CONN_DSP_JCK"), + MTK_FUNCTION(4, "UDI_TCK"), + MTK_FUNCTION(5, "IPU_JTAG_TCK"), + MTK_FUNCTION(6, "SSPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL3") + ), + MTK_PIN( + 52, "GPIO52", + MTK_EINT_FUNCTION(0, 52), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(2, "PCM1_SYNC"), + MTK_FUNCTION(3, "CONN_DSP_JMS"), + MTK_FUNCTION(4, "UDI_TMS"), + MTK_FUNCTION(5, "IPU_JTAG_TMS"), + MTK_FUNCTION(6, "SSPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL3") + ), + MTK_PIN( + 53, "GPIO53", + MTK_EINT_FUNCTION(0, 53), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "PCM1_DI"), + MTK_FUNCTION(3, "CONN_DSP_JINTP"), + MTK_FUNCTION(4, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 54, "GPIO54", + MTK_EINT_FUNCTION(0, 54), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "PCM1_DO0"), + MTK_FUNCTION(3, "CONN_DSP_JDI"), + MTK_FUNCTION(4, "UDI_TDI"), + MTK_FUNCTION(5, "IPU_JTAG_TDI"), + MTK_FUNCTION(6, "SSPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL3") + ), + MTK_PIN( + 55, "GPIO55", + MTK_EINT_FUNCTION(0, 55), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "PCM1_DO2"), + MTK_FUNCTION(3, "CONN_MCU_AICE_TCKC"), + MTK_FUNCTION(4, "UDI_NTRST"), + MTK_FUNCTION(5, "IPU_JTAG_TRST"), + MTK_FUNCTION(6, "SSPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL3") + ), + MTK_PIN( + 56, "GPIO56", + MTK_EINT_FUNCTION(0, 56), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "PCM1_DO1"), + MTK_FUNCTION(3, "CONN_DSP_JDO"), + MTK_FUNCTION(4, "UDI_TDO"), + MTK_FUNCTION(5, "IPU_JTAG_TDO"), + MTK_FUNCTION(6, "SSPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL3") + ), + MTK_PIN( + 57, "GPIO57", + MTK_EINT_FUNCTION(0, 57), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "MIPI2_D_SCLK") + ), + MTK_PIN( + 58, "GPIO58", + MTK_EINT_FUNCTION(0, 58), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "MIPI2_D_SDATA") + ), + MTK_PIN( + 59, "GPIO59", + MTK_EINT_FUNCTION(0, 59), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "MIPI_M_SCLK") + ), + MTK_PIN( + 60, "GPIO60", + MTK_EINT_FUNCTION(0, 60), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "MIPI_M_SDATA") + ), + MTK_PIN( + 61, "GPIO61", + MTK_EINT_FUNCTION(0, 61), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "MD_UCNT_A_TGL") + ), + MTK_PIN( + 62, "GPIO62", + MTK_EINT_FUNCTION(0, 62), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "DIGRF_IRQ") + ), + MTK_PIN( + 63, "GPIO63", + MTK_EINT_FUNCTION(0, 63), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "BPI_BUS0"), + MTK_FUNCTION(3, "PCIE_WAKE_N") + ), + MTK_PIN( + 64, "GPIO64", + MTK_EINT_FUNCTION(0, 64), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "BPI_BUS1"), + MTK_FUNCTION(3, "PCIE_PERESET_N") + ), + MTK_PIN( + 65, "GPIO65", + MTK_EINT_FUNCTION(0, 65), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "BPI_BUS2"), + MTK_FUNCTION(3, "PCIE_CLKREQ_N") + ), + MTK_PIN( + 66, "GPIO66", + MTK_EINT_FUNCTION(0, 66), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "BPI_BUS3") + ), + MTK_PIN( + 67, "GPIO67", + MTK_EINT_FUNCTION(0, 67), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "BPI_BUS4") + ), + MTK_PIN( + 68, "GPIO68", + MTK_EINT_FUNCTION(0, 68), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "BPI_BUS5") + ), + MTK_PIN( + 69, "GPIO69", + MTK_EINT_FUNCTION(0, 69), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "BPI_BUS6"), + MTK_FUNCTION(2, "CONN_BPI_BUS6") + ), + MTK_PIN( + 70, "GPIO70", + MTK_EINT_FUNCTION(0, 70), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "BPI_BUS7"), + MTK_FUNCTION(2, "CONN_BPI_BUS7") + ), + MTK_PIN( + 71, "GPIO71", + MTK_EINT_FUNCTION(0, 71), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "BPI_BUS8"), + MTK_FUNCTION(2, "CONN_BPI_BUS8") + ), + MTK_PIN( + 72, "GPIO72", + MTK_EINT_FUNCTION(0, 72), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "BPI_BUS9"), + MTK_FUNCTION(2, "CONN_BPI_BUS9") + ), + MTK_PIN( + 73, "GPIO73", + MTK_EINT_FUNCTION(0, 73), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "BPI_BUS10"), + MTK_FUNCTION(2, "CONN_BPI_BUS10") + ), + MTK_PIN( + 74, "GPIO74", + MTK_EINT_FUNCTION(0, 74), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO74"), + MTK_FUNCTION(1, "BPI_BUS11_OLAT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS11_OLAT0") + ), + MTK_PIN( + 75, "GPIO75", + MTK_EINT_FUNCTION(0, 75), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO75"), + MTK_FUNCTION(1, "BPI_BUS12_OLAT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS12_OLAT1") + ), + MTK_PIN( + 76, "GPIO76", + MTK_EINT_FUNCTION(0, 76), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO76"), + MTK_FUNCTION(1, "BPI_BUS13_OLAT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS13_OLAT2") + ), + MTK_PIN( + 77, "GPIO77", + MTK_EINT_FUNCTION(0, 77), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO77"), + MTK_FUNCTION(1, "BPI_BUS14_OLAT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS14_OLAT3") + ), + MTK_PIN( + 78, "GPIO78", + MTK_EINT_FUNCTION(0, 78), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO78"), + MTK_FUNCTION(1, "BPI_BUS15_OLAT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS15_OLAT4") + ), + MTK_PIN( + 79, "GPIO79", + MTK_EINT_FUNCTION(0, 79), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO79"), + MTK_FUNCTION(1, "BPI_BUS16_OLAT5"), + MTK_FUNCTION(2, "CONN_BPI_BUS16_OLAT5") + ), + MTK_PIN( + 80, "GPIO80", + MTK_EINT_FUNCTION(0, 80), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO80"), + MTK_FUNCTION(1, "BPI_BUS17_ANT0"), + MTK_FUNCTION(2, "CONN_BPI_BUS17_ANT0"), + MTK_FUNCTION(3, "PCIE_WAKE_N") + ), + MTK_PIN( + 81, "GPIO81", + MTK_EINT_FUNCTION(0, 81), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO81"), + MTK_FUNCTION(1, "BPI_BUS18_ANT1"), + MTK_FUNCTION(2, "CONN_BPI_BUS18_ANT1"), + MTK_FUNCTION(3, "PCIE_PERESET_N") + ), + MTK_PIN( + 82, "GPIO82", + MTK_EINT_FUNCTION(0, 82), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO82"), + MTK_FUNCTION(1, "BPI_BUS19_ANT2"), + MTK_FUNCTION(2, "CONN_BPI_BUS19_ANT2"), + MTK_FUNCTION(3, "PCIE_CLKREQ_N") + ), + MTK_PIN( + 83, "GPIO83", + MTK_EINT_FUNCTION(0, 83), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO83"), + MTK_FUNCTION(1, "BPI_BUS20_ANT3"), + MTK_FUNCTION(2, "CONN_BPI_BUS20_ANT3") + ), + MTK_PIN( + 84, "GPIO84", + MTK_EINT_FUNCTION(0, 84), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO84"), + MTK_FUNCTION(1, "BPI_BUS21_ANT4"), + MTK_FUNCTION(2, "CONN_BPI_BUS21_ANT4") + ), + MTK_PIN( + 85, "GPIO85", + MTK_EINT_FUNCTION(0, 85), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO85"), + MTK_FUNCTION(1, "MIPI1_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI1_SCLK") + ), + MTK_PIN( + 86, "GPIO86", + MTK_EINT_FUNCTION(0, 86), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO86"), + MTK_FUNCTION(1, "MIPI1_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI1_SDATA") + ), + MTK_PIN( + 87, "GPIO87", + MTK_EINT_FUNCTION(0, 87), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO87"), + MTK_FUNCTION(1, "MIPI0_D_SCLK"), + MTK_FUNCTION(2, "CONN_MIPI0_SCLK") + ), + MTK_PIN( + 88, "GPIO88", + MTK_EINT_FUNCTION(0, 88), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO88"), + MTK_FUNCTION(1, "MIPI0_D_SDATA"), + MTK_FUNCTION(2, "CONN_MIPI0_SDATA") + ), + MTK_PIN( + 89, "GPIO89", + MTK_EINT_FUNCTION(0, 89), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO89"), + MTK_FUNCTION(1, "SPMI_SCL"), + MTK_FUNCTION(2, "SCL10") + ), + MTK_PIN( + 90, "GPIO90", + MTK_EINT_FUNCTION(0, 90), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO90"), + MTK_FUNCTION(1, "SPMI_SDA"), + MTK_FUNCTION(2, "SDA10") + ), + MTK_PIN( + 91, "GPIO91", + MTK_EINT_FUNCTION(0, 91), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO91"), + MTK_FUNCTION(1, "AP_GOOD") + ), + MTK_PIN( + 92, "GPIO92", + MTK_EINT_FUNCTION(0, 92), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO92"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "MD_URXD0"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "CONN_UART0_RXD") + ), + MTK_PIN( + 93, "GPIO93", + MTK_EINT_FUNCTION(0, 93), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO93"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "MD_UTXD0"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "CONN_UART0_TXD"), + MTK_FUNCTION(6, "WIFI_TXD") + ), + MTK_PIN( + 94, "GPIO94", + MTK_EINT_FUNCTION(0, 94), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO94"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "ADSP_URXD0"), + MTK_FUNCTION(3, "MD32_0_RXD"), + MTK_FUNCTION(4, "SSPM_URXD_AO"), + MTK_FUNCTION(5, "TP_URXD1_AO"), + MTK_FUNCTION(6, "TP_URXD2_AO"), + MTK_FUNCTION(7, "MBISTREADEN_TRIGGER") + ), + MTK_PIN( + 95, "GPIO95", + MTK_EINT_FUNCTION(0, 95), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO95"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "ADSP_UTXD0"), + MTK_FUNCTION(3, "MD32_0_TXD"), + MTK_FUNCTION(4, "SSPM_UTXD_AO"), + MTK_FUNCTION(5, "TP_UTXD1_AO"), + MTK_FUNCTION(6, "TP_UTXD2_AO"), + MTK_FUNCTION(7, "MBISTWRITEEN_TRIGGER") + ), + MTK_PIN( + 96, "GPIO96", + MTK_EINT_FUNCTION(0, 96), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO96"), + MTK_FUNCTION(1, "TDM_LRCK"), + MTK_FUNCTION(2, "I2S7_LRCK"), + MTK_FUNCTION(3, "I2S9_LRCK"), + MTK_FUNCTION(4, "DPI_D0"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDI"), + MTK_FUNCTION(7, "IO_JTAG_TDI") + ), + MTK_PIN( + 97, "GPIO97", + MTK_EINT_FUNCTION(0, 97), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO97"), + MTK_FUNCTION(1, "TDM_BCK"), + MTK_FUNCTION(2, "I2S7_BCK"), + MTK_FUNCTION(3, "I2S9_BCK"), + MTK_FUNCTION(4, "DPI_D1"), + MTK_FUNCTION(5, "ADSP_JTAG0_TRSTN"), + MTK_FUNCTION(7, "IO_JTAG_TRSTN") + ), + MTK_PIN( + 98, "GPIO98", + MTK_EINT_FUNCTION(0, 98), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO98"), + MTK_FUNCTION(1, "TDM_MCK"), + MTK_FUNCTION(2, "I2S7_MCK"), + MTK_FUNCTION(3, "I2S9_MCK"), + MTK_FUNCTION(4, "DPI_D2"), + MTK_FUNCTION(5, "ADSP_JTAG0_TCK"), + MTK_FUNCTION(7, "IO_JTAG_TCK") + ), + MTK_PIN( + 99, "GPIO99", + MTK_EINT_FUNCTION(0, 99), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO99"), + MTK_FUNCTION(1, "TDM_DATA0"), + MTK_FUNCTION(2, "I2S6_DI"), + MTK_FUNCTION(3, "I2S8_DI"), + MTK_FUNCTION(4, "DPI_D3"), + MTK_FUNCTION(5, "ADSP_JTAG0_TDO"), + MTK_FUNCTION(7, "IO_JTAG_TDO") + ), + MTK_PIN( + 100, "GPIO100", + MTK_EINT_FUNCTION(0, 100), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "TDM_DATA1"), + MTK_FUNCTION(2, "I2S7_DO"), + MTK_FUNCTION(3, "I2S9_DO"), + MTK_FUNCTION(4, "DPI_D4"), + MTK_FUNCTION(5, "ADSP_JTAG0_TMS"), + MTK_FUNCTION(7, "IO_JTAG_TMS") + ), + MTK_PIN( + 101, "GPIO101", + MTK_EINT_FUNCTION(0, 101), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "TDM_DATA2"), + MTK_FUNCTION(2, "DMIC1_CLK"), + MTK_FUNCTION(3, "SRCLKENAI0"), + MTK_FUNCTION(4, "DPI_D5"), + MTK_FUNCTION(5, "CLKM0"), + MTK_FUNCTION(7, "DAP_MD32_SWD") + ), + MTK_PIN( + 102, "GPIO102", + MTK_EINT_FUNCTION(0, 102), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "TDM_DATA3"), + MTK_FUNCTION(2, "DMIC1_DAT"), + MTK_FUNCTION(3, "SRCLKENAI1"), + MTK_FUNCTION(4, "DPI_D6"), + MTK_FUNCTION(6, "DVFSRC_EXT_REQ"), + MTK_FUNCTION(7, "DAP_MD32_SWCK") + ), + MTK_PIN( + 103, "GPIO103", + MTK_EINT_FUNCTION(0, 103), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "SPI0_A_MI"), + MTK_FUNCTION(2, "SCP_SPI0_MI"), + MTK_FUNCTION(4, "DPI_D7"), + MTK_FUNCTION(5, "DFD_TDO"), + MTK_FUNCTION(6, "SPM_JTAG_TDO"), + MTK_FUNCTION(7, "JTDO_SEL1") + ), + MTK_PIN( + 104, "GPIO104", + MTK_EINT_FUNCTION(0, 104), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "SPI0_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI0_CS"), + MTK_FUNCTION(4, "DPI_D8"), + MTK_FUNCTION(5, "DFD_TMS"), + MTK_FUNCTION(6, "SPM_JTAG_TMS"), + MTK_FUNCTION(7, "JTMS_SEL1") + ), + MTK_PIN( + 105, "GPIO105", + MTK_EINT_FUNCTION(0, 105), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "SPI0_A_MO"), + MTK_FUNCTION(2, "SCP_SPI0_MO"), + MTK_FUNCTION(3, "SCP_SDA0"), + MTK_FUNCTION(4, "DPI_D9"), + MTK_FUNCTION(5, "DFD_TDI"), + MTK_FUNCTION(6, "SPM_JTAG_TDI"), + MTK_FUNCTION(7, "JTDI_SEL1") + ), + MTK_PIN( + 106, "GPIO106", + MTK_EINT_FUNCTION(0, 106), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "SPI0_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI0_CK"), + MTK_FUNCTION(3, "SCP_SCL0"), + MTK_FUNCTION(4, "DPI_D10"), + MTK_FUNCTION(5, "DFD_TCK_XI"), + MTK_FUNCTION(6, "SPM_JTAG_TCK"), + MTK_FUNCTION(7, "JTCK_SEL1") + ), + MTK_PIN( + 107, "GPIO107", + MTK_EINT_FUNCTION(0, 107), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "DMIC_CLK"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "CLKM2"), + MTK_FUNCTION(6, "SPM_JTAG_TRSTN"), + MTK_FUNCTION(7, "JTRSTN_SEL1") + ), + MTK_PIN( + 108, "GPIO108", + MTK_EINT_FUNCTION(0, 108), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "DMIC_DAT"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "CLKM3"), + MTK_FUNCTION(7, "DAP_SONIC_SWD") + ), + MTK_PIN( + 109, "GPIO109", + MTK_EINT_FUNCTION(0, 109), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "I2S1_MCK"), + MTK_FUNCTION(2, "I2S3_MCK"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "DPI_DE"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "SRCLKENAI0"), + MTK_FUNCTION(7, "DAP_SONIC_SWCK") + ), + MTK_PIN( + 110, "GPIO110", + MTK_EINT_FUNCTION(0, 110), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "I2S1_BCK"), + MTK_FUNCTION(2, "I2S3_BCK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "DPI_D11"), + MTK_FUNCTION(5, "I2S2_BCK"), + MTK_FUNCTION(6, "CONN_MCU_TDO") + ), + MTK_PIN( + 111, "GPIO111", + MTK_EINT_FUNCTION(0, 111), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "I2S1_LRCK"), + MTK_FUNCTION(2, "I2S3_LRCK"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "DPI_VSYNC"), + MTK_FUNCTION(5, "I2S2_LRCK"), + MTK_FUNCTION(6, "CONN_MCU_TDI") + ), + MTK_PIN( + 112, "GPIO112", + MTK_EINT_FUNCTION(0, 112), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "I2S2_DI"), + MTK_FUNCTION(2, "I2S0_DI"), + MTK_FUNCTION(3, "I2S2_DI2"), + MTK_FUNCTION(4, "DPI_CK"), + MTK_FUNCTION(5, "I2S2_DI"), + MTK_FUNCTION(6, "CONN_MCU_TMS") + ), + MTK_PIN( + 113, "GPIO113", + MTK_EINT_FUNCTION(0, 113), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "I2S1_DO"), + MTK_FUNCTION(2, "I2S3_DO"), + MTK_FUNCTION(3, "I2S5_DO"), + MTK_FUNCTION(4, "DPI_HSYNC"), + MTK_FUNCTION(5, "I2S2_DI2"), + MTK_FUNCTION(6, "CONN_MCU_TCK") + ), + MTK_PIN( + 114, "GPIO114", + MTK_EINT_FUNCTION(0, 114), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "SPI2_MI"), + MTK_FUNCTION(2, "SCP_SPI2_MI"), + MTK_FUNCTION(4, "PCM0_DI"), + MTK_FUNCTION(6, "CONN_MCU_TRST_B") + ), + MTK_PIN( + 115, "GPIO115", + MTK_EINT_FUNCTION(0, 115), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "SPI2_CSB"), + MTK_FUNCTION(2, "SCP_SPI2_CS"), + MTK_FUNCTION(4, "PCM0_SYNC"), + MTK_FUNCTION(6, "CONN_MCU_DBGI_N") + ), + MTK_PIN( + 116, "GPIO116", + MTK_EINT_FUNCTION(0, 116), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "SPI2_MO"), + MTK_FUNCTION(2, "SCP_SPI2_MO"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(4, "PCM0_DO"), + MTK_FUNCTION(6, "CONN_MCU_DBGACK_N") + ), + MTK_PIN( + 117, "GPIO117", + MTK_EINT_FUNCTION(0, 117), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "SPI2_CLK"), + MTK_FUNCTION(2, "SCP_SPI2_CK"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(4, "PCM0_CLK") + ), + MTK_PIN( + 118, "GPIO118", + MTK_EINT_FUNCTION(0, 118), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "SCL1"), + MTK_FUNCTION(2, "SCP_SCL0"), + MTK_FUNCTION(3, "SCP_SCL1") + ), + MTK_PIN( + 119, "GPIO119", + MTK_EINT_FUNCTION(0, 119), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "SDA1"), + MTK_FUNCTION(2, "SCP_SDA0"), + MTK_FUNCTION(3, "SCP_SDA1") + ), + MTK_PIN( + 120, "GPIO120", + MTK_EINT_FUNCTION(0, 120), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "SCL9"), + MTK_FUNCTION(2, "SCP_SCL0") + ), + MTK_PIN( + 121, "GPIO121", + MTK_EINT_FUNCTION(0, 121), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "SDA9"), + MTK_FUNCTION(2, "SCP_SDA0") + ), + MTK_PIN( + 122, "GPIO122", + MTK_EINT_FUNCTION(0, 122), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "SCL8"), + MTK_FUNCTION(2, "SCP_SDA0") + ), + MTK_PIN( + 123, "GPIO123", + MTK_EINT_FUNCTION(0, 123), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "SDA8"), + MTK_FUNCTION(2, "SCP_SCL0") + ), + MTK_PIN( + 124, "GPIO124", + MTK_EINT_FUNCTION(0, 124), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "SCL7"), + MTK_FUNCTION(2, "DMIC1_CLK") + ), + MTK_PIN( + 125, "GPIO125", + MTK_EINT_FUNCTION(0, 125), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO125"), + MTK_FUNCTION(1, "SDA7"), + MTK_FUNCTION(2, "DMIC1_DAT") + ), + MTK_PIN( + 126, "GPIO126", + MTK_EINT_FUNCTION(0, 126), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO126"), + MTK_FUNCTION(1, "CMFLASH0"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "UCTS0"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(7, "DBG_MON_A14") + ), + MTK_PIN( + 127, "GPIO127", + MTK_EINT_FUNCTION(0, 127), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO127"), + MTK_FUNCTION(1, "CMFLASH1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "URTS0"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(7, "DBG_MON_A15") + ), + MTK_PIN( + 128, "GPIO128", + MTK_EINT_FUNCTION(0, 128), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO128"), + MTK_FUNCTION(1, "CMFLASH2"), + MTK_FUNCTION(2, "PWM_0"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "UCTS1"), + MTK_FUNCTION(5, "SCL_6306"), + MTK_FUNCTION(7, "DBG_MON_A16") + ), + MTK_PIN( + 129, "GPIO129", + MTK_EINT_FUNCTION(0, 129), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO129"), + MTK_FUNCTION(1, "CMFLASH3"), + MTK_FUNCTION(2, "PWM_1"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "URTS1"), + MTK_FUNCTION(5, "SDA_6306"), + MTK_FUNCTION(7, "DBG_MON_A17") + ), + MTK_PIN( + 130, "GPIO130", + MTK_EINT_FUNCTION(0, 130), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO130"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "ANT_SEL10"), + MTK_FUNCTION(3, "SCP_JTAG0_TDO"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDO"), + MTK_FUNCTION(5, "SCL11"), + MTK_FUNCTION(6, "SPI5_B_CLK"), + MTK_FUNCTION(7, "DBG_MON_A22") + ), + MTK_PIN( + 131, "GPIO131", + MTK_EINT_FUNCTION(0, 131), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO131"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "ANT_SEL11"), + MTK_FUNCTION(3, "SCP_JTAG0_TDI"), + MTK_FUNCTION(4, "MD32_0_JTAG_TDI"), + MTK_FUNCTION(5, "SDA11"), + MTK_FUNCTION(6, "SPI5_B_MO"), + MTK_FUNCTION(7, "DBG_MON_A25") + ), + MTK_PIN( + 132, "GPIO132", + MTK_EINT_FUNCTION(0, 132), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO132"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "ANT_SEL12"), + MTK_FUNCTION(3, "SCP_JTAG0_TMS"), + MTK_FUNCTION(4, "MD32_0_JTAG_TMS"), + MTK_FUNCTION(7, "DBG_MON_A28") + ), + MTK_PIN( + 133, "GPIO133", + MTK_EINT_FUNCTION(0, 133), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO133"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "SCP_JTAG0_TCK"), + MTK_FUNCTION(4, "MD32_0_JTAG_TCK"), + MTK_FUNCTION(6, "SPI5_B_CSB"), + MTK_FUNCTION(7, "DBG_MON_A23") + ), + MTK_PIN( + 134, "GPIO134", + MTK_EINT_FUNCTION(0, 134), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO134"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(3, "SCP_JTAG0_TRSTN"), + MTK_FUNCTION(4, "MD32_0_JTAG_TRST"), + MTK_FUNCTION(7, "DBG_MON_A26") + ), + MTK_PIN( + 135, "GPIO135", + MTK_EINT_FUNCTION(0, 135), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO135"), + MTK_FUNCTION(1, "PWM_0"), + MTK_FUNCTION(2, "SRCLKENAI1"), + MTK_FUNCTION(3, "MD_URXD0"), + MTK_FUNCTION(4, "MD32_0_RXD"), + MTK_FUNCTION(5, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_A29") + ), + MTK_PIN( + 136, "GPIO136", + MTK_EINT_FUNCTION(0, 136), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO136"), + MTK_FUNCTION(1, "CMMCLK3"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD_UTXD0"), + MTK_FUNCTION(4, "MD32_0_TXD"), + MTK_FUNCTION(6, "SPI5_B_MI"), + MTK_FUNCTION(7, "DBG_MON_A24") + ), + MTK_PIN( + 137, "GPIO137", + MTK_EINT_FUNCTION(0, 137), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO137"), + MTK_FUNCTION(1, "CMMCLK4"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD_URXD1"), + MTK_FUNCTION(6, "CONN_UART0_RXD"), + MTK_FUNCTION(7, "DBG_MON_A27") + ), + MTK_PIN( + 138, "GPIO138", + MTK_EINT_FUNCTION(0, 138), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO138"), + MTK_FUNCTION(1, "CMMCLK5"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "MD_UTXD1"), + MTK_FUNCTION(6, "CONN_UART0_TXD"), + MTK_FUNCTION(7, "DBG_MON_A30") + ), + MTK_PIN( + 139, "GPIO139", + MTK_EINT_FUNCTION(0, 139), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO139"), + MTK_FUNCTION(1, "SCL4"), + MTK_FUNCTION(7, "DBG_MON_A21") + ), + MTK_PIN( + 140, "GPIO140", + MTK_EINT_FUNCTION(0, 140), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO140"), + MTK_FUNCTION(1, "SDA4"), + MTK_FUNCTION(7, "DBG_MON_A20") + ), + MTK_PIN( + 141, "GPIO141", + MTK_EINT_FUNCTION(0, 141), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO141"), + MTK_FUNCTION(1, "SCL2"), + MTK_FUNCTION(7, "DBG_MON_A18") + ), + MTK_PIN( + 142, "GPIO142", + MTK_EINT_FUNCTION(0, 142), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO142"), + MTK_FUNCTION(1, "SDA2"), + MTK_FUNCTION(7, "DBG_MON_A19") + ), + MTK_PIN( + 143, "GPIO143", + MTK_EINT_FUNCTION(0, 143), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO143"), + MTK_FUNCTION(1, "CMVREF0"), + MTK_FUNCTION(2, "SPI3_CLK"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDO"), + MTK_FUNCTION(4, "SCP_JTAG1_TDO"), + MTK_FUNCTION(7, "DBG_MON_A31") + ), + MTK_PIN( + 144, "GPIO144", + MTK_EINT_FUNCTION(0, 144), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO144"), + MTK_FUNCTION(1, "CMVREF1"), + MTK_FUNCTION(2, "SPI3_CSB"), + MTK_FUNCTION(3, "ADSP_JTAG1_TDI"), + MTK_FUNCTION(4, "SCP_JTAG1_TDI") + ), + MTK_PIN( + 145, "GPIO145", + MTK_EINT_FUNCTION(0, 145), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO145"), + MTK_FUNCTION(1, "CMVREF2"), + MTK_FUNCTION(2, "SPI3_MI"), + MTK_FUNCTION(3, "ADSP_JTAG1_TMS"), + MTK_FUNCTION(4, "SCP_JTAG1_TMS") + ), + MTK_PIN( + 146, "GPIO146", + MTK_EINT_FUNCTION(0, 146), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO146"), + MTK_FUNCTION(1, "CMVREF3"), + MTK_FUNCTION(2, "SPI3_MO"), + MTK_FUNCTION(3, "ADSP_JTAG1_TCK"), + MTK_FUNCTION(4, "SCP_JTAG1_TCK"), + MTK_FUNCTION(7, "DBG_MON_A32") + ), + MTK_PIN( + 147, "GPIO147", + MTK_EINT_FUNCTION(0, 147), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO147"), + MTK_FUNCTION(1, "CMVREF4"), + MTK_FUNCTION(2, "EXT_FRAME_SYNC"), + MTK_FUNCTION(3, "ADSP_JTAG1_TRSTN"), + MTK_FUNCTION(4, "SCP_JTAG1_TRSTN") + ), + MTK_PIN( + 148, "GPIO148", + MTK_EINT_FUNCTION(0, 148), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO148"), + MTK_FUNCTION(1, "PWM_1"), + MTK_FUNCTION(2, "AGPS_SYNC"), + MTK_FUNCTION(3, "CMMCLK5") + ), + MTK_PIN( + 149, "GPIO149", + MTK_EINT_FUNCTION(0, 149), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO149"), + MTK_FUNCTION(1, "CMMCLK0"), + MTK_FUNCTION(2, "CLKM0"), + MTK_FUNCTION(3, "MD32_0_GPIO0") + ), + MTK_PIN( + 150, "GPIO150", + MTK_EINT_FUNCTION(0, 150), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO150"), + MTK_FUNCTION(1, "CMMCLK1"), + MTK_FUNCTION(2, "CLKM1"), + MTK_FUNCTION(3, "MD32_0_GPIO1"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TMSC") + ), + MTK_PIN( + 151, "GPIO151", + MTK_EINT_FUNCTION(0, 151), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO151"), + MTK_FUNCTION(1, "CMMCLK2"), + MTK_FUNCTION(2, "CLKM2"), + MTK_FUNCTION(3, "MD32_0_GPIO2"), + MTK_FUNCTION(7, "CONN_MCU_AICE_TCKC") + ), + MTK_PIN( + 152, "GPIO152", + MTK_EINT_FUNCTION(0, 152), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO152"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "PWM_2"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(6, "MBISTREADEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B9") + ), + MTK_PIN( + 153, "GPIO153", + MTK_EINT_FUNCTION(0, 153), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO153"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(7, "DBG_MON_B8") + ), + MTK_PIN( + 154, "GPIO154", + MTK_EINT_FUNCTION(0, 154), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO154"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_B6") + ), + MTK_PIN( + 155, "GPIO155", + MTK_EINT_FUNCTION(0, 155), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO155"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "PWM_3"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(6, "MBISTWRITEEN_TRIGGER"), + MTK_FUNCTION(7, "DBG_MON_B7") + ), + MTK_PIN( + 156, "GPIO156", + MTK_EINT_FUNCTION(0, 156), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO156"), + MTK_FUNCTION(1, "SPI1_A_CLK"), + MTK_FUNCTION(2, "SCP_SPI1_A_CK"), + MTK_FUNCTION(3, "MRG_CLK"), + MTK_FUNCTION(4, "AGPS_SYNC"), + MTK_FUNCTION(5, "MD_URXD0"), + MTK_FUNCTION(6, "UDI_TMS"), + MTK_FUNCTION(7, "DBG_MON_B10") + ), + MTK_PIN( + 157, "GPIO157", + MTK_EINT_FUNCTION(0, 157), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO157"), + MTK_FUNCTION(1, "SPI1_A_CSB"), + MTK_FUNCTION(2, "SCP_SPI1_A_CS"), + MTK_FUNCTION(3, "MRG_SYNC"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "MD_UTXD0"), + MTK_FUNCTION(6, "UDI_TCK"), + MTK_FUNCTION(7, "DBG_MON_B11") + ), + MTK_PIN( + 158, "GPIO158", + MTK_EINT_FUNCTION(0, 158), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO158"), + MTK_FUNCTION(1, "SPI1_A_MI"), + MTK_FUNCTION(2, "SCP_SPI1_A_MI"), + MTK_FUNCTION(3, "MRG_DI"), + MTK_FUNCTION(4, "PTA_RXD"), + MTK_FUNCTION(5, "MD_URXD1"), + MTK_FUNCTION(6, "UDI_TDO"), + MTK_FUNCTION(7, "DBG_MON_B12") + ), + MTK_PIN( + 159, "GPIO159", + MTK_EINT_FUNCTION(0, 159), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO159"), + MTK_FUNCTION(1, "SPI1_A_MO"), + MTK_FUNCTION(2, "SCP_SPI1_A_MO"), + MTK_FUNCTION(3, "MRG_DO"), + MTK_FUNCTION(4, "PTA_TXD"), + MTK_FUNCTION(5, "MD_UTXD1"), + MTK_FUNCTION(6, "UDI_NTRST"), + MTK_FUNCTION(7, "DBG_MON_B13") + ), + MTK_PIN( + 160, "GPIO160", + MTK_EINT_FUNCTION(0, 160), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO160"), + MTK_FUNCTION(1, "SCL3"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(7, "DBG_MON_B14") + ), + MTK_PIN( + 161, "GPIO161", + MTK_EINT_FUNCTION(0, 161), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO161"), + MTK_FUNCTION(1, "SDA3"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(7, "DBG_MON_B15") + ), + MTK_PIN( + 162, "GPIO162", + MTK_EINT_FUNCTION(0, 162), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO162"), + MTK_FUNCTION(1, "ANT_SEL0"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(6, "UDI_TDI"), + MTK_FUNCTION(7, "DBG_MON_B16") + ), + MTK_PIN( + 163, "GPIO163", + MTK_EINT_FUNCTION(0, 163), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO163"), + MTK_FUNCTION(1, "ANT_SEL1"), + MTK_FUNCTION(2, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(7, "DBG_MON_B17") + ), + MTK_PIN( + 164, "GPIO164", + MTK_EINT_FUNCTION(0, 164), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO164"), + MTK_FUNCTION(1, "ANT_SEL2"), + MTK_FUNCTION(2, "SCP_SPI1_B_CK"), + MTK_FUNCTION(3, "TP_URXD1_AO"), + MTK_FUNCTION(5, "UCTS0"), + MTK_FUNCTION(7, "DBG_MON_B18") + ), + MTK_PIN( + 165, "GPIO165", + MTK_EINT_FUNCTION(0, 165), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO165"), + MTK_FUNCTION(1, "ANT_SEL3"), + MTK_FUNCTION(2, "SCP_SPI1_B_CS"), + MTK_FUNCTION(3, "TP_UTXD1_AO"), + MTK_FUNCTION(4, "CONN_TCXOENA_REQ"), + MTK_FUNCTION(5, "URTS0"), + MTK_FUNCTION(7, "DBG_MON_B19") + ), + MTK_PIN( + 166, "GPIO166", + MTK_EINT_FUNCTION(0, 166), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO166"), + MTK_FUNCTION(1, "ANT_SEL4"), + MTK_FUNCTION(2, "SCP_SPI1_B_MI"), + MTK_FUNCTION(3, "TP_URXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B20") + ), + MTK_PIN( + 167, "GPIO167", + MTK_EINT_FUNCTION(0, 167), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO167"), + MTK_FUNCTION(1, "ANT_SEL5"), + MTK_FUNCTION(2, "SCP_SPI1_B_MO"), + MTK_FUNCTION(3, "TP_UTXD2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "URTS1"), + MTK_FUNCTION(7, "DBG_MON_B21") + ), + MTK_PIN( + 168, "GPIO168", + MTK_EINT_FUNCTION(0, 168), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO168"), + MTK_FUNCTION(1, "ANT_SEL6"), + MTK_FUNCTION(2, "SPI0_B_CLK"), + MTK_FUNCTION(3, "TP_UCTS1_AO"), + MTK_FUNCTION(4, "KPCOL2"), + MTK_FUNCTION(5, "MD_UCTS0"), + MTK_FUNCTION(6, "SCL11"), + MTK_FUNCTION(7, "DBG_MON_B22") + ), + MTK_PIN( + 169, "GPIO169", + MTK_EINT_FUNCTION(0, 169), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO169"), + MTK_FUNCTION(1, "ANT_SEL7"), + MTK_FUNCTION(2, "SPI0_B_CSB"), + MTK_FUNCTION(3, "TP_URTS1_AO"), + MTK_FUNCTION(4, "KPROW2"), + MTK_FUNCTION(5, "MD_URTS0"), + MTK_FUNCTION(6, "SDA11"), + MTK_FUNCTION(7, "DBG_MON_B23") + ), + MTK_PIN( + 170, "GPIO170", + MTK_EINT_FUNCTION(0, 170), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO170"), + MTK_FUNCTION(1, "ANT_SEL8"), + MTK_FUNCTION(2, "SPI0_B_MI"), + MTK_FUNCTION(3, "TP_UCTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI1"), + MTK_FUNCTION(5, "MD_UCTS1"), + MTK_FUNCTION(7, "DBG_MON_B24") + ), + MTK_PIN( + 171, "GPIO171", + MTK_EINT_FUNCTION(0, 171), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO171"), + MTK_FUNCTION(1, "ANT_SEL9"), + MTK_FUNCTION(2, "SPI0_B_MO"), + MTK_FUNCTION(3, "TP_URTS2_AO"), + MTK_FUNCTION(4, "SRCLKENAI0"), + MTK_FUNCTION(5, "MD_URTS1"), + MTK_FUNCTION(7, "DBG_MON_B25") + ), + MTK_PIN( + 172, "GPIO172", + MTK_EINT_FUNCTION(0, 172), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO172"), + MTK_FUNCTION(1, "CONN_TOP_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK0"), + MTK_FUNCTION(7, "DBG_MON_B29") + ), + MTK_PIN( + 173, "GPIO173", + MTK_EINT_FUNCTION(0, 173), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO173"), + MTK_FUNCTION(1, "CONN_TOP_DATA"), + MTK_FUNCTION(2, "AUXIF_ST0"), + MTK_FUNCTION(7, "DBG_MON_B30") + ), + MTK_PIN( + 174, "GPIO174", + MTK_EINT_FUNCTION(0, 174), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO174"), + MTK_FUNCTION(1, "CONN_HRST_B"), + MTK_FUNCTION(7, "DBG_MON_B28") + ), + MTK_PIN( + 175, "GPIO175", + MTK_EINT_FUNCTION(0, 175), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO175"), + MTK_FUNCTION(1, "CONN_WB_PTA"), + MTK_FUNCTION(7, "DBG_MON_B31") + ), + MTK_PIN( + 176, "GPIO176", + MTK_EINT_FUNCTION(0, 176), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO176"), + MTK_FUNCTION(1, "CONN_BT_CLK"), + MTK_FUNCTION(2, "AUXIF_CLK1"), + MTK_FUNCTION(7, "DBG_MON_B26") + ), + MTK_PIN( + 177, "GPIO177", + MTK_EINT_FUNCTION(0, 177), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO177"), + MTK_FUNCTION(1, "CONN_BT_DATA"), + MTK_FUNCTION(2, "AUXIF_ST1"), + MTK_FUNCTION(7, "DBG_MON_B27") + ), + MTK_PIN( + 178, "GPIO178", + MTK_EINT_FUNCTION(0, 178), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO178"), + MTK_FUNCTION(1, "CONN_WF_CTRL0") + ), + MTK_PIN( + 179, "GPIO179", + MTK_EINT_FUNCTION(0, 179), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO179"), + MTK_FUNCTION(1, "CONN_WF_CTRL1"), + MTK_FUNCTION(2, "UFS_MPHY_SCL") + ), + MTK_PIN( + 180, "GPIO180", + MTK_EINT_FUNCTION(0, 180), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO180"), + MTK_FUNCTION(1, "CONN_WF_CTRL2"), + MTK_FUNCTION(2, "UFS_MPHY_SDA") + ), + MTK_PIN( + 181, "GPIO181", + MTK_EINT_FUNCTION(0, 181), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO181"), + MTK_FUNCTION(1, "CONN_WF_CTRL3") + ), + MTK_PIN( + 182, "GPIO182", + MTK_EINT_FUNCTION(0, 182), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO182"), + MTK_FUNCTION(1, "CONN_WF_CTRL4") + ), + MTK_PIN( + 183, "GPIO183", + MTK_EINT_FUNCTION(0, 183), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO183"), + MTK_FUNCTION(1, "MSDC0_CMD") + ), + MTK_PIN( + 184, "GPIO184", + MTK_EINT_FUNCTION(0, 184), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO184"), + MTK_FUNCTION(1, "MSDC0_DAT0") + ), + MTK_PIN( + 185, "GPIO185", + MTK_EINT_FUNCTION(0, 185), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO185"), + MTK_FUNCTION(1, "MSDC0_DAT2") + ), + MTK_PIN( + 186, "GPIO186", + MTK_EINT_FUNCTION(0, 186), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO186"), + MTK_FUNCTION(1, "MSDC0_DAT4") + ), + MTK_PIN( + 187, "GPIO187", + MTK_EINT_FUNCTION(0, 187), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO187"), + MTK_FUNCTION(1, "MSDC0_DAT6") + ), + MTK_PIN( + 188, "GPIO188", + MTK_EINT_FUNCTION(0, 188), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO188"), + MTK_FUNCTION(1, "MSDC0_DAT1") + ), + MTK_PIN( + 189, "GPIO189", + MTK_EINT_FUNCTION(0, 189), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO189"), + MTK_FUNCTION(1, "MSDC0_DAT5") + ), + MTK_PIN( + 190, "GPIO190", + MTK_EINT_FUNCTION(0, 190), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO190"), + MTK_FUNCTION(1, "MSDC0_DAT7") + ), + MTK_PIN( + 191, "GPIO191", + MTK_EINT_FUNCTION(0, 191), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO191"), + MTK_FUNCTION(1, "MSDC0_DSL"), + MTK_FUNCTION(2, "GPS_L1_ELNA_EN"), + MTK_FUNCTION(3, "IDDIG"), + MTK_FUNCTION(4, "DMIC_CLK") + ), + MTK_PIN( + 192, "GPIO192", + MTK_EINT_FUNCTION(0, 192), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO192"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(3, "USB_DRVVBUS"), + MTK_FUNCTION(4, "DMIC_DAT") + ), + MTK_PIN( + 193, "GPIO193", + MTK_EINT_FUNCTION(0, 193), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO193"), + MTK_FUNCTION(1, "MSDC0_DAT3") + ), + MTK_PIN( + 194, "GPIO194", + MTK_EINT_FUNCTION(0, 194), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO194"), + MTK_FUNCTION(1, "MSDC0_RSTB") + ), + MTK_PIN( + 195, "GPIO195", + MTK_EINT_FUNCTION(0, 195), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO195"), + MTK_FUNCTION(1, "SCP_VREQ_VAO"), + MTK_FUNCTION(2, "DVFSRC_EXT_REQ") + ), + MTK_PIN( + 196, "GPIO196", + MTK_EINT_FUNCTION(0, 196), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO196"), + MTK_FUNCTION(1, "AUD_DAT_MOSI2") + ), + MTK_PIN( + 197, "GPIO197", + MTK_EINT_FUNCTION(0, 197), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO197"), + MTK_FUNCTION(1, "AUD_NLE_MOSI1"), + MTK_FUNCTION(2, "AUD_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_MCK"), + MTK_FUNCTION(4, "I2S6_MCK"), + MTK_FUNCTION(5, "I2S8_MCK") + ), + MTK_PIN( + 198, "GPIO198", + MTK_EINT_FUNCTION(0, 198), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO198"), + MTK_FUNCTION(1, "AUD_NLE_MOSI0"), + MTK_FUNCTION(2, "AUD_SYNC_MISO"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "I2S6_BCK"), + MTK_FUNCTION(5, "I2S8_BCK") + ), + MTK_PIN( + 199, "GPIO199", + MTK_EINT_FUNCTION(0, 199), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO199"), + MTK_FUNCTION(1, "AUD_DAT_MISO2"), + MTK_FUNCTION(3, "I2S2_DI2") + ), + MTK_PIN( + 200, "GPIO200", + MTK_EINT_FUNCTION(0, 200), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO200"), + MTK_FUNCTION(1, "SCL6"), + MTK_FUNCTION(3, "SCP_SCL1"), + MTK_FUNCTION(4, "SCL_6306"), + MTK_FUNCTION(7, "DBG_MON_A4") + ), + MTK_PIN( + 201, "GPIO201", + MTK_EINT_FUNCTION(0, 201), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO201"), + MTK_FUNCTION(1, "SDA6"), + MTK_FUNCTION(3, "SCP_SDA1"), + MTK_FUNCTION(4, "SDA_6306"), + MTK_FUNCTION(7, "DBG_MON_A5") + ), + MTK_PIN( + 202, "GPIO202", + MTK_EINT_FUNCTION(0, 202), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO202"), + MTK_FUNCTION(1, "SCL5") + ), + MTK_PIN( + 203, "GPIO203", + MTK_EINT_FUNCTION(0, 203), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO203"), + MTK_FUNCTION(1, "SDA5") + ), + MTK_PIN( + 204, "GPIO204", + MTK_EINT_FUNCTION(0, 204), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO204"), + MTK_FUNCTION(1, "SCL0"), + MTK_FUNCTION(6, "SPI7_A_CLK"), + MTK_FUNCTION(7, "DBG_MON_A2") + ), + MTK_PIN( + 205, "GPIO205", + MTK_EINT_FUNCTION(0, 205), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO205"), + MTK_FUNCTION(1, "SDA0"), + MTK_FUNCTION(6, "SPI7_A_CSB"), + MTK_FUNCTION(7, "DBG_MON_A3") + ), + MTK_PIN( + 206, "GPIO206", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO206"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + 207, "GPIO207", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO207"), + MTK_FUNCTION(1, "SRCLKENA1") + ), + MTK_PIN( + 208, "GPIO208", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO208"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + 209, "GPIO209", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO209"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + 210, "GPIO210", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO210"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + 211, "GPIO211", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO211"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + 212, "GPIO212", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO212"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + 213, "GPIO213", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO213"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + 214, "GPIO214", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO214"), + MTK_FUNCTION(1, "AUD_CLK_MOSI"), + MTK_FUNCTION(3, "I2S1_MCK"), + MTK_FUNCTION(4, "I2S7_MCK"), + MTK_FUNCTION(5, "I2S9_MCK") + ), + MTK_PIN( + 215, "GPIO215", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO215"), + MTK_FUNCTION(1, "AUD_SYNC_MOSI"), + MTK_FUNCTION(3, "I2S1_BCK"), + MTK_FUNCTION(4, "I2S7_BCK"), + MTK_FUNCTION(5, "I2S9_BCK") + ), + MTK_PIN( + 216, "GPIO216", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO216"), + MTK_FUNCTION(1, "AUD_DAT_MOSI0"), + MTK_FUNCTION(3, "I2S1_LRCK"), + MTK_FUNCTION(4, "I2S7_LRCK"), + MTK_FUNCTION(5, "I2S9_LRCK") + ), + MTK_PIN( + 217, "GPIO217", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO217"), + MTK_FUNCTION(1, "AUD_DAT_MOSI1"), + MTK_FUNCTION(3, "I2S1_DO"), + MTK_FUNCTION(4, "I2S7_DO"), + MTK_FUNCTION(5, "I2S9_DO") + ), + MTK_PIN( + 218, "GPIO218", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO218"), + MTK_FUNCTION(1, "AUD_DAT_MISO0"), + MTK_FUNCTION(2, "VOW_DAT_MISO"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "I2S6_LRCK"), + MTK_FUNCTION(5, "I2S8_LRCK") + ), + MTK_PIN( + 219, "GPIO219", + MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO219"), + MTK_FUNCTION(1, "AUD_DAT_MISO1"), + MTK_FUNCTION(2, "VOW_CLK_MISO"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "I2S6_DI"), + MTK_FUNCTION(5, "I2S8_DI") + ), + MTK_PIN( + 220, "GPIO220", + MTK_EINT_FUNCTION(0, 208), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO220") + ), + MTK_PIN( + 221, "GPIO221", + MTK_EINT_FUNCTION(0, 209), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO221") + ), + MTK_PIN( + 222, "GPIO222", + MTK_EINT_FUNCTION(0, 210), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO222") + ), + MTK_PIN( + 223, "GPIO223", + MTK_EINT_FUNCTION(0, 211), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO223") + ), + MTK_PIN( + 224, "GPIO224", + MTK_EINT_FUNCTION(0, 212), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO224") + ), + MTK_PIN( + 225, "GPIO225", + MTK_EINT_FUNCTION(0, 214), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO225") + ), + MTK_PIN( + 226, "GPIO226", + MTK_EINT_FUNCTION(0, 215), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO226") + ), + MTK_PIN( + 227, "GPIO227", + MTK_EINT_FUNCTION(0, 216), + DRV_GRP4, + MTK_FUNCTION(0, "GPIO227") + ), +}; + +#endif /* __PINCTRL_MTK_MT8192_H */ From ebc2599144b610a7e6e967ee89a769d908a3eeef Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Fri, 28 Aug 2020 13:32:35 +0300 Subject: [PATCH 20/78] pinctrl: mcp23s08: Improve error messaging in ->probe() Print particular message in each of error case in the ->probe(). While here, use dev_err_probe() for that. Signed-off-by: Andy Shevchenko Cc: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200828103235.78380-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 42b12ea14d6b..b4606811cf57 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -564,7 +564,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = mcp_read(mcp, MCP_IOCON, &status); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't identify chip %d\n", addr); mcp->irq_controller = device_property_read_bool(dev, "interrupt-controller"); @@ -598,7 +598,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = mcp_write(mcp, MCP_IOCON, status); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't write IOCON %d\n", addr); } if (mcp->irq && mcp->irq_controller) { @@ -616,7 +616,7 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp); if (ret < 0) - goto fail; + return dev_err_probe(dev, ret, "can't add GPIO chip\n"); mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; @@ -628,18 +628,17 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->pinctrl_desc.owner = THIS_MODULE; mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp); - if (IS_ERR(mcp->pctldev)) { - ret = PTR_ERR(mcp->pctldev); - goto fail; + if (IS_ERR(mcp->pctldev)) + return dev_err_probe(dev, PTR_ERR(mcp->pctldev), "can't register controller\n"); + + if (mcp->irq) { + ret = mcp23s08_irq_setup(mcp); + if (ret) + return dev_err_probe(dev, ret, "can't setup IRQ\n"); } - if (mcp->irq) - ret = mcp23s08_irq_setup(mcp); - -fail: - if (ret < 0) - dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); - return ret; + return 0; } EXPORT_SYMBOL_GPL(mcp23s08_probe_one); + MODULE_LICENSE("GPL"); From bbf369d4e59a248ed715041267951f5cd051b317 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Aug 2020 10:54:48 +0100 Subject: [PATCH 21/78] pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functions Add pins, groups and functions for the CAN{0,1} interface. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200825095448.13093-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 ++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 39ba1e7cc1c3..60f973c5dffe 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -1871,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; +/* - CAN0 ----------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { + /* CAN0 RX */ + RCAR_GP_PIN(1, 17), + /* CAN0 TX */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int can0_data_mux[] = { + CAN0_RX_MARK, + CAN0_TX_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* CAN0 RXB */ + RCAR_GP_PIN(4, 5), + /* CAN0 TXB */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_RX_B_MARK, + CAN0_TX_B_MARK, +}; +static const unsigned int can0_data_c_pins[] = { + /* CAN0 RXC */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXC */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int can0_data_c_mux[] = { + CAN0_RX_C_MARK, + CAN0_TX_C_MARK, +}; +static const unsigned int can0_data_d_pins[] = { + /* CAN0 RXD */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXD */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int can0_data_d_mux[] = { + CAN0_RX_D_MARK, + CAN0_TX_D_MARK, +}; +/* - CAN1 ----------------------------------------------------------------- */ +static const unsigned int can1_data_pins[] = { + /* CAN1 RX */ + RCAR_GP_PIN(1, 22), + /* CAN1 TX */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int can1_data_mux[] = { + CAN1_RX_MARK, + CAN1_TX_MARK, +}; +static const unsigned int can1_data_b_pins[] = { + /* CAN1 RXB */ + RCAR_GP_PIN(4, 7), + /* CAN1 TXB */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int can1_data_b_mux[] = { + CAN1_RX_B_MARK, + CAN1_TX_B_MARK, +}; +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 21), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +static const unsigned int can_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(4, 3), +}; + +static const unsigned int can_clk_b_mux[] = { + CAN_CLK_B_MARK, +}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3946,7 +4026,7 @@ static const unsigned int vin3_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[290]; + struct sh_pfc_pin_group common[298]; struct sh_pfc_pin_group automotive[1]; } pinmux_groups = { .common = { @@ -3963,6 +4043,14 @@ static const struct { SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4265,6 +4353,23 @@ static const char * const avb_groups[] = { "avb_gmii", }; +static const char * const can0_groups[] = { + "can0_data", + "can0_data_b", + "can0_data_c", + "can0_data_d", +}; + +static const char * const can1_groups[] = { + "can1_data", + "can1_data_b", +}; + +static const char * const can_clk_groups[] = { + "can_clk", + "can_clk_b", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4706,13 +4811,16 @@ static const char * const vin3_groups[] = { }; static const struct { - struct sh_pfc_function common[55]; + struct sh_pfc_function common[58]; struct sh_pfc_function automotive[1]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), From a0bf06dc51dbbc5ad182b1bcf4d879db8d297c5e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 4 Sep 2020 19:21:41 +0200 Subject: [PATCH 22/78] pinctrl: cherryview: Preserve CHV_PADCTRL1_INVRXTX_TXDATA flag on GPIOs One some devices the GPIO should output the inverted value from what device-drivers / ACPI code expects. The reason for this is unknown, perhaps these systems use an external buffer chip on the GPIO which inverts the signal. The BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag. Before this commit we would unconditionally clear all INVRXTX flags, including the CHV_PADCTRL1_INVRXTX_TXDATA flag when a GPIO is requested by a driver (from chv_gpio_request_enable()). This breaks systems using this setup. Specifically it is causing problems for systems with a goodix touchscreen, where the BIOS sets the INVRXTX_TXDATA flag on the GPIO used for the touchscreen's reset pin. The goodix touchscreen driver by defaults configures this pin as input (relying on the pull-up to keep it high), but the clearing of the INVRXTX_TXDATA flag done by chv_gpio_request_enable() causes it to be driven low for a brief time before the GPIO gets set to input mode. This causes the touchscreen controller to get reset. On most CHT devs with this touchscreen this leads to: [ 31.596534] Goodix-TS i2c-GDIX1001:00: i2c test failed attempt 1: -121 The driver retries this though and then everything is fine. But during reset the touchscreen uses its interrupt pin as bootstrap to determine which i2c address to use and on the Acer One S1003 the spurious reset caused by the clearing of the INVRXTX_TXDATA flag causes the controller to come back up again on the wrong i2c address, breaking things. This commit fixes both the -121 errors, as well as the total breakage on the Acer One S1003, by making chv_gpio_clear_triggering() not clear the INVRXTX_TXDATA flag if the pin is already configured as a GPIO. Note that chv_pinmux_set_mux() does still unconditionally clear the flag, so this only affects GPIO usage. Fixes: a7d4b171660c ("Input: goodix - add support for getting IRQ + reset GPIOs on Cherry Trail devices") Signed-off-by: Hans de Goede Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index e48d4445e932..2ed17cdf946d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -58,6 +58,7 @@ #define CHV_PADCTRL1_CFGLOCK BIT(31) #define CHV_PADCTRL1_INVRXTX_SHIFT 4 #define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) +#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) #define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) #define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) #define CHV_PADCTRL1_ODEN BIT(3) @@ -768,11 +769,22 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, unsigned int offset) { + u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; u32 value; + /* + * One some devices the GPIO should output the inverted value from what + * device-drivers / ACPI code expects (inverted external buffer?). The + * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, + * preserve this flag if the pin is already setup as GPIO. + */ + value = chv_readl(pctrl, offset, CHV_PADCTRL0); + if (value & CHV_PADCTRL0_GPIOEN) + invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; + value = chv_readl(pctrl, offset, CHV_PADCTRL1); value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; - value &= ~CHV_PADCTRL1_INVRXTX_MASK; + value &= ~invrxtx_mask; chv_writel(pctrl, offset, CHV_PADCTRL1, value); } From b445f6237744df5e8d4f56f8733b2108c611220a Mon Sep 17 00:00:00 2001 From: Thomas Preston Date: Fri, 28 Aug 2020 22:32:25 +0100 Subject: [PATCH 23/78] pinctrl: mcp23s08: Fix mcp23x17_regmap initialiser The mcp23x17_regmap is initialised with structs named "mcp23x16". However, the mcp23s08 driver doesn't support the MCP23016 device yet, so this appears to be a typo. Fixes: 8f38910ba4f6 ("pinctrl: mcp23s08: switch to regmap caching") Signed-off-by: Thomas Preston Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200828213226.1734264-2-thomas.preston@codethink.co.uk Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index b4606811cf57..3f5fed28557b 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -87,7 +87,7 @@ const struct regmap_config mcp23x08_regmap = { }; EXPORT_SYMBOL_GPL(mcp23x08_regmap); -static const struct reg_default mcp23x16_defaults[] = { +static const struct reg_default mcp23x17_defaults[] = { {.reg = MCP_IODIR << 1, .def = 0xffff}, {.reg = MCP_IPOL << 1, .def = 0x0000}, {.reg = MCP_GPINTEN << 1, .def = 0x0000}, @@ -98,23 +98,23 @@ static const struct reg_default mcp23x16_defaults[] = { {.reg = MCP_OLAT << 1, .def = 0x0000}, }; -static const struct regmap_range mcp23x16_volatile_range = { +static const struct regmap_range mcp23x17_volatile_range = { .range_min = MCP_INTF << 1, .range_max = MCP_GPIO << 1, }; -static const struct regmap_access_table mcp23x16_volatile_table = { - .yes_ranges = &mcp23x16_volatile_range, +static const struct regmap_access_table mcp23x17_volatile_table = { + .yes_ranges = &mcp23x17_volatile_range, .n_yes_ranges = 1, }; -static const struct regmap_range mcp23x16_precious_range = { +static const struct regmap_range mcp23x17_precious_range = { .range_min = MCP_GPIO << 1, .range_max = MCP_GPIO << 1, }; -static const struct regmap_access_table mcp23x16_precious_table = { - .yes_ranges = &mcp23x16_precious_range, +static const struct regmap_access_table mcp23x17_precious_table = { + .yes_ranges = &mcp23x17_precious_range, .n_yes_ranges = 1, }; @@ -124,10 +124,10 @@ const struct regmap_config mcp23x17_regmap = { .reg_stride = 2, .max_register = MCP_OLAT << 1, - .volatile_table = &mcp23x16_volatile_table, - .precious_table = &mcp23x16_precious_table, - .reg_defaults = mcp23x16_defaults, - .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults), + .volatile_table = &mcp23x17_volatile_table, + .precious_table = &mcp23x17_precious_table, + .reg_defaults = mcp23x17_defaults, + .num_reg_defaults = ARRAY_SIZE(mcp23x17_defaults), .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; From b9b7fb29433b906635231d0a111224efa009198c Mon Sep 17 00:00:00 2001 From: Thomas Preston Date: Fri, 28 Aug 2020 22:32:26 +0100 Subject: [PATCH 24/78] pinctrl: mcp23s08: Fix mcp23x17 precious range On page 23 of the datasheet [0] it says "The register remains unchanged until the interrupt is cleared via a read of INTCAP or GPIO." Include INTCAPA and INTCAPB registers in precious range, so that they aren't accidentally cleared when we read via debugfs. [0] https://ww1.microchip.com/downloads/en/DeviceDoc/20001952C.pdf Fixes: 8f38910ba4f6 ("pinctrl: mcp23s08: switch to regmap caching") Signed-off-by: Thomas Preston Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200828213226.1734264-3-thomas.preston@codethink.co.uk Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 3f5fed28557b..ce2d8014b7e0 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -109,7 +109,7 @@ static const struct regmap_access_table mcp23x17_volatile_table = { }; static const struct regmap_range mcp23x17_precious_range = { - .range_min = MCP_GPIO << 1, + .range_min = MCP_INTCAP << 1, .range_max = MCP_GPIO << 1, }; From 8e2f830acaa4a05087bc637fff4434de50057c11 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 31 Aug 2020 00:43:09 +0200 Subject: [PATCH 25/78] pinctrl: actions: pinctrl-owl: Constify owl_pinctrl_ops and owl_pinmux_ops The only usage of owl_pinctrl_ops and owl_pinmux_ops is to assign their addresses to the pctlops and the pmxops fields in the pinctrl_desc struct, which are const pointers. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200830224311.36994-2-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-owl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/actions/pinctrl-owl.c b/drivers/pinctrl/actions/pinctrl-owl.c index 7efdfb4f3e9b..903a4baf3846 100644 --- a/drivers/pinctrl/actions/pinctrl-owl.c +++ b/drivers/pinctrl/actions/pinctrl-owl.c @@ -125,7 +125,7 @@ static void owl_pin_dbg_show(struct pinctrl_dev *pctrldev, seq_printf(s, "%s", dev_name(pctrl->dev)); } -static struct pinctrl_ops owl_pinctrl_ops = { +static const struct pinctrl_ops owl_pinctrl_ops = { .get_groups_count = owl_get_groups_count, .get_group_name = owl_get_group_name, .get_group_pins = owl_get_group_pins, @@ -212,7 +212,7 @@ static int owl_set_mux(struct pinctrl_dev *pctrldev, return 0; } -static struct pinmux_ops owl_pinmux_ops = { +static const struct pinmux_ops owl_pinmux_ops = { .get_functions_count = owl_get_funcs_count, .get_function_name = owl_get_func_name, .get_function_groups = owl_get_func_groups, From d01afb7115b190a594441d152a5dd364b9e0d602 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 31 Aug 2020 00:43:10 +0200 Subject: [PATCH 26/78] pinctrl: actions: pinctrl-s700: Constify s700_padinfo[] The only usage of s700_padinfo[] is to assign it to the padinfo field in the owl_pinctrl_soc_data struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200830224311.36994-3-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-s700.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/actions/pinctrl-s700.c b/drivers/pinctrl/actions/pinctrl-s700.c index f579a6593f37..fd00940a5799 100644 --- a/drivers/pinctrl/actions/pinctrl-s700.c +++ b/drivers/pinctrl/actions/pinctrl-s700.c @@ -1685,7 +1685,7 @@ static PAD_PULLCTL_CONF(I2C2_SDATA, 2, 8, 1); static PAD_PULLCTL_CONF(I2C2_SCLK, 2, 7, 1); /* Pad info table for the pinmux subsystem */ -static struct owl_padinfo s700_padinfo[NUM_PADS] = { +static const struct owl_padinfo s700_padinfo[NUM_PADS] = { [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), From 8a643cc8d56d12e56cdd08139566a28b6150b231 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Mon, 31 Aug 2020 00:43:11 +0200 Subject: [PATCH 27/78] pinctrl: actions: pinctrl-s900: Constify s900_padinfo[] The only usage of s900_padinfo[] is to assign it to the padinfo field in the owl_pinctrl_soc_data struct, which is a const pointer. Make it const to allow the compiler to put it in read-only memory. Signed-off-by: Rikard Falkeborn Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200830224311.36994-4-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/actions/pinctrl-s900.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/actions/pinctrl-s900.c b/drivers/pinctrl/actions/pinctrl-s900.c index 9492b86852e7..811249a8011e 100644 --- a/drivers/pinctrl/actions/pinctrl-s900.c +++ b/drivers/pinctrl/actions/pinctrl-s900.c @@ -1556,7 +1556,7 @@ static PAD_ST_CONF(I2S_BCLK0, 1, 1, 1); static PAD_ST_CONF(I2S_MCLK0, 1, 0, 1); /* Pad info table */ -static struct owl_padinfo s900_padinfo[NUM_PADS] = { +static const struct owl_padinfo s900_padinfo[NUM_PADS] = { [ETH_TXD0] = PAD_INFO_ST(ETH_TXD0), [ETH_TXD1] = PAD_INFO_ST(ETH_TXD1), [ETH_TXEN] = PAD_INFO_ST(ETH_TXEN), From 1825c1fe0057e1904f772574e16d9cbbcaf30f85 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Sep 2020 05:43:29 +0900 Subject: [PATCH 28/78] pinctrl: Add DT bindings for Toshiba Visconti TMPV7700 SoC Add pinctrl bindings for Toshiba Visconti TMPV7700 SoC series. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal Link: https://lore.kernel.org/r/20200909204336.2558-2-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Linus Walleij --- .../pinctrl/toshiba,visconti-pinctrl.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml new file mode 100644 index 000000000000..d0d1a01140ea --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti TMPV770x pin mux/config controller + +maintainers: + - Nobuhiro Iwamatsu + +description: + Toshiba's Visconti ARM SoC a pin mux/config controller. + +properties: + compatible: + enum: + - toshiba,tmpv7708-pinctrl + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + '-pins$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength. + $ref: "pinmux-node.yaml" + + properties: + function: + description: + Function to mux. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8, + spi0, spi1, spi2, spi3, spi4, spi5, spi6, + uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in] + + groups: + description: + Name of the pin group to use for the functions. + $ref: "/schemas/types.yaml#/definitions/string" + enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp, + i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp, + spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp, + spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp, + uart0_grp, uart1_grp, uart2_grp, uart3_grp, + pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp, + pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp, + pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp, + pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp, + pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp, + pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp] + + drive-strength: + enum: [2, 4, 6, 8, 16, 24, 32] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-up: true + + bias-pull-down: true + + bias-disable: true + +additionalProperties: false + +examples: + # Pinmux controller node + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pmux: pmux@24190000 { + compatible = "toshiba,tmpv7708-pinctrl"; + reg = <0 0x24190000 0 0x10000>; + + spi0_pins: spi0-pins { + function = "spi0"; + groups = "spi0_grp"; + }; + }; + }; From a68a7844264e4fb91dcc1c6525cdb275223ce79c Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 10 Sep 2020 05:43:30 +0900 Subject: [PATCH 29/78] pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support Add pinctrl support to Toshiba Visconti SoCs. Signed-off-by: Nobuhiro Iwamatsu Reviewed-by: Punit Agrawal Link: https://lore.kernel.org/r/20200909204336.2558-3-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/visconti/Kconfig | 14 + drivers/pinctrl/visconti/Makefile | 3 + drivers/pinctrl/visconti/pinctrl-common.c | 305 +++++++++++++++++ drivers/pinctrl/visconti/pinctrl-common.h | 96 ++++++ drivers/pinctrl/visconti/pinctrl-tmpv7700.c | 355 ++++++++++++++++++++ 7 files changed, 775 insertions(+) create mode 100644 drivers/pinctrl/visconti/Kconfig create mode 100644 drivers/pinctrl/visconti/Makefile create mode 100644 drivers/pinctrl/visconti/pinctrl-common.c create mode 100644 drivers/pinctrl/visconti/pinctrl-common.h create mode 100644 drivers/pinctrl/visconti/pinctrl-tmpv7700.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8828613c4e0e..6f62b9bb79bb 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -429,6 +429,7 @@ source "drivers/pinctrl/mediatek/Kconfig" source "drivers/pinctrl/zte/Kconfig" source "drivers/pinctrl/meson/Kconfig" source "drivers/pinctrl/cirrus/Kconfig" +source "drivers/pinctrl/visconti/Kconfig" config PINCTRL_XWAY bool diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1731b2154df9..576cbedcbf73 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/ obj-y += mediatek/ obj-$(CONFIG_PINCTRL_ZX) += zte/ obj-y += cirrus/ +obj-$(CONFIG_PINCTRL_VISCONTI) += visconti/ diff --git a/drivers/pinctrl/visconti/Kconfig b/drivers/pinctrl/visconti/Kconfig new file mode 100644 index 000000000000..198ec33189cc --- /dev/null +++ b/drivers/pinctrl/visconti/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only +config PINCTRL_VISCONTI + bool + select PINMUX + select GENERIC_PINCONF + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + +config PINCTRL_TMPV7700 + bool "Toshiba Visconti TMPV7700 series pinctrl driver" + depends on OF + depends on ARM64 || COMPILE_TEST + select PINCTRL_VISCONTI + default ARM64 && ARCH_VISCONTI diff --git a/drivers/pinctrl/visconti/Makefile b/drivers/pinctrl/visconti/Makefile new file mode 100644 index 000000000000..43b2eb663bce --- /dev/null +++ b/drivers/pinctrl/visconti/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-$(CONFIG_PINCTRL_VISCONTI) += pinctrl-common.o +obj-$(CONFIG_PINCTRL_TMPV7700) += pinctrl-tmpv7700.o diff --git a/drivers/pinctrl/visconti/pinctrl-common.c b/drivers/pinctrl/visconti/pinctrl-common.c new file mode 100644 index 000000000000..0cb10b7b4430 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.c @@ -0,0 +1,305 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "pinctrl-common.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" + +#define DSEL_MASK GENMASK(3, 0) + +/* private data */ +struct visconti_pinctrl { + void __iomem *base; + struct device *dev; + struct pinctrl_dev *pctl; + struct pinctrl_desc pctl_desc; + + const struct visconti_pinctrl_devdata *devdata; + + spinlock_t lock; /* protect pinctrl register */ +}; + +/* pinconf */ +static int visconti_pin_config_set(struct pinctrl_dev *pctldev, + unsigned int _pin, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_desc_pin *pin = &priv->devdata->pins[_pin]; + enum pin_config_param param; + unsigned int arg; + int i, ret = 0; + unsigned int val, set_val, pude_val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: pin = %d (%s)\n", __func__, _pin, pin->pin.name); + + spin_lock_irqsave(&priv->lock, flags); + + for (i = 0; i < num_configs; i++) { + set_val = 0; + pude_val = 0; + + param = pinconf_to_config_param(configs[i]); + switch (param) { + case PIN_CONFIG_BIAS_PULL_UP: + set_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_PULL_DOWN: + /* update pudsel setting */ + val = readl(priv->base + pin->pudsel_offset); + val &= ~BIT(pin->pud_shift); + val |= set_val << pin->pud_shift; + writel(val, priv->base + pin->pudsel_offset); + pude_val = 1; + fallthrough; + case PIN_CONFIG_BIAS_DISABLE: + /* update pude setting */ + val = readl(priv->base + pin->pude_offset); + val &= ~BIT(pin->pud_shift); + val |= pude_val << pin->pud_shift; + writel(val, priv->base + pin->pude_offset); + dev_dbg(priv->dev, "BIAS(%d): off = 0x%x val = 0x%x\n", + param, pin->pude_offset, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + arg = pinconf_to_config_argument(configs[i]); + dev_dbg(priv->dev, "DRV_STR arg = %d\n", arg); + switch (arg) { + case 2: + case 4: + case 8: + case 16: + case 24: + case 32: + /* + * I/O drive capacity setting: + * 2mA: 0 + * 4mA: 1 + * 8mA: 3 + * 16mA: 7 + * 24mA: 11 + * 32mA: 15 + */ + set_val = DIV_ROUND_CLOSEST(arg, 2) - 1; + break; + default: + ret = -EINVAL; + goto err; + } + /* update drive setting */ + val = readl(priv->base + pin->dsel_offset); + val &= ~(DSEL_MASK << pin->dsel_shift); + val |= set_val << pin->dsel_shift; + writel(val, priv->base + pin->dsel_offset); + break; + + default: + ret = -EOPNOTSUPP; + goto err; + } + } +err: + spin_unlock_irqrestore(&priv->lock, flags); + return ret; +} + +static int visconti_pin_config_group_set(struct pinctrl_dev *pctldev, + unsigned int selector, + unsigned long *configs, + unsigned int num_configs) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const unsigned int *pins; + unsigned int num_pins; + int i, ret; + + pins = priv->devdata->groups[selector].pins; + num_pins = priv->devdata->groups[selector].nr_pins; + + dev_dbg(priv->dev, "%s: select = %d, n_pin = %d, n_config = %d\n", + __func__, selector, num_pins, num_configs); + + for (i = 0; i < num_pins; i++) { + ret = visconti_pin_config_set(pctldev, pins[i], + configs, num_configs); + if (ret) + return ret; + } + + return 0; +} +static const struct pinconf_ops visconti_pinconf_ops = { + .is_generic = true, + .pin_config_set = visconti_pin_config_set, + .pin_config_group_set = visconti_pin_config_group_set, + .pin_config_config_dbg_show = pinconf_generic_dump_config, +}; + +/* pinctrl */ +static int visconti_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_groups; +} + +static const char *visconti_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->groups[selector].name; +} + +static int visconti_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *pins = priv->devdata->groups[selector].pins; + *num_pins = priv->devdata->groups[selector].nr_pins; + + return 0; +} + +static const struct pinctrl_ops visconti_pinctrl_ops = { + .get_groups_count = visconti_get_groups_count, + .get_group_name = visconti_get_group_name, + .get_group_pins = visconti_get_group_pins, + .dt_node_to_map = pinconf_generic_dt_node_to_map_group, + .dt_free_map = pinctrl_utils_free_map, +}; + +/* pinmux */ +static int visconti_get_functions_count(struct pinctrl_dev *pctldev) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->nr_functions; +} + +static const char *visconti_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + return priv->devdata->functions[selector].name; +} + +static int visconti_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned * const num_groups) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + + *groups = priv->devdata->functions[selector].groups; + *num_groups = priv->devdata->functions[selector].nr_groups; + + return 0; +} + +static int visconti_set_mux(struct pinctrl_dev *pctldev, + unsigned int function, unsigned int group) +{ + struct visconti_pinctrl *priv = pinctrl_dev_get_drvdata(pctldev); + const struct visconti_pin_function *func = &priv->devdata->functions[function]; + const struct visconti_pin_group *grp = &priv->devdata->groups[group]; + const struct visconti_mux *mux = &grp->mux; + unsigned int val; + unsigned long flags; + + dev_dbg(priv->dev, "%s: function = %d(%s) group = %d(%s)\n", __func__, + function, func->name, group, grp->name); + + spin_lock_irqsave(&priv->lock, flags); + + /* update mux */ + val = readl(priv->base + mux->offset); + val &= ~mux->mask; + val |= mux->val; + writel(val, priv->base + mux->offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + dev_dbg(priv->dev, "[%x]: 0x%x\n", mux->offset, val); + + return 0; +} + +static const struct pinmux_ops visconti_pinmux_ops = { + .get_functions_count = visconti_get_functions_count, + .get_function_name = visconti_get_function_name, + .get_function_groups = visconti_get_function_groups, + .set_mux = visconti_set_mux, + .strict = true, +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata) +{ + struct device *dev = &pdev->dev; + struct visconti_pinctrl *priv; + struct pinctrl_pin_desc *pins; + int i, ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->devdata = devdata; + spin_lock_init(&priv->lock); + + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) { + dev_err(dev, "unable to map I/O space\n"); + return PTR_ERR(priv->base); + } + + pins = devm_kcalloc(dev, devdata->nr_pins, + sizeof(*pins), GFP_KERNEL); + if (!pins) + return -ENOMEM; + + for (i = 0; i < devdata->nr_pins; i++) + pins[i] = devdata->pins[i].pin; + + priv->pctl_desc.name = dev_name(dev); + priv->pctl_desc.owner = THIS_MODULE; + priv->pctl_desc.pins = pins; + priv->pctl_desc.npins = devdata->nr_pins; + priv->pctl_desc.confops = &visconti_pinconf_ops; + priv->pctl_desc.pctlops = &visconti_pinctrl_ops; + priv->pctl_desc.pmxops = &visconti_pinmux_ops; + + ret = devm_pinctrl_register_and_init(dev, &priv->pctl_desc, + priv, &priv->pctl); + if (ret) { + dev_err(dev, "couldn't register pinctrl: %d\n", ret); + return ret; + } + + if (devdata->unlock) + devdata->unlock(priv->base); + + return pinctrl_enable(priv->pctl); +} diff --git a/drivers/pinctrl/visconti/pinctrl-common.h b/drivers/pinctrl/visconti/pinctrl-common.h new file mode 100644 index 000000000000..56a2eb0225fb --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-common.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu + */ + +#ifndef __VISCONTI_PINCTRL_COMMON_H__ +#define __VISCONTI_PINCTRL_COMMON_H__ + +struct pinctrl_pin_desc; + +/* PIN */ +#define VISCONTI_PINS(pins_name, ...) \ + static const unsigned int pins_name ## _pins[] = { __VA_ARGS__ } + +struct visconti_desc_pin { + struct pinctrl_pin_desc pin; + unsigned int dsel_offset; + unsigned int dsel_shift; + unsigned int pude_offset; + unsigned int pudsel_offset; + unsigned int pud_shift; +}; + +#define VISCONTI_PIN(_pin, dsel, d_sh, pude, pudsel, p_sh) \ +{ \ + .pin = _pin, \ + .dsel_offset = dsel, \ + .dsel_shift = d_sh, \ + .pude_offset = pude, \ + .pudsel_offset = pudsel, \ + .pud_shift = p_sh, \ +} + +/* Group */ +#define VISCONTI_GROUPS(groups_name, ...) \ + static const char * const groups_name ## _grps[] = { __VA_ARGS__ } + +struct visconti_mux { + unsigned int offset; + unsigned int mask; + unsigned int val; +}; + +struct visconti_pin_group { + const char *name; + const unsigned int *pins; + unsigned int nr_pins; + struct visconti_mux mux; +}; + +#define VISCONTI_PIN_GROUP(group_name, off, msk, v) \ +{ \ + .name = __stringify(group_name) "_grp", \ + .pins = group_name ## _pins, \ + .nr_pins = ARRAY_SIZE(group_name ## _pins), \ + .mux = { \ + .offset = off, \ + .mask = msk, \ + .val = v, \ + } \ +} + +/* MUX */ +struct visconti_pin_function { + const char *name; + const char * const *groups; + unsigned int nr_groups; +}; + +#define VISCONTI_PIN_FUNCTION(func) \ +{ \ + .name = #func, \ + .groups = func ## _grps, \ + .nr_groups = ARRAY_SIZE(func ## _grps), \ +} + +/* chip dependent data */ +struct visconti_pinctrl_devdata { + const struct visconti_desc_pin *pins; + unsigned int nr_pins; + const struct visconti_pin_group *groups; + unsigned int nr_groups; + const struct visconti_pin_function *functions; + unsigned int nr_functions; + + const struct visconti_mux *gpio_mux; + + void (*unlock)(void __iomem *base); +}; + +int visconti_pinctrl_probe(struct platform_device *pdev, + const struct visconti_pinctrl_devdata *devdata); + +#endif /* __VISCONTI_PINCTRL_COMMON_H__ */ diff --git a/drivers/pinctrl/visconti/pinctrl-tmpv7700.c b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c new file mode 100644 index 000000000000..38a00d514f74 --- /dev/null +++ b/drivers/pinctrl/visconti/pinctrl-tmpv7700.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 TOSHIBA CORPORATION + * Copyright (c) 2020 Toshiba Electronic Devices & Storage Corporation + * Copyright (c) 2020 Nobuhiro Iwamatsu + */ + +#include +#include +#include +#include +#include +#include "pinctrl-common.h" + +#define tmpv7700_MAGIC_NUM 0x4932f70e + +/* register offset */ +#define REG_KEY_CTRL 0x0000 +#define REG_KEY_CMD 0x0004 +#define REG_PINMUX1 0x3000 +#define REG_PINMUX2 0x3004 +#define REG_PINMUX3 0x3008 +#define REG_PINMUX4 0x300c +#define REG_PINMUX5 0x3010 +#define REG_IOSET 0x3014 +#define REG_IO_VSEL 0x3018 +#define REG_IO_DSEL1 0x301c +#define REG_IO_DSEL2 0x3020 +#define REG_IO_DSEL3 0x3024 +#define REG_IO_DSEL4 0x3028 +#define REG_IO_DSEL5 0x302c +#define REG_IO_DSEL6 0x3030 +#define REG_IO_DSEL7 0x3034 +#define REG_IO_DSEL8 0x3038 +#define REG_IO_PUDE1 0x303c +#define REG_IO_PUDE2 0x3040 +#define REG_IO_PUDSEL1 0x3044 +#define REG_IO_PUDSEL2 0x3048 + +/* PIN */ +static const struct visconti_desc_pin pins_tmpv7700[] = { + VISCONTI_PIN(PINCTRL_PIN(0, "gpio0"), REG_IO_DSEL4, 24, + REG_IO_PUDE1, REG_IO_PUDSEL1, 30), + VISCONTI_PIN(PINCTRL_PIN(1, "gpio1"), REG_IO_DSEL4, 28, + REG_IO_PUDE1, REG_IO_PUDSEL1, 31), + VISCONTI_PIN(PINCTRL_PIN(2, "gpio2"), REG_IO_DSEL5, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 0), + VISCONTI_PIN(PINCTRL_PIN(3, "gpio3"), REG_IO_DSEL5, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 1), + VISCONTI_PIN(PINCTRL_PIN(4, "gpio4"), REG_IO_DSEL5, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 2), + VISCONTI_PIN(PINCTRL_PIN(5, "gpio5"), REG_IO_DSEL5, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 3), + VISCONTI_PIN(PINCTRL_PIN(6, "gpio6"), REG_IO_DSEL5, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 4), + VISCONTI_PIN(PINCTRL_PIN(7, "gpio7"), REG_IO_DSEL5, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 5), + VISCONTI_PIN(PINCTRL_PIN(8, "gpio8"), REG_IO_DSEL5, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 6), + VISCONTI_PIN(PINCTRL_PIN(9, "gpio9"), REG_IO_DSEL5, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 7), + VISCONTI_PIN(PINCTRL_PIN(10, "gpio10"), REG_IO_DSEL6, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 8), + VISCONTI_PIN(PINCTRL_PIN(11, "gpio11"), REG_IO_DSEL6, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 9), + VISCONTI_PIN(PINCTRL_PIN(12, "gpio12"), REG_IO_DSEL6, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 10), + VISCONTI_PIN(PINCTRL_PIN(13, "gpio13"), REG_IO_DSEL6, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 11), + VISCONTI_PIN(PINCTRL_PIN(14, "gpio14"), REG_IO_DSEL6, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 12), + VISCONTI_PIN(PINCTRL_PIN(15, "gpio15"), REG_IO_DSEL6, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 13), + VISCONTI_PIN(PINCTRL_PIN(16, "gpio16"), REG_IO_DSEL6, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 14), + VISCONTI_PIN(PINCTRL_PIN(17, "gpio17"), REG_IO_DSEL6, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 15), + VISCONTI_PIN(PINCTRL_PIN(18, "gpio18"), REG_IO_DSEL7, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 16), + VISCONTI_PIN(PINCTRL_PIN(19, "gpio19"), REG_IO_DSEL7, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 17), + VISCONTI_PIN(PINCTRL_PIN(20, "gpio20"), REG_IO_DSEL7, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 18), + VISCONTI_PIN(PINCTRL_PIN(21, "gpio21"), REG_IO_DSEL7, 12, + REG_IO_PUDE2, REG_IO_PUDSEL2, 19), + VISCONTI_PIN(PINCTRL_PIN(22, "gpio22"), REG_IO_DSEL7, 16, + REG_IO_PUDE2, REG_IO_PUDSEL2, 20), + VISCONTI_PIN(PINCTRL_PIN(23, "gpio23"), REG_IO_DSEL7, 20, + REG_IO_PUDE2, REG_IO_PUDSEL2, 21), + VISCONTI_PIN(PINCTRL_PIN(24, "gpio24"), REG_IO_DSEL7, 24, + REG_IO_PUDE2, REG_IO_PUDSEL2, 22), + VISCONTI_PIN(PINCTRL_PIN(25, "gpio25"), REG_IO_DSEL7, 28, + REG_IO_PUDE2, REG_IO_PUDSEL2, 23), + VISCONTI_PIN(PINCTRL_PIN(26, "gpio26"), REG_IO_DSEL8, 0, + REG_IO_PUDE2, REG_IO_PUDSEL2, 24), + VISCONTI_PIN(PINCTRL_PIN(27, "gpio27"), REG_IO_DSEL8, 4, + REG_IO_PUDE2, REG_IO_PUDSEL2, 25), + VISCONTI_PIN(PINCTRL_PIN(28, "gpio28"), REG_IO_DSEL8, 8, + REG_IO_PUDE2, REG_IO_PUDSEL2, 26), + VISCONTI_PIN(PINCTRL_PIN(29, "gpio29"), REG_IO_DSEL4, 8, + REG_IO_PUDE1, REG_IO_PUDSEL1, 26), + VISCONTI_PIN(PINCTRL_PIN(30, "gpio30"), REG_IO_DSEL4, 4, + REG_IO_PUDE1, REG_IO_PUDSEL1, 25), + VISCONTI_PIN(PINCTRL_PIN(31, "gpio31"), REG_IO_DSEL4, 0, + REG_IO_PUDE1, REG_IO_PUDSEL1, 24), + VISCONTI_PIN(PINCTRL_PIN(32, "spi_sck"), REG_IO_DSEL4, 12, + REG_IO_PUDE1, REG_IO_PUDSEL1, 27), + VISCONTI_PIN(PINCTRL_PIN(33, "spi_sdo"), REG_IO_DSEL4, 16, + REG_IO_PUDE1, REG_IO_PUDSEL1, 28), + VISCONTI_PIN(PINCTRL_PIN(34, "spi_sdi"), REG_IO_DSEL4, 20, + REG_IO_PUDE1, REG_IO_PUDSEL1, 29), +}; + +/* Group */ +VISCONTI_PINS(i2c0, 0, 1); +VISCONTI_PINS(i2c1, 2, 3); +VISCONTI_PINS(i2c2, 12, 13); +VISCONTI_PINS(i2c3, 14, 15); +VISCONTI_PINS(i2c4, 16, 17); +VISCONTI_PINS(i2c5, 18, 19); +VISCONTI_PINS(i2c6, 33, 34); +VISCONTI_PINS(i2c7, 29, 32); +VISCONTI_PINS(i2c8, 30, 31); +VISCONTI_PINS(spi0_cs0, 29); +VISCONTI_PINS(spi0_cs1, 30); +VISCONTI_PINS(spi0_cs2, 31); +VISCONTI_PINS(spi1_cs, 3); +VISCONTI_PINS(spi2_cs, 7); +VISCONTI_PINS(spi3_cs, 11); +VISCONTI_PINS(spi4_cs, 15); +VISCONTI_PINS(spi5_cs, 19); +VISCONTI_PINS(spi6_cs, 27); +VISCONTI_PINS(spi0, 32, 33, 34); +VISCONTI_PINS(spi1, 0, 1, 2); +VISCONTI_PINS(spi2, 4, 5, 6); +VISCONTI_PINS(spi3, 8, 9, 10); +VISCONTI_PINS(spi4, 12, 13, 14); +VISCONTI_PINS(spi5, 16, 17, 18); +VISCONTI_PINS(spi6, 24, 25, 26); +VISCONTI_PINS(uart0, 4, 5, 6, 7); +VISCONTI_PINS(uart1, 8, 9, 10, 11); +VISCONTI_PINS(uart2, 12, 13, 14, 15); +VISCONTI_PINS(uart3, 16, 17, 18, 19); +VISCONTI_PINS(pwm0_gpio4, 4); +VISCONTI_PINS(pwm1_gpio5, 5); +VISCONTI_PINS(pwm2_gpio6, 6); +VISCONTI_PINS(pwm3_gpio7, 7); +VISCONTI_PINS(pwm0_gpio8, 8); +VISCONTI_PINS(pwm1_gpio9, 9); +VISCONTI_PINS(pwm2_gpio10, 10); +VISCONTI_PINS(pwm3_gpio11, 11); +VISCONTI_PINS(pwm0_gpio12, 12); +VISCONTI_PINS(pwm1_gpio13, 13); +VISCONTI_PINS(pwm2_gpio14, 14); +VISCONTI_PINS(pwm3_gpio15, 15); +VISCONTI_PINS(pwm0_gpio16, 16); +VISCONTI_PINS(pwm1_gpio17, 17); +VISCONTI_PINS(pwm2_gpio18, 18); +VISCONTI_PINS(pwm3_gpio19, 19); +VISCONTI_PINS(pcmif_out, 20, 21, 22); +VISCONTI_PINS(pcmif_in, 24, 25, 26); + +static const struct visconti_pin_group groups_tmpv7700[] = { + VISCONTI_PIN_GROUP(i2c0, REG_PINMUX2, GENMASK(7, 0), 0x00000022), + VISCONTI_PIN_GROUP(i2c1, REG_PINMUX2, GENMASK(15, 8), 0x00002200), + VISCONTI_PIN_GROUP(i2c2, REG_PINMUX3, GENMASK(23, 16), 0x00770000), + VISCONTI_PIN_GROUP(i2c3, REG_PINMUX3, GENMASK(31, 24), 0x77000000), + VISCONTI_PIN_GROUP(i2c4, REG_PINMUX4, GENMASK(7, 0), 0x00000077), + VISCONTI_PIN_GROUP(i2c5, REG_PINMUX4, GENMASK(15, 8), 0x00007700), + VISCONTI_PIN_GROUP(i2c6, REG_PINMUX1, GENMASK(3, 0), 0x0000002), + VISCONTI_PIN_GROUP(i2c7, REG_PINMUX5, GENMASK(23, 20), 0x00200000), + VISCONTI_PIN_GROUP(i2c8, REG_PINMUX5, GENMASK(31, 24), 0x22000000), + VISCONTI_PIN_GROUP(spi0_cs0, REG_PINMUX5, GENMASK(23, 20), 0x00100000), + VISCONTI_PIN_GROUP(spi0_cs1, REG_PINMUX5, GENMASK(27, 24), 0x01000000), + VISCONTI_PIN_GROUP(spi0_cs2, REG_PINMUX5, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi1_cs, REG_PINMUX2, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi2_cs, REG_PINMUX2, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi3_cs, REG_PINMUX3, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi4_cs, REG_PINMUX4, GENMASK(31, 28), 0x10000000), + VISCONTI_PIN_GROUP(spi5_cs, REG_PINMUX4, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi6_cs, REG_PINMUX5, GENMASK(15, 12), 0x00001000), + VISCONTI_PIN_GROUP(spi0, REG_PINMUX1, GENMASK(3, 0), 0x00000001), + VISCONTI_PIN_GROUP(spi1, REG_PINMUX2, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi2, REG_PINMUX2, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi3, REG_PINMUX3, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi4, REG_PINMUX3, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(spi5, REG_PINMUX4, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(spi6, REG_PINMUX5, GENMASK(11, 0), 0x00000111), + VISCONTI_PIN_GROUP(uart0, REG_PINMUX2, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart1, REG_PINMUX3, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(uart2, REG_PINMUX3, GENMASK(31, 16), 0x22220000), + VISCONTI_PIN_GROUP(uart3, REG_PINMUX4, GENMASK(15, 0), 0x00002222), + VISCONTI_PIN_GROUP(pwm0_gpio4, REG_PINMUX2, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio5, REG_PINMUX2, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio6, REG_PINMUX2, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio7, REG_PINMUX2, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio8, REG_PINMUX3, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio9, REG_PINMUX3, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio10, REG_PINMUX3, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio11, REG_PINMUX3, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pwm0_gpio12, REG_PINMUX3, GENMASK(19, 16), 0x00050000), + VISCONTI_PIN_GROUP(pwm1_gpio13, REG_PINMUX3, GENMASK(23, 20), 0x00500000), + VISCONTI_PIN_GROUP(pwm2_gpio14, REG_PINMUX3, GENMASK(27, 24), 0x05000000), + VISCONTI_PIN_GROUP(pwm3_gpio15, REG_PINMUX3, GENMASK(31, 28), 0x50000000), + VISCONTI_PIN_GROUP(pwm0_gpio16, REG_PINMUX4, GENMASK(3, 0), 0x00000005), + VISCONTI_PIN_GROUP(pwm1_gpio17, REG_PINMUX4, GENMASK(7, 4), 0x00000050), + VISCONTI_PIN_GROUP(pwm2_gpio18, REG_PINMUX4, GENMASK(11, 8), 0x00000500), + VISCONTI_PIN_GROUP(pwm3_gpio19, REG_PINMUX4, GENMASK(15, 12), 0x00005000), + VISCONTI_PIN_GROUP(pcmif_out, REG_PINMUX4, GENMASK(27, 16), 0x01110000), + VISCONTI_PIN_GROUP(pcmif_in, REG_PINMUX5, GENMASK(11, 0), 0x00000222), +}; + +/* MUX */ +VISCONTI_GROUPS(i2c0, "i2c0_grp"); +VISCONTI_GROUPS(i2c1, "i2c1_grp"); +VISCONTI_GROUPS(i2c2, "i2c2_grp"); +VISCONTI_GROUPS(i2c3, "i2c3_grp"); +VISCONTI_GROUPS(i2c4, "i2c4_grp"); +VISCONTI_GROUPS(i2c5, "i2c5_grp"); +VISCONTI_GROUPS(i2c6, "i2c6_grp"); +VISCONTI_GROUPS(i2c7, "i2c7_grp"); +VISCONTI_GROUPS(i2c8, "i2c8_grp"); +VISCONTI_GROUPS(spi0, "spi0_grp", "spi0_cs0_grp", + "spi0_cs1_grp", "spi0_cs2_grp"); +VISCONTI_GROUPS(spi1, "spi1_grp", "spi1_cs_grp"); +VISCONTI_GROUPS(spi2, "spi2_grp", "spi2_cs_grp"); +VISCONTI_GROUPS(spi3, "spi3_grp", "spi3_cs_grp"); +VISCONTI_GROUPS(spi4, "spi4_grp", "spi4_cs_grp"); +VISCONTI_GROUPS(spi5, "spi5_grp", "spi5_cs_grp"); +VISCONTI_GROUPS(spi6, "spi6_grp", "spi6_cs_grp"); +VISCONTI_GROUPS(uart0, "uart0_grp"); +VISCONTI_GROUPS(uart1, "uart1_grp"); +VISCONTI_GROUPS(uart2, "uart2_grp"); +VISCONTI_GROUPS(uart3, "uart3_grp"); +VISCONTI_GROUPS(pwm, "pwm0_gpio4_grp", "pwm0_gpio8_grp", + "pwm0_gpio12_grp", "pwm0_gpio16_grp", + "pwm1_gpio5_grp", "pwm1_gpio9_grp", + "pwm1_gpio13_grp", "pwm1_gpio17_grp", + "pwm2_gpio6_grp", "pwm2_gpio10_grp", + "pwm2_gpio14_grp", "pwm2_gpio18_grp", + "pwm3_gpio7_grp", "pwm3_gpio11_grp", + "pwm3_gpio15_grp", "pwm3_gpio19_grp"); +VISCONTI_GROUPS(pcmif_out, "pcmif_out_grp"); +VISCONTI_GROUPS(pcmif_in, "pcmif_in_grp"); + +static const struct visconti_pin_function functions_tmpv7700[] = { + VISCONTI_PIN_FUNCTION(i2c0), + VISCONTI_PIN_FUNCTION(i2c1), + VISCONTI_PIN_FUNCTION(i2c2), + VISCONTI_PIN_FUNCTION(i2c3), + VISCONTI_PIN_FUNCTION(i2c4), + VISCONTI_PIN_FUNCTION(i2c5), + VISCONTI_PIN_FUNCTION(i2c6), + VISCONTI_PIN_FUNCTION(i2c7), + VISCONTI_PIN_FUNCTION(i2c8), + VISCONTI_PIN_FUNCTION(spi0), + VISCONTI_PIN_FUNCTION(spi1), + VISCONTI_PIN_FUNCTION(spi2), + VISCONTI_PIN_FUNCTION(spi3), + VISCONTI_PIN_FUNCTION(spi4), + VISCONTI_PIN_FUNCTION(spi5), + VISCONTI_PIN_FUNCTION(spi6), + VISCONTI_PIN_FUNCTION(uart0), + VISCONTI_PIN_FUNCTION(uart1), + VISCONTI_PIN_FUNCTION(uart2), + VISCONTI_PIN_FUNCTION(uart3), + VISCONTI_PIN_FUNCTION(pwm), + VISCONTI_PIN_FUNCTION(pcmif_in), + VISCONTI_PIN_FUNCTION(pcmif_out), +}; + +/* GPIO MUX */ +#define tmpv7700_GPIO_MUX(off, msk) \ +{ \ + .offset = off, \ + .mask = msk, \ + .val = 0, \ +} + +static const struct visconti_mux gpio_mux_tmpv7700[] = { + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX2, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX3, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX4, GENMASK(31, 28)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(3, 0)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(7, 4)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(11, 8)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(15, 12)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(19, 16)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(23, 20)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(27, 24)), + tmpv7700_GPIO_MUX(REG_PINMUX5, GENMASK(31, 28)), +}; + +static void tmpv7700_pinctrl_unlock(void __iomem *base) +{ + writel(1, base + REG_KEY_CTRL); + writel(tmpv7700_MAGIC_NUM, base + REG_KEY_CMD); +} + +/* chip dependent data */ +static const struct visconti_pinctrl_devdata tmpv7700_pinctrl_data = { + .pins = pins_tmpv7700, + .nr_pins = ARRAY_SIZE(pins_tmpv7700), + .groups = groups_tmpv7700, + .nr_groups = ARRAY_SIZE(groups_tmpv7700), + .functions = functions_tmpv7700, + .nr_functions = ARRAY_SIZE(functions_tmpv7700), + .gpio_mux = gpio_mux_tmpv7700, + .unlock = tmpv7700_pinctrl_unlock, +}; + +static int tmpv7700_pinctrl_probe(struct platform_device *pdev) +{ + return visconti_pinctrl_probe(pdev, &tmpv7700_pinctrl_data); +} + +static const struct of_device_id tmpv7700_pctrl_of_match[] = { + { .compatible = "toshiba,tmpv7708-pinctrl", }, + {}, +}; + +static struct platform_driver tmpv7700_pinctrl_driver = { + .probe = tmpv7700_pinctrl_probe, + .driver = { + .name = "tmpv7700-pinctrl", + .of_match_table = tmpv7700_pctrl_of_match, + }, +}; + +static int __init tmpv7700_pinctrl_init(void) +{ + return platform_driver_register(&tmpv7700_pinctrl_driver); +} +arch_initcall(tmpv7700_pinctrl_init); From 96bef667ddbb82e891ed15b7087d1ae0a7081115 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:00:31 +0800 Subject: [PATCH 30/78] dt-bindings: pinctrl: sunxi: Get rid of continual nesting Rather than a continual nesting of 'else' clauses, just make each 'if' a new entry under 'allOf' and get rid of the else. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/229e4870dab1b34797304c384e68c7d04196423b.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 112 ++++++++++-------- 1 file changed, 62 insertions(+), 50 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 7556be6e2754..35a26abb02e7 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -155,62 +155,74 @@ allOf: minItems: 5 maxItems: 5 - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-pinctrl - - allwinner,sun6i-a31s-pinctrl - - allwinner,sun50i-h6-pinctrl + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-pinctrl + - allwinner,sun6i-a31s-pinctrl + - allwinner,sun50i-h6-pinctrl - then: - properties: - interrupts: - minItems: 4 - maxItems: 4 + then: + properties: + interrupts: + minItems: 4 + maxItems: 4 - else: - if: - properties: - compatible: - enum: - - allwinner,sun8i-a23-pinctrl - - allwinner,sun8i-a83t-pinctrl - - allwinner,sun50i-a64-pinctrl - - allwinner,sun50i-h5-pinctrl - - allwinner,suniv-f1c100s-pinctrl + - if: + properties: + compatible: + enum: + - allwinner,sun8i-a23-pinctrl + - allwinner,sun8i-a83t-pinctrl + - allwinner,sun50i-a64-pinctrl + - allwinner,sun50i-h5-pinctrl + - allwinner,suniv-f1c100s-pinctrl - then: - properties: - interrupts: - minItems: 3 - maxItems: 3 + then: + properties: + interrupts: + minItems: 3 + maxItems: 3 - else: - if: - properties: - compatible: - enum: - - allwinner,sun6i-a31-r-pinctrl - - allwinner,sun8i-a33-pinctrl - - allwinner,sun8i-h3-pinctrl - - allwinner,sun8i-v3-pinctrl - - allwinner,sun8i-v3s-pinctrl - - allwinner,sun9i-a80-r-pinctrl - - allwinner,sun50i-h6-r-pinctrl + - if: + properties: + compatible: + enum: + - allwinner,sun6i-a31-r-pinctrl + - allwinner,sun8i-a33-pinctrl + - allwinner,sun8i-h3-pinctrl + - allwinner,sun8i-v3-pinctrl + - allwinner,sun8i-v3s-pinctrl + - allwinner,sun9i-a80-r-pinctrl + - allwinner,sun50i-h6-r-pinctrl - then: - properties: - interrupts: - minItems: 2 - maxItems: 2 + then: + properties: + interrupts: + minItems: 2 + maxItems: 2 - else: - properties: - interrupts: - minItems: 1 - maxItems: 1 + - if: + properties: + compatible: + enum: + - allwinner,sun4i-a10-pinctrl + - allwinner,sun5i-a10s-pinctrl + - allwinner,sun5i-a13-pinctrl + - allwinner,sun7i-a20-pinctrl + - allwinner,sun8i-a23-r-pinctrl + - allwinner,sun8i-a83t-r-pinctrl + - allwinner,sun8i-h3-r-pinctrl + - allwinner,sun8i-r40-pinctrl + - allwinner,sun50i-a64-r-pinctrl + - nextthing,gr8-pinctrl + + then: + properties: + interrupts: + minItems: 1 + maxItems: 1 additionalProperties: false From 5e842dc23cd3a99051f615161bb0972b8dc10d66 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:02:42 +0800 Subject: [PATCH 31/78] dt-bindings: pinctrl: sunxi: Add A100 pinctrl bindings Add device tree binding Documentation details for A100 pinctrl driver, which has a r pin controller and a pin controller with more irq lines. Signed-off-by: Yangtao Li Reviewed-by: Rob Herring Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/a5773d677bcc89af3810cdd187fae54eced82f27.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 35a26abb02e7..34a17d5c6135 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -48,6 +48,8 @@ properties: - allwinner,sun9i-a80-r-pinctrl - allwinner,sun50i-a64-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-pinctrl + - allwinner,sun50i-a100-r-pinctrl - allwinner,sun50i-h5-pinctrl - allwinner,sun50i-h6-pinctrl - allwinner,sun50i-h6-r-pinctrl @@ -143,6 +145,18 @@ allOf: # boards are defining it at the moment so it would generate a lot of # warnings. + - if: + properties: + compatible: + enum: + - allwinner,sun50i-a100-pinctrl + + then: + properties: + interrupts: + minItems: 7 + maxItems: 7 + - if: properties: compatible: @@ -216,6 +230,7 @@ allOf: - allwinner,sun8i-h3-r-pinctrl - allwinner,sun8i-r40-pinctrl - allwinner,sun50i-a64-r-pinctrl + - allwinner,sun50i-a100-r-pinctrl - nextthing,gr8-pinctrl then: From 473436e7647d63dc8bc144edd4b970fd210509d7 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Fri, 24 Jul 2020 15:05:49 +0800 Subject: [PATCH 32/78] pinctrl: sunxi: add support for the Allwinner A100 pin controller This commit introduces support for the pin controller on A100. Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Link: https://lore.kernel.org/r/4e331a2ed4a30c883df6157bc5c52bb686aa8e0d.1595572867.git.frank@allwinnertech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/Kconfig | 10 + drivers/pinctrl/sunxi/Makefile | 2 + drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c | 105 +++ drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 708 ++++++++++++++++++ 4 files changed, 825 insertions(+) create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index f7aae200ee15..593293584ecc 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -94,6 +94,16 @@ config PINCTRL_SUN50I_A64_R default ARM64 && ARCH_SUNXI select PINCTRL_SUNXI +config PINCTRL_SUN50I_A100 + bool "Support for the Allwinner A100 PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + +config PINCTRL_SUN50I_A100_R + bool "Support for the Allwinner A100 R-PIO" + default ARM64 && ARCH_SUNXI + select PINCTRL_SUNXI + config PINCTRL_SUN50I_H5 bool "Support for the Allwinner H5 PIO" default ARM64 && ARCH_SUNXI diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile index fafcdae8134f..8b7ff0dc3bdf 100644 --- a/drivers/pinctrl/sunxi/Makefile +++ b/drivers/pinctrl/sunxi/Makefile @@ -13,6 +13,8 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23_R) += pinctrl-sun8i-a23-r.o obj-$(CONFIG_PINCTRL_SUN8I_A33) += pinctrl-sun8i-a33.o obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o obj-$(CONFIG_PINCTRL_SUN50I_A64_R) += pinctrl-sun50i-a64-r.o +obj-$(CONFIG_PINCTRL_SUN50I_A100) += pinctrl-sun50i-a100.o +obj-$(CONFIG_PINCTRL_SUN50I_A100_R) += pinctrl-sun50i-a100-r.o obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c new file mode 100644 index 000000000000..21054fcacd34 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100-r.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Yangtao Li + * + * Based on: + * huangshuosheng + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin a100_r_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c1"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_i2c1"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "s_pwm"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(L, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "s_cir"), /* IN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), +}; + +static const struct sunxi_pinctrl_desc a100_r_pinctrl_data = { + .pins = a100_r_pins, + .npins = ARRAY_SIZE(a100_r_pins), + .pin_base = PL_BASE, + .irq_banks = 1, +}; + +static int a100_r_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &a100_r_pinctrl_data); +} + +static const struct of_device_id a100_r_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a100-r-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, a100_r_pinctrl_match); + +static struct platform_driver a100_r_pinctrl_driver = { + .probe = a100_r_pinctrl_probe, + .driver = { + .name = "sun50iw10p1-r-pinctrl", + .of_match_table = a100_r_pinctrl_match, + }, +}; +module_platform_driver(a100_r_pinctrl_driver); diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c new file mode 100644 index 000000000000..19cfd1e76ee2 --- /dev/null +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c @@ -0,0 +1,708 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Yangtao Li + * + * Based on: + * huangshuosheng + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-sunxi.h" + +static const struct sunxi_desc_pin a100_pins[] = { + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ + SUNXI_FUNCTION(0x3, "spi2"), /* CS */ + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ + SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x3, "i2s0"), /* MCLK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "i2s0"), /* BCLK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s0"), /* LRCK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* DIN */ + SUNXI_FUNCTION(0x3, "i2s0_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s0_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "spdif"), /* DOUT */ + SUNXI_FUNCTION(0x3, "i2s0_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x4, "i2s0_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x4, "pwm1"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* DS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* RST */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ + SUNXI_FUNCTION(0x4, "spi0"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */ + SUNXI_FUNCTION(0x4, "spi0"), /* CS0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ + SUNXI_FUNCTION(0x4, "spi0"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* RB1 */ + SUNXI_FUNCTION(0x4, "spi0"), /* CS1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D4 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D5 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */ + SUNXI_FUNCTION(0x4, "spi0"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D6 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D2 */ + SUNXI_FUNCTION(0x4, "spi0"), /* WP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ + SUNXI_FUNCTION(0x3, "mmc2"), /* D7 */ + SUNXI_FUNCTION(0x4, "spi0"), /* HOLD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 16)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D0P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D0N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D1P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D1N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D2P */ + SUNXI_FUNCTION(0x4, "dsi0"), /* CKP */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* D2N */ + SUNXI_FUNCTION(0x4, "dsi0"), /* CKM */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* CKP */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */ + SUNXI_FUNCTION(0x3, "lvds0"), /* CKN */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DP3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */ + SUNXI_FUNCTION(0x4, "dsi0"), /* DM3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */ + SUNXI_FUNCTION(0x4, "spi1"), /* CS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */ + SUNXI_FUNCTION(0x4, "spi1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */ + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */ + SUNXI_FUNCTION(0x4, "spi1"), /* MISO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */ + SUNXI_FUNCTION(0x4, "uart3"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */ + SUNXI_FUNCTION(0x4, "uart3"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */ + SUNXI_FUNCTION(0x4, "uart3"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */ + SUNXI_FUNCTION(0x4, "uart4"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* DE */ + SUNXI_FUNCTION(0x4, "uart4"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 19)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 20), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */ + SUNXI_FUNCTION(0x3, "pwm2"), + SUNXI_FUNCTION(0x4, "uart4"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 20)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 21), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */ + SUNXI_FUNCTION(0x3, "pwm3"), + SUNXI_FUNCTION(0x4, "uart4"), /* CTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 21)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 22), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm1"), + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 22)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 23), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "pwm0"), + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 23)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c2"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c3"), /* SDA */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */ + SUNXI_FUNCTION(0x3, "pll"), /* LOCK_DBG */ + SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x5, "ledc"), /* LEDC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT0 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "csi"), /* SM_VS */ + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT1 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ + SUNXI_FUNCTION(0x5, "tcon0"), /* TRIG */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT2 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* DOUT0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "bist0"), /* RESULT3 */ + SUNXI_FUNCTION(0x4, "i2s2"), /* DIN0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */ + SUNXI_FUNCTION(0x3, "jtag"), /* MS1 */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* MS_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */ + SUNXI_FUNCTION(0x3, "jtag"), /* DI1 */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DI_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */ + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */ + SUNXI_FUNCTION(0x3, "jtag"), /* DO */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* DO_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */ + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */ + SUNXI_FUNCTION(0x3, "jtag"), /* CK */ + SUNXI_FUNCTION(0x4, "jtag_gpu"), /* CK_GPU */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 4, 6)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s1_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s1_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x4, "i2s1_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 5, 13)), + /* HOLE */ + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 0)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 1)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCTL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 2)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ + SUNXI_FUNCTION(0x3, "cir0"), /* OUT */ + SUNXI_FUNCTION(0x5, "emac0"), /* CLKIN */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 3)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CS */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 4)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ + SUNXI_FUNCTION(0x3, "spi1"), /* CLK */ + SUNXI_FUNCTION(0x4, "ledc"), + SUNXI_FUNCTION(0x5, "emac0"), /* TXD0 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 5)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 6)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ + SUNXI_FUNCTION(0x3, "spi1"), /* MISO */ + SUNXI_FUNCTION(0x4, "spdif"), /* OUT */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXCTL */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 7)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* CLK */ + SUNXI_FUNCTION(0x3, "spi2"), /* CS */ + SUNXI_FUNCTION(0x4, "i2s2"), /* MCLK */ + SUNXI_FUNCTION(0x5, "i2s2_din2"), /* DIN2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 8)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA0 */ + SUNXI_FUNCTION(0x3, "spi2"), /* CLK */ + SUNXI_FUNCTION(0x4, "i2s2"), /* BCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDC */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 9)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 10), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA1 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MOSI */ + SUNXI_FUNCTION(0x4, "i2s2"), /* LRCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* MDIO */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 10)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 11), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA2 */ + SUNXI_FUNCTION(0x3, "spi2"), /* MISO */ + SUNXI_FUNCTION(0x4, "i2s2_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x5, "i2s2_din1"), /* DIN1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 11)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 12), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "dmic"), /* DATA3 */ + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s2_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x5, "i2s2_dout1"), /* DOUT1 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 12)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 13), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2c3"), /* SCK */ + SUNXI_FUNCTION(0x4, "i2s3"), /* MCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* EPHY */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 13)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 14), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "i2s3"), /* BCLK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 14)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 15), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x4, "i2s3"), /* LRCK */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXD2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 15)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 16), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s3_dout0"), /* DOUT0 */ + SUNXI_FUNCTION(0x4, "i2s3_din1"), /* DIN1 */ + SUNXI_FUNCTION(0x5, "emac0"), /* RXCK */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 16)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 17), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x3, "i2s3_dout1"), /* DOUT1 */ + SUNXI_FUNCTION(0x4, "i2s3_din0"), /* DIN0 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD3 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 17)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 18), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "cir0"), /* OUT */ + SUNXI_FUNCTION(0x3, "i2s3_dout2"), /* DOUT2 */ + SUNXI_FUNCTION(0x4, "i2s3_din2"), /* DIN2 */ + SUNXI_FUNCTION(0x5, "emac0"), /* TXD2 */ + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 18)), + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 19), + SUNXI_FUNCTION(0x0, "gpio_in"), + SUNXI_FUNCTION(0x1, "gpio_out"), + SUNXI_FUNCTION(0x2, "cir0"), /* IN */ + SUNXI_FUNCTION(0x3, "i2s3_dout3"), /* DOUT3 */ + SUNXI_FUNCTION(0x4, "i2s3_din3"), /* DIN3 */ + SUNXI_FUNCTION(0x5, "ledc"), + SUNXI_FUNCTION_IRQ_BANK(0x6, 6, 19)), +}; + +static const unsigned int a100_irq_bank_map[] = { 0, 1, 2, 3, 4, 5, 6}; + +static const struct sunxi_pinctrl_desc a100_pinctrl_data = { + .pins = a100_pins, + .npins = ARRAY_SIZE(a100_pins), + .irq_banks = 7, + .irq_bank_map = a100_irq_bank_map, + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, +}; + +static int a100_pinctrl_probe(struct platform_device *pdev) +{ + return sunxi_pinctrl_init(pdev, &a100_pinctrl_data); +} + +static const struct of_device_id a100_pinctrl_match[] = { + { .compatible = "allwinner,sun50i-a100-pinctrl", }, + {} +}; +MODULE_DEVICE_TABLE(of, a100_pinctrl_match); + +static struct platform_driver a100_pinctrl_driver = { + .probe = a100_pinctrl_probe, + .driver = { + .name = "sun50i-a100-pinctrl", + .of_match_table = a100_pinctrl_match, + }, +}; +module_platform_driver(a100_pinctrl_driver); From 0662e4a190cfdb50df7a00bbc9aebe3ed3f09474 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 5 Sep 2020 23:49:55 +0200 Subject: [PATCH 33/78] pinctrl: rockchip: depend on OF The Rockchip pinctrl driver needs to handle information from Devicetree so only makes sense getting compiled on systems with CONFIG_OF enabled. This also fixes a problem found by the "kernel-test-robot" when compiling the driver on test-builds that do not have CONFIG_OF enabled: drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_pinctrl_parse_groups': >> drivers/pinctrl/pinctrl-rockchip.c:2881:9: error: implicit declaration of function 'pinconf_generic_parse_dt_config'; did you mean 'pinconf_generic_dump_config'? [-Werror=implicit-function-declaration] 2881 | ret = pinconf_generic_parse_dt_config(np_config, NULL, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | pinconf_generic_dump_config drivers/pinctrl/pinctrl-rockchip.c: In function 'rockchip_gpiolib_register': >> drivers/pinctrl/pinctrl-rockchip.c:3473:5: error: 'struct gpio_chip' has no member named 'of_node' 3473 | gc->of_node = bank->of_node; Reported-by: kernel test robot Signed-off-by: Heiko Stuebner Link: https://lore.kernel.org/r/20200905214955.907950-1-heiko@sntech.de Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 6f62b9bb79bb..029dd65eaa76 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -208,10 +208,12 @@ config PINCTRL_OXNAS config PINCTRL_ROCKCHIP bool + depends on OF select PINMUX select GENERIC_PINCONF select GENERIC_IRQ_CHIP select MFD_SYSCON + select OF_GPIO config PINCTRL_RZA1 bool "Renesas RZ/A1 gpio and pinctrl driver" From 6d8e04f9d38345770572a39125a47da37bb8ce9e Mon Sep 17 00:00:00 2001 From: Martin DEVERA Date: Wed, 5 Aug 2020 11:28:11 +0200 Subject: [PATCH 34/78] pinctrl: sx150x: Fix pinctrl enablement order bug MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I encountered bug in SX1502 expander driver in 5.7.7. Here is relevant DTS part: compatible = "semtech,sx1502q"; gpio4_cfg_pins: gpio2-cfg {                         pins = "gpio5";                         output-high;     }; And part of OOPS: [    0.673996] [] (gpiochip_get_data) from [] (sx150x_gpio_direction_output+0xd) [    0.683259] [] (sx150x_gpio_direction_output) from [] (sx150x_pinconf_set+0x) [    0.692796] [] (sx150x_pinconf_set) from [] (pinconf_apply_setting+0x39/0x7e) [    0.701635] [] (pinconf_apply_setting) from [] (pinctrl_commit_state+0xa5/0x) [    0.710648] [] (pinctrl_commit_state) from [] (pinctrl_enable+0xff/0x1d4) [    0.719139] [] (pinctrl_enable) from [] (sx150x_probe+0x1a3/0x358) [    0.727027] [] (sx150x_probe) from [] (i2c_device_probe+0x1bb/0x1dc) The problem is that sx150x_pinconf_set uses sx150x_gpio_direction_output but gpio is not setup yet. Patch below fixes it but I'm not sure whether is it correct. Link: https://lore.kernel.org/r/f32130bf-cfd4-b1bf-538c-dbc9ee2d947a@eaxlabs.cz Signed-off-by: Martin DEVERA Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-sx150x.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index b325a136ac48..c110f780407b 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -1154,12 +1154,6 @@ static int sx150x_probe(struct i2c_client *client, return ret; } - ret = pinctrl_enable(pctl->pctldev); - if (ret) { - dev_err(dev, "Failed to enable pinctrl device\n"); - return ret; - } - /* Register GPIO controller */ pctl->gpio.base = -1; pctl->gpio.ngpio = pctl->data->npins; @@ -1238,6 +1232,17 @@ static int sx150x_probe(struct i2c_client *client, if (ret) return ret; + /* + * Pin control functions need to be enabled AFTER registering the + * GPIO chip because sx150x_pinconf_set() calls + * sx150x_gpio_direction_output(). + */ + ret = pinctrl_enable(pctl->pctldev); + if (ret) { + dev_err(dev, "Failed to enable pinctrl device\n"); + return ret; + } + ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev), 0, 0, pctl->data->npins); if (ret) From 84f28fc38d2ff99e2ac623325ba37809da611b8e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 25 Aug 2020 16:33:48 +0200 Subject: [PATCH 35/78] pinctrl: devicetree: Keep deferring even on timeout driver_deferred_probe_check_state() may return -ETIMEDOUT instead of -EPROBE_DEFER after all built-in drivers have been probed. This can cause issues for built-in drivers that depend on resources provided by loadable modules. One such case happens on Tegra where I2C controllers are used during early boot to set up the system PMIC, so the I2C driver needs to be a built-in driver. At the same time, some instances of the I2C controller depend on the DPAUX hardware for pinmuxing. Since the DPAUX is handled by the display driver, which is usually not built-in, the pin control states will not become available until after the root filesystem has been mounted and the display driver loaded from it. Fixes: bec6c0ecb243 ("pinctrl: Remove use of driver_deferred_probe_check_state_continue()") Suggested-by: John Stultz Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20200825143348.1358679-1-thierry.reding@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/devicetree.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c index 5eff8c296552..3fb238714718 100644 --- a/drivers/pinctrl/devicetree.c +++ b/drivers/pinctrl/devicetree.c @@ -130,9 +130,8 @@ static int dt_to_map_one_config(struct pinctrl *p, if (!np_pctldev || of_node_is_root(np_pctldev)) { of_node_put(np_pctldev); ret = driver_deferred_probe_check_state(p->dev); - /* keep deferring if modules are enabled unless we've timed out */ - if (IS_ENABLED(CONFIG_MODULES) && !allow_default && - (ret == -ENODEV)) + /* keep deferring if modules are enabled */ + if (IS_ENABLED(CONFIG_MODULES) && !allow_default && ret < 0) ret = -EPROBE_DEFER; return ret; } From 7b9ec811752c17c4c6e70d296ef8aa205a7acacd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:22:08 +0200 Subject: [PATCH 36/78] dt-bindings: pinctrl: sh-pfc: Convert to json-schema Convert the Renesas Pin Function Controller (PFC) Device Tree binding documentation to json-schema. Document missing properties. Drop deprecated and obsolete #gpio-range-cells property. Update the example to match reality. Drop consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20200821112208.5295-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 188 ----------------- .../bindings/pinctrl/renesas,pfc.yaml | 193 ++++++++++++++++++ 2 files changed, 193 insertions(+), 188 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted file mode 100644 index d75476e24514..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ /dev/null @@ -1,188 +0,0 @@ -* Renesas Pin Function Controller (GPIO and Pin Mux/Config) - -The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, -R8A73A4 and R8A7740 it also acts as a GPIO controller. - - -Pin Control ------------ - -Required Properties: - - - compatible: should be one of the following. - - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller. - - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller. - - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller. - - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller. - - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller. - - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - - "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller. - - "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller. - - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. - - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller. - - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - - - reg: Base address and length of each memory resource used by the pin - controller hardware module. - -Optional properties: - - - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden - otherwise. Should be 3. - - - interrupts-extended: Specify the interrupts associated with external - IRQ pins. This property is mandatory when the PFC handles GPIOs and - forbidden otherwise. When specified, it must contain one interrupt per - external IRQ, sorted by external IRQ number. - -The PFC node also acts as a container for pin configuration nodes. Please refer -to pinctrl-bindings.txt in this directory for the definition of the term "pin -configuration node" and for the common pinctrl bindings used by client devices. - -Each pin configuration node represents a desired configuration for a pin, a -pin group, or a list of pins or pin groups. The configuration can include the -function to select on those pin(s) and pin configuration parameters (such as -pull-up and pull-down). - -Pin configuration nodes contain pin configuration properties, either directly -or grouped in child subnodes. Both pin muxing and configuration parameters can -be grouped in that way and referenced as a single pin configuration node by -client devices. - -A configuration node or subnode must reference at least one pin (through the -pins or pin groups properties) and contain at least a function or one -configuration parameter. When the function is present only pin groups can be -used to reference pins. - -All pin configuration nodes and subnodes names are ignored. All of those nodes -are parsed through phandles and processed purely based on their content. - -Pin Configuration Node Properties: - -- pins : An array of strings, each string containing the name of a pin. -- groups : An array of strings, each string containing the name of a pin - group. - -- function: A string containing the name of the function to mux to the pin - group(s) specified by the groups property. - - Valid values for pin, group and function names can be found in the group and - function arrays of the PFC data file corresponding to the SoC - (drivers/pinctrl/sh-pfc/pfc-*.c) - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For -pins that have a configurable I/O voltage, the power-source value should be the -nominal I/O voltage in millivolts. - - -GPIO ----- - -On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node. - -Required Properties: - - - gpio-controller: Marks the device node as a gpio controller. - - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -The syntax of the gpio specifier used by client nodes should be the following -with values derived from the SoC user manual. - - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - -On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. -Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml -for documentation of the GPIO device tree bindings on those platforms. - - -Examples --------- - -Example 1: SH73A0 (SH-Mobile AG5) pin controller node - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - }; - -Example 2: A GPIO LED node that references a GPIO - - #include - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - }; - }; - -Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps - for the MMCIF and SCIFA4 devices - - &pfc { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - mmcif_pins: mmcif { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - }; - -Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device - - &mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml new file mode 100644 index 000000000000..4efe117550bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Pin Function Controller (GPIO and Pin Mux/Config) + +maintainers: + - Geert Uytterhoeven + +description: + The Pin Function Controller (PFC) is a Pin Mux/Config controller. + On SH/R-Mobile SoCs it also acts as a GPIO controller. + +properties: + compatible: + enum: + - renesas,pfc-emev2 # EMMA Mobile EV2 + - renesas,pfc-r8a73a4 # R-Mobile APE6 + - renesas,pfc-r8a7740 # R-Mobile A1 + - renesas,pfc-r8a7742 # RZ/G1H + - renesas,pfc-r8a7743 # RZ/G1M + - renesas,pfc-r8a7744 # RZ/G1N + - renesas,pfc-r8a7745 # RZ/G1E + - renesas,pfc-r8a77470 # RZ/G1C + - renesas,pfc-r8a774a1 # RZ/G2M + - renesas,pfc-r8a774b1 # RZ/G2N + - renesas,pfc-r8a774c0 # RZ/G2E + - renesas,pfc-r8a774e1 # RZ/G2H + - renesas,pfc-r8a7778 # R-Car M1 + - renesas,pfc-r8a7779 # R-Car H1 + - renesas,pfc-r8a7790 # R-Car H2 + - renesas,pfc-r8a7791 # R-Car M2-W + - renesas,pfc-r8a7792 # R-Car V2H + - renesas,pfc-r8a7793 # R-Car M2-N + - renesas,pfc-r8a7794 # R-Car E2 + - renesas,pfc-r8a7795 # R-Car H3 + - renesas,pfc-r8a7796 # R-Car M3-W + - renesas,pfc-r8a77961 # R-Car M3-W+ + - renesas,pfc-r8a77965 # R-Car M3-N + - renesas,pfc-r8a77970 # R-Car V3M + - renesas,pfc-r8a77980 # R-Car V3H + - renesas,pfc-r8a77990 # R-Car E3 + - renesas,pfc-r8a77995 # R-Car D3 + - renesas,pfc-sh73a0 # SH-Mobile AG5 + + reg: + minItems: 1 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 16 + + interrupts-extended: + minItems: 32 + maxItems: 64 + description: + Specify the interrupts associated with external IRQ pins on SoCs where + the PFC acts as a GPIO controller. It must contain one interrupt per + external IRQ, sorted by external IRQ number. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + items: + enum: + - renesas,pfc-r8a73a4 + - renesas,pfc-r8a7740 + - renesas,pfc-sh73a0 +then: + required: + - interrupts-extended + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - power-domains + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + function: true + groups: true + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: + enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values + power-source: + enum: [ 1800, 3300 ] + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + + lcd0_mux { + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; + }; + + - | + pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0xe6060000 0x50c>; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", + "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2", + "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1"; + bias-pull-up; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + }; From aa5b0f7e0f7e8a05c5bd9bfab33d98699735762f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:40 +0900 Subject: [PATCH 37/78] pinctrl: sh-pfc: Tidy up Emma Mobile EV2 It is "Emma Mobile EV2" not "AV2". This patch tidies it up. Reported-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87lfi4y4re.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 7fdc7ed8bd2e..8b2b1e1a9047 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -66,7 +66,7 @@ config PINCTRL_SH_FUNC_GPIO This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 - bool "Emma Mobile AV2 pin control support" if COMPILE_TEST + bool "Emma Mobile EV2 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A73A4 bool "R-Mobile APE6 pin control support" if COMPILE_TEST From af028ecd546a71b4d3937b63e1b39707ef9c3b17 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:48 +0900 Subject: [PATCH 38/78] pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place Renesas related pinctrl CONFIGs are located in many places, which is confusing. This patch collects them into the same place, grouped in a new "Renesas pinctrl drivers" menu. This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com [geert: Update path in MAINTAINERS] Signed-off-by: Geert Uytterhoeven --- MAINTAINERS | 1 - drivers/pinctrl/Kconfig | 32 ------------------ drivers/pinctrl/Makefile | 3 -- drivers/pinctrl/sh-pfc/Kconfig | 36 +++++++++++++++++++++ drivers/pinctrl/sh-pfc/Makefile | 4 +++ drivers/pinctrl/{ => sh-pfc}/pinctrl-rza1.c | 8 ++--- drivers/pinctrl/{ => sh-pfc}/pinctrl-rza2.c | 4 +-- drivers/pinctrl/{ => sh-pfc}/pinctrl-rzn1.c | 6 ++-- 8 files changed, 49 insertions(+), 45 deletions(-) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rza1.c (99%) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rza2.c (99%) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rzn1.c (99%) diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..73242e16e327 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13690,7 +13690,6 @@ L: linux-renesas-soc@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc F: Documentation/devicetree/bindings/pinctrl/renesas,* -F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ PIN CONTROLLER - SAMSUNG diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8828613c4e0e..f63c5a04a3f7 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -213,38 +213,6 @@ config PINCTRL_ROCKCHIP select GENERIC_IRQ_CHIP select MFD_SYSCON -config PINCTRL_RZA1 - bool "Renesas RZ/A1 gpio and pinctrl driver" - depends on OF - depends on ARCH_R7S72100 || COMPILE_TEST - select GPIOLIB - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/A1 platforms. - -config PINCTRL_RZA2 - bool "Renesas RZ/A2 gpio and pinctrl driver" - depends on OF - depends on ARCH_R7S9210 || COMPILE_TEST - select GPIOLIB - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. - -config PINCTRL_RZN1 - bool "Renesas RZ/N1 pinctrl driver" - depends on OF - depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/N1 devices. - config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1731b2154df9..1da9f28aecbd 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -30,9 +30,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o -obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o -obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o -obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 8b2b1e1a9047..ff10bb2ed497 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -3,6 +3,8 @@ # Renesas SH and SH Mobile PINCTRL drivers # +menu "Renesas pinctrl drivers" + config PINCTRL_SH_PFC bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH @@ -53,6 +55,38 @@ config PINCTRL_SH_PFC help This enables pin control drivers for Renesas SuperH and ARM platforms +config PINCTRL_RZA1 + bool "RZ/A1 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S72100 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/A1 platforms. + +config PINCTRL_RZA2 + bool "RZ/A2 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S9210 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. + +config PINCTRL_RZN1 + bool "RZ/N1 pinctrl driver" + depends on OF + depends on ARCH_RZN1 || COMPILE_TEST + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/N1 devices. + config PINCTRL_SH_PFC_GPIO select GPIOLIB bool @@ -203,3 +237,5 @@ config PINCTRL_PFC_SH7786 config PINCTRL_PFC_SHX3 bool "SH-X3 pin control support" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO + +endmenu diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 7bb99187cd8e..0b5640cf457b 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -43,6 +43,10 @@ obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o +obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o +obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o +obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c similarity index 99% rename from drivers/pinctrl/pinctrl-rza1.c rename to drivers/pinctrl/sh-pfc/pinctrl-rza1.c index 511f232ab7bc..a0cb586a46b7 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c @@ -26,10 +26,10 @@ #include #include -#include "core.h" -#include "devicetree.h" -#include "pinconf.h" -#include "pinmux.h" +#include "../core.h" +#include "../devicetree.h" +#include "../pinconf.h" +#include "../pinmux.h" #define DRIVER_NAME "pinctrl-rza1" diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/sh-pfc/pinctrl-rza2.c similarity index 99% rename from drivers/pinctrl/pinctrl-rza2.c rename to drivers/pinctrl/sh-pfc/pinctrl-rza2.c index c5bf98c86b2b..32829eb9656c 100644 --- a/drivers/pinctrl/pinctrl-rza2.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza2.c @@ -17,8 +17,8 @@ #include #include -#include "core.h" -#include "pinmux.h" +#include "../core.h" +#include "../pinmux.h" #define DRIVER_NAME "pinctrl-rza2" diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c similarity index 99% rename from drivers/pinctrl/pinctrl-rzn1.c rename to drivers/pinctrl/sh-pfc/pinctrl-rzn1.c index 39538d40dbf3..ef5fb25b6016 100644 --- a/drivers/pinctrl/pinctrl-rzn1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c @@ -17,9 +17,9 @@ #include #include #include -#include "core.h" -#include "pinconf.h" -#include "pinctrl-utils.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" /* Field positions and masks in the pinmux registers */ #define RZN1_L1_PIN_DRIVE_STRENGTH 10 From 16261dcd7cd17409b3f1235b0b89a805338eac28 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:52 +0900 Subject: [PATCH 39/78] pinctrl: sh-pfc: Align driver description title Now, Renesas Pin Control drivers are under menu, but current descriptions are not aligned. This patch aligns them. - RZ/A2 gpio and pinctrl driver - RZ/N1 pinctrl driver - Emma Mobile EV2 pin control support - R-Mobile APE6 pin control support - R-Mobile A1 pin control support - RZ/G1H pin control support - RZ/G1M pin control support + pin control support for RZ/A2 + pin control support for RZ/N1 + pin control support for Emma Mobile EV2 + pin control support for R-Mobile APE6 + pin control support for R-Mobile A1 + pin control support for RZ/G1H + pin control support for RZ/G1M Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87imd8y4r2.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 88 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index ff10bb2ed497..86e4d062ef99 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -56,7 +56,7 @@ config PINCTRL_SH_PFC This enables pin control drivers for Renesas SuperH and ARM platforms config PINCTRL_RZA1 - bool "RZ/A1 gpio and pinctrl driver" + bool "pin control support for RZ/A1" depends on OF depends on ARCH_R7S72100 || COMPILE_TEST select GPIOLIB @@ -67,7 +67,7 @@ config PINCTRL_RZA1 This selects pinctrl driver for Renesas RZ/A1 platforms. config PINCTRL_RZA2 - bool "RZ/A2 gpio and pinctrl driver" + bool "pin control support for RZ/A2" depends on OF depends on ARCH_R7S9210 || COMPILE_TEST select GPIOLIB @@ -78,7 +78,7 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZN1 - bool "RZ/N1 pinctrl driver" + bool "pin control support for RZ/N1" depends on OF depends on ARCH_RZN1 || COMPILE_TEST select GENERIC_PINCTRL_GROUPS @@ -100,142 +100,142 @@ config PINCTRL_SH_FUNC_GPIO This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 - bool "Emma Mobile EV2 pin control support" if COMPILE_TEST + bool "pin control support for Emma Mobile EV2" if COMPILE_TEST config PINCTRL_PFC_R8A73A4 - bool "R-Mobile APE6 pin control support" if COMPILE_TEST + bool "pin control support for R-Mobile APE6" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7740 - bool "R-Mobile A1 pin control support" if COMPILE_TEST + bool "pin control support for R-Mobile A1" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7742 - bool "RZ/G1H pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1H" if COMPILE_TEST config PINCTRL_PFC_R8A7743 - bool "RZ/G1M pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1M" if COMPILE_TEST config PINCTRL_PFC_R8A7744 - bool "RZ/G1N pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1N" if COMPILE_TEST config PINCTRL_PFC_R8A7745 - bool "RZ/G1E pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1E" if COMPILE_TEST config PINCTRL_PFC_R8A77470 - bool "RZ/G1C pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1C" if COMPILE_TEST config PINCTRL_PFC_R8A774A1 - bool "RZ/G2M pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2M" if COMPILE_TEST config PINCTRL_PFC_R8A774B1 - bool "RZ/G2N pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2N" if COMPILE_TEST config PINCTRL_PFC_R8A774C0 - bool "RZ/G2E pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2E" if COMPILE_TEST config PINCTRL_PFC_R8A774E1 - bool "RZ/G2H pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2H" if COMPILE_TEST config PINCTRL_PFC_R8A7778 - bool "R-Car M1A pin control support" if COMPILE_TEST + bool "pin control support for R-Car M1A" if COMPILE_TEST config PINCTRL_PFC_R8A7779 - bool "R-Car H1 pin control support" if COMPILE_TEST + bool "pin control support for R-Car H1" if COMPILE_TEST config PINCTRL_PFC_R8A7790 - bool "R-Car H2 pin control support" if COMPILE_TEST + bool "pin control support for R-Car H2" if COMPILE_TEST config PINCTRL_PFC_R8A7791 - bool "R-Car M2-W pin control support" if COMPILE_TEST + bool "pin control support for R-Car M2-W" if COMPILE_TEST config PINCTRL_PFC_R8A7792 - bool "R-Car V2H pin control support" if COMPILE_TEST + bool "pin control support for R-Car V2H" if COMPILE_TEST config PINCTRL_PFC_R8A7793 - bool "R-Car M2-N pin control support" if COMPILE_TEST + bool "pin control support for R-Car M2-N" if COMPILE_TEST config PINCTRL_PFC_R8A7794 - bool "R-Car E2 pin control support" if COMPILE_TEST + bool "pin control support for R-Car E2" if COMPILE_TEST config PINCTRL_PFC_R8A77950 - bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST + bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST config PINCTRL_PFC_R8A77951 - bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST + bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST config PINCTRL_PFC_R8A77960 - bool "R-Car M3-W pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-W" if COMPILE_TEST config PINCTRL_PFC_R8A77961 - bool "R-Car M3-W+ pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-W+" if COMPILE_TEST config PINCTRL_PFC_R8A77965 - bool "R-Car M3-N pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-N" if COMPILE_TEST config PINCTRL_PFC_R8A77970 - bool "R-Car V3M pin control support" if COMPILE_TEST + bool "pin control support for R-Car V3M" if COMPILE_TEST config PINCTRL_PFC_R8A77980 - bool "R-Car V3H pin control support" if COMPILE_TEST + bool "pin control support for R-Car V3H" if COMPILE_TEST config PINCTRL_PFC_R8A77990 - bool "R-Car E3 pin control support" if COMPILE_TEST + bool "pin control support for R-Car E3" if COMPILE_TEST config PINCTRL_PFC_R8A77995 - bool "R-Car D3 pin control support" if COMPILE_TEST + bool "pin control support for R-Car D3" if COMPILE_TEST config PINCTRL_PFC_SH7203 - bool "SH7203 pin control support" if COMPILE_TEST + bool "pin control support for SH7203" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7264 - bool "SH7264 pin control support" if COMPILE_TEST + bool "pin control support for SH7264" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7269 - bool "SH7269 pin control support" if COMPILE_TEST + bool "pin control support for SH7269" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH73A0 - bool "SH-Mobile AG5 pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile AG5" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO select REGULATOR config PINCTRL_PFC_SH7720 - bool "SH7720 pin control support" if COMPILE_TEST + bool "pin control support for SH7720" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7722 - bool "SH7722 pin control support" if COMPILE_TEST + bool "pin control support for SH7722" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7723 - bool "SH-Mobile R2 pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile R2" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7724 - bool "SH-Mobile R2R pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile R2R" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7734 - bool "SH7734 pin control support" if COMPILE_TEST + bool "pin control support for SH7734" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7757 - bool "SH7757 pin control support" if COMPILE_TEST + bool "pin control support for SH7757" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7785 - bool "SH7785 pin control support" if COMPILE_TEST + bool "pin control support for SH7785" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7786 - bool "SH7786 pin control support" if COMPILE_TEST + bool "pin control support for SH7786" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SHX3 - bool "SH-X3 pin control support" if COMPILE_TEST + bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO endmenu From d89a08f52b0dd30d8e13c91886788cd42333dba7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:56 +0900 Subject: [PATCH 40/78] pinctrl: sh-pfc: Tidy up driver description title Sort each driver by description title in alphabetical order. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87h7ssy4qy.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 202 ++++++++++++++++----------------- 1 file changed, 101 insertions(+), 101 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 86e4d062ef99..2cff88684f36 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -55,6 +55,77 @@ config PINCTRL_SH_PFC help This enables pin control drivers for Renesas SuperH and ARM platforms +config PINCTRL_SH_PFC_GPIO + select GPIOLIB + bool + help + This enables pin control and GPIO drivers for SH/SH Mobile platforms + +config PINCTRL_SH_FUNC_GPIO + select PINCTRL_SH_PFC_GPIO + bool + help + This enables legacy function GPIOs for SH platforms + +config PINCTRL_PFC_EMEV2 + bool "pin control support for Emma Mobile EV2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77995 + bool "pin control support for R-Car D3" if COMPILE_TEST + +config PINCTRL_PFC_R8A7794 + bool "pin control support for R-Car E2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77990 + bool "pin control support for R-Car E3" if COMPILE_TEST + +config PINCTRL_PFC_R8A7779 + bool "pin control support for R-Car H1" if COMPILE_TEST + +config PINCTRL_PFC_R8A7790 + bool "pin control support for R-Car H2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77950 + bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST + +config PINCTRL_PFC_R8A77951 + bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST + +config PINCTRL_PFC_R8A7778 + bool "pin control support for R-Car M1A" if COMPILE_TEST + +config PINCTRL_PFC_R8A7793 + bool "pin control support for R-Car M2-N" if COMPILE_TEST + +config PINCTRL_PFC_R8A7791 + bool "pin control support for R-Car M2-W" if COMPILE_TEST + +config PINCTRL_PFC_R8A77965 + bool "pin control support for R-Car M3-N" if COMPILE_TEST + +config PINCTRL_PFC_R8A77960 + bool "pin control support for R-Car M3-W" if COMPILE_TEST + +config PINCTRL_PFC_R8A77961 + bool "pin control support for R-Car M3-W+" if COMPILE_TEST + +config PINCTRL_PFC_R8A7792 + bool "pin control support for R-Car V2H" if COMPILE_TEST + +config PINCTRL_PFC_R8A77980 + bool "pin control support for R-Car V3H" if COMPILE_TEST + +config PINCTRL_PFC_R8A77970 + bool "pin control support for R-Car V3M" if COMPILE_TEST + +config PINCTRL_PFC_R8A7740 + bool "pin control support for R-Mobile A1" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + +config PINCTRL_PFC_R8A73A4 + bool "pin control support for R-Mobile APE6" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + config PINCTRL_RZA1 bool "pin control support for RZ/A1" depends on OF @@ -77,38 +148,11 @@ config PINCTRL_RZA2 help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. -config PINCTRL_RZN1 - bool "pin control support for RZ/N1" - depends on OF - depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/N1 devices. +config PINCTRL_PFC_R8A77470 + bool "pin control support for RZ/G1C" if COMPILE_TEST -config PINCTRL_SH_PFC_GPIO - select GPIOLIB - bool - help - This enables pin control and GPIO drivers for SH/SH Mobile platforms - -config PINCTRL_SH_FUNC_GPIO - select PINCTRL_SH_PFC_GPIO - bool - help - This enables legacy function GPIOs for SH platforms - -config PINCTRL_PFC_EMEV2 - bool "pin control support for Emma Mobile EV2" if COMPILE_TEST - -config PINCTRL_PFC_R8A73A4 - bool "pin control support for R-Mobile APE6" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO - -config PINCTRL_PFC_R8A7740 - bool "pin control support for R-Mobile A1" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7745 + bool "pin control support for RZ/G1E" if COMPILE_TEST config PINCTRL_PFC_R8A7742 bool "pin control support for RZ/G1H" if COMPILE_TEST @@ -119,11 +163,11 @@ config PINCTRL_PFC_R8A7743 config PINCTRL_PFC_R8A7744 bool "pin control support for RZ/G1N" if COMPILE_TEST -config PINCTRL_PFC_R8A7745 - bool "pin control support for RZ/G1E" if COMPILE_TEST +config PINCTRL_PFC_R8A774C0 + bool "pin control support for RZ/G2E" if COMPILE_TEST -config PINCTRL_PFC_R8A77470 - bool "pin control support for RZ/G1C" if COMPILE_TEST +config PINCTRL_PFC_R8A774E1 + bool "pin control support for RZ/G2H" if COMPILE_TEST config PINCTRL_PFC_R8A774A1 bool "pin control support for RZ/G2M" if COMPILE_TEST @@ -131,59 +175,15 @@ config PINCTRL_PFC_R8A774A1 config PINCTRL_PFC_R8A774B1 bool "pin control support for RZ/G2N" if COMPILE_TEST -config PINCTRL_PFC_R8A774C0 - bool "pin control support for RZ/G2E" if COMPILE_TEST - -config PINCTRL_PFC_R8A774E1 - bool "pin control support for RZ/G2H" if COMPILE_TEST - -config PINCTRL_PFC_R8A7778 - bool "pin control support for R-Car M1A" if COMPILE_TEST - -config PINCTRL_PFC_R8A7779 - bool "pin control support for R-Car H1" if COMPILE_TEST - -config PINCTRL_PFC_R8A7790 - bool "pin control support for R-Car H2" if COMPILE_TEST - -config PINCTRL_PFC_R8A7791 - bool "pin control support for R-Car M2-W" if COMPILE_TEST - -config PINCTRL_PFC_R8A7792 - bool "pin control support for R-Car V2H" if COMPILE_TEST - -config PINCTRL_PFC_R8A7793 - bool "pin control support for R-Car M2-N" if COMPILE_TEST - -config PINCTRL_PFC_R8A7794 - bool "pin control support for R-Car E2" if COMPILE_TEST - -config PINCTRL_PFC_R8A77950 - bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST - -config PINCTRL_PFC_R8A77951 - bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST - -config PINCTRL_PFC_R8A77960 - bool "pin control support for R-Car M3-W" if COMPILE_TEST - -config PINCTRL_PFC_R8A77961 - bool "pin control support for R-Car M3-W+" if COMPILE_TEST - -config PINCTRL_PFC_R8A77965 - bool "pin control support for R-Car M3-N" if COMPILE_TEST - -config PINCTRL_PFC_R8A77970 - bool "pin control support for R-Car V3M" if COMPILE_TEST - -config PINCTRL_PFC_R8A77980 - bool "pin control support for R-Car V3H" if COMPILE_TEST - -config PINCTRL_PFC_R8A77990 - bool "pin control support for R-Car E3" if COMPILE_TEST - -config PINCTRL_PFC_R8A77995 - bool "pin control support for R-Car D3" if COMPILE_TEST +config PINCTRL_RZN1 + bool "pin control support for RZ/N1" + depends on OF + depends on ARCH_RZN1 || COMPILE_TEST + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/N1 devices. config PINCTRL_PFC_SH7203 bool "pin control support for SH7203" if COMPILE_TEST @@ -197,11 +197,6 @@ config PINCTRL_PFC_SH7269 bool "pin control support for SH7269" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO -config PINCTRL_PFC_SH73A0 - bool "pin control support for SH-Mobile AG5" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO - select REGULATOR - config PINCTRL_PFC_SH7720 bool "pin control support for SH7720" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO @@ -210,14 +205,6 @@ config PINCTRL_PFC_SH7722 bool "pin control support for SH7722" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO -config PINCTRL_PFC_SH7723 - bool "pin control support for SH-Mobile R2" if COMPILE_TEST - select PINCTRL_SH_FUNC_GPIO - -config PINCTRL_PFC_SH7724 - bool "pin control support for SH-Mobile R2R" if COMPILE_TEST - select PINCTRL_SH_FUNC_GPIO - config PINCTRL_PFC_SH7734 bool "pin control support for SH7734" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO @@ -234,6 +221,19 @@ config PINCTRL_PFC_SH7786 bool "pin control support for SH7786" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO +config PINCTRL_PFC_SH73A0 + bool "pin control support for SH-Mobile AG5" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + select REGULATOR + +config PINCTRL_PFC_SH7723 + bool "pin control support for SH-Mobile R2" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO + +config PINCTRL_PFC_SH7724 + bool "pin control support for SH-Mobile R2R" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO + config PINCTRL_PFC_SHX3 bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO From a4eb6afa7c2c3795ec693cd806fd69593c9ecca7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:14:01 +0200 Subject: [PATCH 41/78] pinctrl: rza1: Switch to using "output-enable" For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 425562429d4f3b13 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by: Geert Uytterhoeven Reviewed-by: Chris Brandt Acked-by: Jacopo Mondi Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111401.4021-1-geert+renesas@glider.be --- .../devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt | 5 ++--- drivers/pinctrl/sh-pfc/pinctrl-rza1.c | 3 ++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt index fd3696eb36bf..38cdd23d3498 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -117,10 +117,9 @@ function or a GPIO controller alternatively. - input-enable: enable input bufer for pins requiring software driven IO input operations. - - output-high: + - output-enable: enable output buffer for pins requiring software driven IO output - operations. output-low can be used alternatively, as line value is - ignored by the driver. + operations. The hardware reference manual specifies when a pin has to be configured to work in bi-directional mode and when the IO direction has to be specified diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c index a0cb586a46b7..15dd007700c2 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c @@ -928,7 +928,8 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, case PIN_CONFIG_INPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_INPUT; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ + case PIN_CONFIG_OUTPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; default: break; From d4691b7f6231a022f20028ea27b6c49466b2acd6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:11:27 +0200 Subject: [PATCH 42/78] dt-bindings: pinctrl: renesas,rza2-pinctrl: Fix pin controller node name According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111127.3771-1-geert+renesas@glider.be --- .../devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml index b7911a994f3a..ce1f7343788f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -84,7 +84,7 @@ additionalProperties: false examples: - | #include - pinctrl: pin-controller@fcffe000 { + pinctrl: pinctrl@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; From 5398b2fa464722a3bb3cf4c264a19ac765974d98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:19:56 +0200 Subject: [PATCH 43/78] dt-bindings: pinctrl: rza1: Convert to json-schema Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821111956.4989-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 222 ------------------ .../bindings/pinctrl/renesas,rza1-ports.yaml | 190 +++++++++++++++ 2 files changed, 190 insertions(+), 222 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted file mode 100644 index 38cdd23d3498..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ /dev/null @@ -1,222 +0,0 @@ -Renesas RZ/A1 combined Pin and GPIO controller - -The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, -named "Ports" in the hardware reference manual. -Pin multiplexing and GPIO configuration is performed on a per-pin basis -writing configuration values to per-port register sets. -Each "port" features up to 16 pins, each of them configurable for GPIO -function (port mode) or in alternate function mode. -Up to 8 different alternate function modes exist for each single pin. - -Pin controller node -------------------- - -Required properties: - - compatible: should be: - - "renesas,r7s72100-ports": for RZ/A1H - - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M - - "renesas,r7s72102-ports": for RZ/A1L - - - reg - address base and length of the memory area where the pin controller - hardware is mapped to. - -Example: -Pin controller node for RZ/A1H SoC (r7s72100) - -pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; -}; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function or a GPIO controller alternatively. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - A few alternate function require special pin configuration flags to be - supplied along with the alternate function configuration number. - The hardware reference manual specifies when a pin function requires - "software IO driven" mode to be specified. To do so use the generic - properties from the header file - to instruct the pin controller to perform the desired pin configuration - operation. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the second format when pins part of the same logical group need to have - different generic pin configuration flags applied. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Helper macros to ease assembling the pin index from its position - (port where it sits on and pin number) and alternate function identifier - are provided by the pin controller header file at: - - Integers values in "pinmux" argument list are assembled as: - ((PORT * 16 + PIN) | MUX_FUNC << 16) - - Optional generic properties: - - input-enable: - enable input bufer for pins requiring software driven IO input - operations. - - output-enable: - enable output buffer for pins requiring software driven IO output - operations. - - The hardware reference manual specifies when a pin has to be configured to - work in bi-directional mode and when the IO direction has to be specified - by software. Bi-directional pins are managed by the pin controller driver - internally, while software driven IO direction has to be explicitly - selected when multiple options are available. - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - scif2_pins: serial2 { - pinmux = , ; - }; - }; - - Pin #0 on port #3 is configured as alternate function #6. - Pin #2 on port #3 is configured as alternate function #4. - - Example 2: - I2c master: both SDA and SCL pins need bi-directional operations - - &pinctrl { - i2c2_pins: i2c2 { - pinmux = , ; - }; - }; - - Pin #4 on port #1 is configured as alternate function #1. - Pin #5 on port #1 is configured as alternate function #1. - Both need to work in bi-directional mode, the driver manages this internally. - - Example 3: - Multi-function timer input and output compare pins. - Configure TIOC0A as software driven input and TIOC0B as software driven - output. - - &pinctrl { - tioc0_pins: tioc0 { - tioc0_input_pins { - pinumx = ; - input-enable; - }; - - tioc0_output_pins { - pinmux = ; - output-enable; - }; - }; - }; - - &tioc0 { - ... - pinctrl-0 = <&tioc0_pins>; - ... - }; - - Pin #0 on port #4 is configured as alternate function #2 with IO direction - specified by software as input. - Pin #1 on port #4 is configured as alternate function #1 with IO direction - specified by software as output. - -- GPIO controller sub-nodes: - Each port of the r7s72100 pin controller hardware is itself a GPIO controller. - Different SoCs have different numbers of available pins per port, but - generally speaking, each of them can be configured in GPIO ("port") mode - on this hardware. - Describe GPIO controllers using sub-nodes with the following properties. - - Required properties: - - gpio-controller - empty property as defined by the GPIO bindings documentation. - - #gpio-cells - number of cells required to identify and configure a GPIO. - Shall be 2. - - gpio-ranges - Describes a GPIO controller specifying its specific pin base, the pin - base in the global pin numbering space, and the number of controlled - pins, as defined by the GPIO bindings documentation. Refer to - Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed - description. - - Example: - A GPIO controller node, controlling 16 pins indexed from 0. - The GPIO controller base in the global pin indexing space is pin 48, thus - pins [0 - 15] on this controller map to pins [48 - 63] in the global pin - indexing space. - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - A device node willing to use pins controlled by this GPIO controller, shall - refer to it as follows: - - led1 { - gpios = <&port3 10 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml new file mode 100644 index 000000000000..7f80578dc229 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A1 combined Pin and GPIO controller + +maintainers: + - Jacopo Mondi + - Geert Uytterhoeven + +description: + The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO + controller, named "Ports" in the hardware reference manual. + Pin multiplexing and GPIO configuration is performed on a per-pin basis + writing configuration values to per-port register sets. + Each "port" features up to 16 pins, each of them configurable for GPIO + function (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - const: renesas,r7s72100-ports # RZ/A1H + - items: + - const: renesas,r7s72101-ports # RZ/A1M + - const: renesas,r7s72100-ports # fallback + - const: renesas,r7s72102-ports # RZ/A1L + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + "^gpio-[0-9]*$": + type: object + + description: + Each port of the r7s72100 pin controller hardware is itself a GPIO + controller. + Different SoCs have different numbers of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe GPIO controllers using sub-nodes with the following properties. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - gpio-ranges + + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + A few alternate function require special pin configuration flags to be + supplied along with the alternate function configuration number. + The hardware reference manual specifies when a pin function requires + "software IO driven" mode to be specified. To do so use the generic + properties from the header + file to instruct the pin controller to perform the desired pin + configuration operation. + The hardware reference manual specifies when a pin has to be configured + to work in bi-directional mode and when the IO direction has to be + specified by software. Bi-directional pins must be managed by the pin + controller driver internally, while software driven IO direction has to + be explicitly selected when multiple options are available. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function + identifier are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 16 + PIN) | MUX_FUNC << 16) + + phandle: true + input-enable: true + output-enable: true + + required: + - pinmux + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + /* + * A GPIO controller node, controlling 16 pins indexed from 0. + * The GPIO controller base in the global pin indexing space is pin + * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] + * in the global pin indexing space. + */ + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + * Pin #0 on port #3 is configured as alternate function #6. + * Pin #2 on port #3 is configured as alternate function #4. + */ + scif2_pins: serial2 { + pinmux = , ; + }; + + + /* + * I2c master: both SDA and SCL pins need bi-directional operations + * Pin #4 on port #1 is configured as alternate function #1. + * Pin #5 on port #1 is configured as alternate function #1. + * Both need to work in bi-directional mode, the driver must manage + * this internally. + */ + i2c2_pins: i2c2 { + pinmux = , ; + }; + + + /* + * Multi-function timer input and output compare pins. + */ + tioc0_pins: tioc0 { + /* + * Configure TIOC0A as software driven input + * Pin #0 on port #4 is configured as alternate function #2 + * with IO direction specified by software as input. + */ + tioc0_input_pins { + pinmux = ; + input-enable; + }; + + /* + * Configure TIOC0B as software driven output + * Pin #1 on port #4 is configured as alternate function #1 + * with IO direction specified by software as output. + */ + tioc0_output_pins { + pinmux = ; + output-enable; + }; + }; + }; From 5f76771a4a4514277f4618ba2fe20cb1d9ed5afd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:20:59 +0200 Subject: [PATCH 44/78] dt-bindings: pinctrl: rzn1: Convert to json-schema Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Tested-by: Gareth Williams Reviewed-by: Gareth Williams Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821112059.5133-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rzn1-pinctrl.txt | 153 ------------------ .../pinctrl/renesas,rzn1-pinctrl.yaml | 129 +++++++++++++++ 2 files changed, 129 insertions(+), 153 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt deleted file mode 100644 index 25e53acd523e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt +++ /dev/null @@ -1,153 +0,0 @@ -Renesas RZ/N1 SoC Pinctrl node description. - -Pin controller node -------------------- -Required properties: -- compatible: SoC-specific compatible string "renesas,-pinctrl" - followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible - strings must be one of: - "renesas,r9a06g032-pinctrl" for RZ/N1D - "renesas,r9a06g033-pinctrl" for RZ/N1S -- reg: Address base and length of the memory area where the pin controller - hardware is mapped to. -- clocks: phandle for the clock, see the description of clock-names below. -- clock-names: Contains the name of the clock: - "bus", the bus clock, sometimes described as pclk, for register accesses. - -Example: - pinctrl: pin-controller@40067000 { - compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; - reg = <0x40067000 0x1000>, <0x51000000 0x480>; - clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; - clock-names = "bus"; - }; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - node-3 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the latter two formats when pins part of the same logical group need to - have different generic pin configuration flags applied. Note that the generic - pinconfig in node-3 does not apply to the sub-nodes. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Integers values in the "pinmux" argument list are assembled as: - (PIN | MUX_FUNC << 8) - where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is - one of the alternate function identifiers defined in: - - These identifiers collapse the IO Multiplex Configuration Level 1 and - Level 2 numbers that are detailed in the hardware reference manual into a - single number. The identifiers for Level 2 are simply offset by 10. - Additional identifiers are provided to specify the MDIO source peripheral. - - Optional generic pinconf properties: - - bias-disable - disable any pin bias - - bias-pull-up - pull up the pin with 50 KOhm - - bias-pull-down - pull down the pin with 50 KOhm - - bias-high-impedance - high impedance mode - - drive-strength - sink or source at most 4, 6, 8 or 12 mA - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = < - RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ - RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ - >; - }; - }; - - Example 2: - Here we set the pull up on the RXD pin of the UART. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = ; /* TXD */ - - pins_uart6_rx { - pinmux = ; /* RXD */ - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml new file mode 100644 index 000000000000..4a43af0d6e02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Pin Controller + +maintainers: + - Gareth Williams + - Geert Uytterhoeven + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-pinctrl # RZ/N1D + - renesas,r9a06g033-pinctrl # RZ/N1S + - const: renesas,rzn1-pinctrl # Generic RZ/N1 + + reg: + items: + - description: GPIO Multiplexing Level1 Register Block + - description: GPIO Multiplexing Level2 Register Block + + clocks: + maxItems: 1 + + clock-names: + const: bus + description: + The bus clock, sometimes described as pclk, for register accesses. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Integers values in the "pinmux" argument list are assembled as: + (PIN | MUX_FUNC << 8) + where PIN directly corresponds to the pl_gpio pin number and + MUX_FUNC is one of the alternate function identifiers defined in: + + These identifiers collapse the IO Multiplex Configuration Level 1 + and Level 2 numbers that are detailed in the hardware reference + manual into a single number. The identifiers for Level 2 are simply + offset by 10. Additional identifiers are provided to specify the + MDIO source peripheral. + + phandle: true + bias-disable: true + bias-pull-up: + description: Pull up the pin with 50 kOhm + bias-pull-down: + description: Pull down the pin with 50 kOhm + bias-high-impedance: true + drive-strength: + enum: [ 4, 6, 8, 12 ] + + required: + - pinmux + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + #include + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + */ + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + }; + + /* + * Set the pull-up on the RXD pin of the UART. + */ + pins_uart0_alt: pins_uart0_alt { + pinmux = ; + + pins_uart6_rx { + pinmux = ; + bias-pull-up; + }; + }; + }; From 1308fb4e4eae14e6189dece3b7cf5b5f453c5d02 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:32 +0200 Subject: [PATCH 45/78] pinctrl: rzn1: Do not select GENERIC_PIN{CTRL_GROUPS,MUX_FUNCTIONS} The RZ/N1 pin control driver does not use pin groups or pin functions, so there is no need to select GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-2-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 2cff88684f36..9eb793cb464b 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -179,8 +179,6 @@ config PINCTRL_RZN1 bool "pin control support for RZ/N1" depends on OF depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help This selects pinctrl driver for Renesas RZ/N1 devices. From 077365a941166f3a7f5894017f9d26d17cdec00e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:33 +0200 Subject: [PATCH 46/78] pinctrl: Rename sh-pfc to renesas The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be --- MAINTAINERS | 4 ++-- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/{sh-pfc => renesas}/Kconfig | 2 +- drivers/pinctrl/{sh-pfc => renesas}/Makefile | 4 ++-- drivers/pinctrl/{sh-pfc => renesas}/core.c | 0 drivers/pinctrl/{sh-pfc => renesas}/core.h | 0 drivers/pinctrl/{sh-pfc => renesas}/gpio.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-emev2.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a73a4.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7740.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77470.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7778.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7779.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7790.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7791.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7792.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7794.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77950.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77951.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7796.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77965.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77970.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77980.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77990.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77995.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7203.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7264.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7269.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh73a0.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7720.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7722.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7723.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7724.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7734.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7757.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7785.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7786.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-shx3.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza1.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza2.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rzn1.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl.c | 0 drivers/pinctrl/{sh-pfc => renesas}/sh_pfc.h | 0 44 files changed, 13 insertions(+), 13 deletions(-) rename drivers/pinctrl/{sh-pfc => renesas}/Kconfig (99%) rename drivers/pinctrl/{sh-pfc => renesas}/Makefile (96%) rename drivers/pinctrl/{sh-pfc => renesas}/core.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/core.h (100%) rename drivers/pinctrl/{sh-pfc => renesas}/gpio.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-emev2.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a73a4.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7740.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77470.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7778.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7779.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7790.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7791.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7792.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7794.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77950.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77951.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7796.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77965.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77970.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77980.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77990.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77995.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7203.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7264.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7269.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh73a0.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7720.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7722.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7723.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7724.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7734.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7757.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7785.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7786.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-shx3.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza1.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza2.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rzn1.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/sh_pfc.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 73242e16e327..02c149ce75c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13688,9 +13688,9 @@ PIN CONTROLLER - RENESAS M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org S: Supported -T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc +T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl F: Documentation/devicetree/bindings/pinctrl/renesas,* -F: drivers/pinctrl/sh-pfc/ +F: drivers/pinctrl/renesas/ PIN CONTROLLER - SAMSUNG M: Tomasz Figa diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f63c5a04a3f7..6ca1a6fc9756 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -383,8 +383,8 @@ source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" +source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" -source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1da9f28aecbd..113be648658f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -59,8 +59,8 @@ obj-y += nomadik/ obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ -obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/renesas/Kconfig similarity index 99% rename from drivers/pinctrl/sh-pfc/Kconfig rename to drivers/pinctrl/renesas/Kconfig index 9eb793cb464b..fc1f2611063b 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -5,7 +5,7 @@ menu "Renesas pinctrl drivers" -config PINCTRL_SH_PFC +config PINCTRL_RENESAS bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH select PINMUX diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/renesas/Makefile similarity index 96% rename from drivers/pinctrl/sh-pfc/Makefile rename to drivers/pinctrl/renesas/Makefile index 0b5640cf457b..c96008c9ab59 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o +obj-$(CONFIG_PINCTRL_RENESAS) += core.o pinctrl.o obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o -obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o +obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/renesas/core.c similarity index 100% rename from drivers/pinctrl/sh-pfc/core.c rename to drivers/pinctrl/renesas/core.c diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/renesas/core.h similarity index 100% rename from drivers/pinctrl/sh-pfc/core.h rename to drivers/pinctrl/renesas/core.h diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/renesas/gpio.c similarity index 100% rename from drivers/pinctrl/sh-pfc/gpio.c rename to drivers/pinctrl/renesas/gpio.c diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-emev2.c rename to drivers/pinctrl/renesas/pfc-emev2.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a73a4.c rename to drivers/pinctrl/renesas/pfc-r8a73a4.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7740.c rename to drivers/pinctrl/renesas/pfc-r8a7740.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77470.c rename to drivers/pinctrl/renesas/pfc-r8a77470.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7778.c rename to drivers/pinctrl/renesas/pfc-r8a7778.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7779.c rename to drivers/pinctrl/renesas/pfc-r8a7779.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7790.c rename to drivers/pinctrl/renesas/pfc-r8a7790.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7791.c rename to drivers/pinctrl/renesas/pfc-r8a7791.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7792.c rename to drivers/pinctrl/renesas/pfc-r8a7792.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7794.c rename to drivers/pinctrl/renesas/pfc-r8a7794.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77950.c rename to drivers/pinctrl/renesas/pfc-r8a77950.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77951.c rename to drivers/pinctrl/renesas/pfc-r8a77951.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7796.c rename to drivers/pinctrl/renesas/pfc-r8a7796.c index a2496baca85d..55f0344a3d3e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -4,7 +4,7 @@ * * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77965.c rename to drivers/pinctrl/renesas/pfc-r8a77965.c index 6616f5210b9d..7a50b9b69a7d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Jacopo Mondi * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77970.c rename to drivers/pinctrl/renesas/pfc-r8a77970.c index 9f7d9c9238fc..e8a0fc468eb2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -5,7 +5,7 @@ * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77980.c rename to drivers/pinctrl/renesas/pfc-r8a77980.c index 1055f9853404..ebd07bebaeeb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018 Cogent Embedded, Inc. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77990.c rename to drivers/pinctrl/renesas/pfc-r8a77990.c index c926a59dd21c..aed04a4c6116 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -4,7 +4,7 @@ * * Copyright (C) 2018-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R8A7796 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77995.c rename to drivers/pinctrl/renesas/pfc-r8a77995.c index c10b756476b1..672251d86c2d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -4,7 +4,7 @@ * * Copyright (C) 2017 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7203.c rename to drivers/pinctrl/renesas/pfc-sh7203.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7264.c rename to drivers/pinctrl/renesas/pfc-sh7264.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7269.c rename to drivers/pinctrl/renesas/pfc-sh7269.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh73a0.c rename to drivers/pinctrl/renesas/pfc-sh73a0.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7720.c rename to drivers/pinctrl/renesas/pfc-sh7720.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7722.c rename to drivers/pinctrl/renesas/pfc-sh7722.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7723.c rename to drivers/pinctrl/renesas/pfc-sh7723.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7724.c rename to drivers/pinctrl/renesas/pfc-sh7724.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7734.c rename to drivers/pinctrl/renesas/pfc-sh7734.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/renesas/pfc-sh7757.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7757.c rename to drivers/pinctrl/renesas/pfc-sh7757.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/renesas/pfc-sh7785.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7785.c rename to drivers/pinctrl/renesas/pfc-sh7785.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/renesas/pfc-sh7786.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7786.c rename to drivers/pinctrl/renesas/pfc-sh7786.c diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/renesas/pfc-shx3.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-shx3.c rename to drivers/pinctrl/renesas/pfc-shx3.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rza1.c rename to drivers/pinctrl/renesas/pinctrl-rza1.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rza2.c rename to drivers/pinctrl/renesas/pinctrl-rza2.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rzn1.c rename to drivers/pinctrl/renesas/pinctrl-rzn1.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl.c rename to drivers/pinctrl/renesas/pinctrl.c diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h similarity index 100% rename from drivers/pinctrl/sh-pfc/sh_pfc.h rename to drivers/pinctrl/renesas/sh_pfc.h From 540d9757cea8274a44d69cbadcff5b8c381bae8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:34 +0200 Subject: [PATCH 47/78] pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be --- drivers/pinctrl/renesas/Kconfig | 52 ++++++++++++++++++++++++++------ drivers/pinctrl/renesas/Makefile | 2 +- 2 files changed, 43 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index fc1f2611063b..e941b8440dbc 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -8,9 +8,6 @@ menu "Renesas pinctrl drivers" config PINCTRL_RENESAS bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH - select PINMUX - select PINCONF - select GENERIC_PINCONF select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 @@ -55,68 +52,95 @@ config PINCTRL_RENESAS help This enables pin control drivers for Renesas SuperH and ARM platforms -config PINCTRL_SH_PFC_GPIO - select GPIOLIB +config PINCTRL_SH_PFC bool + select GENERIC_PINCONF + select PINMUX + select PINCONF + help + This enables common pin control functionality for EMMA Mobile, R-Car, + R-Mobile, RZ/G, SH, and SH-Mobile platforms. + +config PINCTRL_SH_PFC_GPIO + bool + select GPIOLIB + select PINCTRL_SH_PFC help This enables pin control and GPIO drivers for SH/SH Mobile platforms config PINCTRL_SH_FUNC_GPIO - select PINCTRL_SH_PFC_GPIO bool + select PINCTRL_SH_PFC_GPIO help This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 bool "pin control support for Emma Mobile EV2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77995 bool "pin control support for R-Car D3" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7794 bool "pin control support for R-Car E2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77990 bool "pin control support for R-Car E3" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7779 bool "pin control support for R-Car H1" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7790 bool "pin control support for R-Car H2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77950 bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77951 bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7778 bool "pin control support for R-Car M1A" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7793 bool "pin control support for R-Car M2-N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7791 bool "pin control support for R-Car M2-W" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77965 bool "pin control support for R-Car M3-N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77960 bool "pin control support for R-Car M3-W" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77961 bool "pin control support for R-Car M3-W+" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7792 bool "pin control support for R-Car V2H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77980 bool "pin control support for R-Car V3H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77970 bool "pin control support for R-Car V3M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7740 bool "pin control support for R-Mobile A1" if COMPILE_TEST @@ -130,10 +154,10 @@ config PINCTRL_RZA1 bool "pin control support for RZ/A1" depends on OF depends on ARCH_R7S72100 || COMPILE_TEST - select GPIOLIB + select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF + select GPIOLIB help This selects pinctrl driver for Renesas RZ/A1 platforms. @@ -141,39 +165,47 @@ config PINCTRL_RZA2 bool "pin control support for RZ/A2" depends on OF depends on ARCH_R7S9210 || COMPILE_TEST - select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF + select GPIOLIB help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7745 bool "pin control support for RZ/G1E" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7742 bool "pin control support for RZ/G1H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7743 bool "pin control support for RZ/G1M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7744 bool "pin control support for RZ/G1N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774C0 bool "pin control support for RZ/G2E" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774E1 bool "pin control support for RZ/G2H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774A1 bool "pin control support for RZ/G2M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774B1 bool "pin control support for RZ/G2N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_RZN1 bool "pin control support for RZ/N1" diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index c96008c9ab59..1f6d7dd019d8 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RENESAS) += core.o pinctrl.o +obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o From 3c41f0609e63dbef49435263198cb8b5c5d9dede Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 7 Sep 2020 13:02:20 +0200 Subject: [PATCH 48/78] pinctrl: mt65xx: add OF bindings for MT8167 Add binding documentation of pinctrl-mt65xx for MT8167 SoC. Signed-off-by: Fabien Parent Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200907110221.1691168-1-fparent@baylibre.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt index 205be98ae078..931a18cd1e23 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt @@ -10,6 +10,7 @@ Required properties: "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl. "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl. "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl. + "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl. "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl. "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl. - pins-are-numbered: Specify the subnodes are using numbered pinmux to From 82d70627e94a04a8de0df5b9f417da3841effbd2 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Mon, 7 Sep 2020 13:02:21 +0200 Subject: [PATCH 49/78] pinctrl: mediatek: Add MT8167 Pinctrl driver This commit adds the pinctrl driver for the MediaTek's MT8167 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20200907110221.1691168-2-fparent@baylibre.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 7 + drivers/pinctrl/mediatek/Makefile | 1 + drivers/pinctrl/mediatek/pinctrl-mt8167.c | 362 +++++ drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h | 1248 +++++++++++++++++ 4 files changed, 1618 insertions(+) create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt8167.c create mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 7d336370d767..eef17f228669 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -119,6 +119,13 @@ config PINCTRL_MT7622 default ARM64 && ARCH_MEDIATEK select PINCTRL_MTK_MOORE +config PINCTRL_MT8167 + bool "Mediatek MT8167 pin control" + depends on OF + depends on ARM64 || COMPILE_TEST + default ARM64 && ARCH_MEDIATEK + select PINCTRL_MTK + config PINCTRL_MT8173 bool "Mediatek MT8173 pin control" depends on OF diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index 1966a5299da4..01218bf4dc30 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_MT6797) += pinctrl-mt6797.o obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o +obj-$(CONFIG_PINCTRL_MT8167) += pinctrl-mt8167.o obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o obj-$(CONFIG_PINCTRL_MT8183) += pinctrl-mt8183.o obj-$(CONFIG_PINCTRL_MT8192) += pinctrl-mt8192.o diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8167.c b/drivers/pinctrl/mediatek/pinctrl-mt8167.c new file mode 100644 index 000000000000..7b68886bad16 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mt8167.c @@ -0,0 +1,362 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 MediaTek Inc. + * Author: Min.Guo + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-mtk-common.h" +#include "pinctrl-mtk-mt8167.h" + +static const struct mtk_drv_group_desc mt8167_drv_grp[] = { + /* 0E4E8SR 4/8/12/16 */ + MTK_DRV_GRP(4, 16, 1, 2, 4), + /* 0E2E4SR 2/4/6/8 */ + MTK_DRV_GRP(2, 8, 1, 2, 2), + /* E8E4E2 2/4/6/8/10/12/14/16 */ + MTK_DRV_GRP(2, 16, 0, 2, 2) +}; + +static const struct mtk_pin_drv_grp mt8167_pin_drv[] = { + MTK_PIN_DRV_GRP(0, 0xd00, 0, 0), + MTK_PIN_DRV_GRP(1, 0xd00, 0, 0), + MTK_PIN_DRV_GRP(2, 0xd00, 0, 0), + MTK_PIN_DRV_GRP(3, 0xd00, 0, 0), + MTK_PIN_DRV_GRP(4, 0xd00, 0, 0), + + MTK_PIN_DRV_GRP(5, 0xd00, 4, 0), + MTK_PIN_DRV_GRP(6, 0xd00, 4, 0), + MTK_PIN_DRV_GRP(7, 0xd00, 4, 0), + MTK_PIN_DRV_GRP(8, 0xd00, 4, 0), + MTK_PIN_DRV_GRP(9, 0xd00, 4, 0), + MTK_PIN_DRV_GRP(10, 0xd00, 4, 0), + + MTK_PIN_DRV_GRP(11, 0xd00, 8, 0), + MTK_PIN_DRV_GRP(12, 0xd00, 8, 0), + MTK_PIN_DRV_GRP(13, 0xd00, 8, 0), + + MTK_PIN_DRV_GRP(14, 0xd00, 12, 2), + MTK_PIN_DRV_GRP(15, 0xd00, 12, 2), + MTK_PIN_DRV_GRP(16, 0xd00, 12, 2), + MTK_PIN_DRV_GRP(17, 0xd00, 12, 2), + + MTK_PIN_DRV_GRP(18, 0xd10, 0, 0), + MTK_PIN_DRV_GRP(19, 0xd10, 0, 0), + MTK_PIN_DRV_GRP(20, 0xd10, 0, 0), + + MTK_PIN_DRV_GRP(21, 0xd00, 12, 2), + MTK_PIN_DRV_GRP(22, 0xd00, 12, 2), + MTK_PIN_DRV_GRP(23, 0xd00, 12, 2), + + MTK_PIN_DRV_GRP(24, 0xd00, 8, 0), + MTK_PIN_DRV_GRP(25, 0xd00, 8, 0), + + MTK_PIN_DRV_GRP(26, 0xd10, 4, 1), + MTK_PIN_DRV_GRP(27, 0xd10, 4, 1), + MTK_PIN_DRV_GRP(28, 0xd10, 4, 1), + MTK_PIN_DRV_GRP(29, 0xd10, 4, 1), + MTK_PIN_DRV_GRP(30, 0xd10, 4, 1), + + MTK_PIN_DRV_GRP(31, 0xd10, 8, 1), + MTK_PIN_DRV_GRP(32, 0xd10, 8, 1), + MTK_PIN_DRV_GRP(33, 0xd10, 8, 1), + + MTK_PIN_DRV_GRP(34, 0xd10, 12, 0), + MTK_PIN_DRV_GRP(35, 0xd10, 12, 0), + + MTK_PIN_DRV_GRP(36, 0xd20, 0, 0), + MTK_PIN_DRV_GRP(37, 0xd20, 0, 0), + MTK_PIN_DRV_GRP(38, 0xd20, 0, 0), + MTK_PIN_DRV_GRP(39, 0xd20, 0, 0), + + MTK_PIN_DRV_GRP(40, 0xd20, 4, 1), + + MTK_PIN_DRV_GRP(41, 0xd20, 8, 1), + MTK_PIN_DRV_GRP(42, 0xd20, 8, 1), + MTK_PIN_DRV_GRP(43, 0xd20, 8, 1), + + MTK_PIN_DRV_GRP(44, 0xd20, 12, 1), + MTK_PIN_DRV_GRP(45, 0xd20, 12, 1), + MTK_PIN_DRV_GRP(46, 0xd20, 12, 1), + MTK_PIN_DRV_GRP(47, 0xd20, 12, 1), + + MTK_PIN_DRV_GRP(48, 0xd30, 0, 1), + MTK_PIN_DRV_GRP(49, 0xd30, 0, 1), + MTK_PIN_DRV_GRP(50, 0xd30, 0, 1), + MTK_PIN_DRV_GRP(51, 0xd30, 0, 1), + + MTK_PIN_DRV_GRP(54, 0xd30, 8, 1), + + MTK_PIN_DRV_GRP(55, 0xd30, 12, 1), + MTK_PIN_DRV_GRP(56, 0xd30, 12, 1), + MTK_PIN_DRV_GRP(57, 0xd30, 12, 1), + + MTK_PIN_DRV_GRP(62, 0xd40, 8, 1), + MTK_PIN_DRV_GRP(63, 0xd40, 8, 1), + MTK_PIN_DRV_GRP(64, 0xd40, 8, 1), + MTK_PIN_DRV_GRP(65, 0xd40, 8, 1), + MTK_PIN_DRV_GRP(66, 0xd40, 8, 1), + MTK_PIN_DRV_GRP(67, 0xd40, 8, 1), + + MTK_PIN_DRV_GRP(68, 0xd40, 12, 2), + + MTK_PIN_DRV_GRP(69, 0xd50, 0, 2), + + MTK_PIN_DRV_GRP(70, 0xd50, 4, 2), + MTK_PIN_DRV_GRP(71, 0xd50, 4, 2), + MTK_PIN_DRV_GRP(72, 0xd50, 4, 2), + MTK_PIN_DRV_GRP(73, 0xd50, 4, 2), + + MTK_PIN_DRV_GRP(100, 0xd50, 8, 1), + MTK_PIN_DRV_GRP(101, 0xd50, 8, 1), + MTK_PIN_DRV_GRP(102, 0xd50, 8, 1), + MTK_PIN_DRV_GRP(103, 0xd50, 8, 1), + + MTK_PIN_DRV_GRP(104, 0xd50, 12, 2), + + MTK_PIN_DRV_GRP(105, 0xd60, 0, 2), + + MTK_PIN_DRV_GRP(106, 0xd60, 4, 2), + MTK_PIN_DRV_GRP(107, 0xd60, 4, 2), + MTK_PIN_DRV_GRP(108, 0xd60, 4, 2), + MTK_PIN_DRV_GRP(109, 0xd60, 4, 2), + + MTK_PIN_DRV_GRP(110, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(111, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(112, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(113, 0xd70, 0, 2), + + MTK_PIN_DRV_GRP(114, 0xd70, 4, 2), + + MTK_PIN_DRV_GRP(115, 0xd60, 12, 2), + + MTK_PIN_DRV_GRP(116, 0xd60, 8, 2), + + MTK_PIN_DRV_GRP(117, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(118, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(119, 0xd70, 0, 2), + MTK_PIN_DRV_GRP(120, 0xd70, 0, 2), +}; + +static const struct mtk_pin_spec_pupd_set_samereg mt8167_spec_pupd[] = { + MTK_PIN_PUPD_SPEC_SR(14, 0xe50, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(15, 0xe60, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(16, 0xe60, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(17, 0xe60, 10, 9, 8), + + MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(22, 0xe70, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 6, 5, 4), + + MTK_PIN_PUPD_SPEC_SR(40, 0xe80, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(41, 0xe80, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(42, 0xe90, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(43, 0xe90, 6, 5, 4), + + MTK_PIN_PUPD_SPEC_SR(68, 0xe50, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(69, 0xe50, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(70, 0xe40, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(71, 0xe40, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(72, 0xe40, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(73, 0xe50, 2, 1, 0), + + MTK_PIN_PUPD_SPEC_SR(104, 0xe40, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(105, 0xe30, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(106, 0xe20, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(107, 0xe30, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(108, 0xe30, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(109, 0xe30, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(110, 0xe10, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(111, 0xe10, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(112, 0xe10, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(113, 0xe10, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(114, 0xe20, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(115, 0xe20, 2, 1, 0), + MTK_PIN_PUPD_SPEC_SR(116, 0xe20, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(117, 0xe00, 14, 13, 12), + MTK_PIN_PUPD_SPEC_SR(118, 0xe00, 10, 9, 8), + MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 6, 5, 4), + MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 2, 1, 0), +}; + +static int mt8167_spec_pull_set(struct regmap *regmap, unsigned int pin, + unsigned char align, bool isup, unsigned int r1r0) +{ + return mtk_pctrl_spec_pull_set_samereg(regmap, mt8167_spec_pupd, + ARRAY_SIZE(mt8167_spec_pupd), pin, align, isup, r1r0); +} + +static const struct mtk_pin_ies_smt_set mt8167_ies_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 6, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(7, 10, 0x900, 3), + MTK_PIN_IES_SMT_SPEC(11, 13, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(14, 17, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(18, 20, 0x910, 10), + MTK_PIN_IES_SMT_SPEC(21, 23, 0x900, 13), + MTK_PIN_IES_SMT_SPEC(24, 25, 0x900, 12), + MTK_PIN_IES_SMT_SPEC(26, 30, 0x900, 0), + MTK_PIN_IES_SMT_SPEC(31, 33, 0x900, 1), + MTK_PIN_IES_SMT_SPEC(34, 39, 0x900, 2), + MTK_PIN_IES_SMT_SPEC(40, 40, 0x910, 11), + MTK_PIN_IES_SMT_SPEC(41, 43, 0x900, 10), + MTK_PIN_IES_SMT_SPEC(44, 47, 0x900, 11), + MTK_PIN_IES_SMT_SPEC(48, 51, 0x900, 14), + MTK_PIN_IES_SMT_SPEC(52, 53, 0x910, 0), + MTK_PIN_IES_SMT_SPEC(54, 54, 0x910, 2), + MTK_PIN_IES_SMT_SPEC(55, 57, 0x910, 4), + MTK_PIN_IES_SMT_SPEC(58, 59, 0x900, 15), + MTK_PIN_IES_SMT_SPEC(60, 61, 0x910, 1), + MTK_PIN_IES_SMT_SPEC(62, 65, 0x910, 5), + MTK_PIN_IES_SMT_SPEC(66, 67, 0x910, 6), + MTK_PIN_IES_SMT_SPEC(68, 68, 0x930, 2), + MTK_PIN_IES_SMT_SPEC(69, 69, 0x930, 1), + MTK_PIN_IES_SMT_SPEC(70, 70, 0x930, 6), + MTK_PIN_IES_SMT_SPEC(71, 71, 0x930, 5), + MTK_PIN_IES_SMT_SPEC(72, 72, 0x930, 4), + MTK_PIN_IES_SMT_SPEC(73, 73, 0x930, 3), + MTK_PIN_IES_SMT_SPEC(100, 103, 0x910, 7), + MTK_PIN_IES_SMT_SPEC(104, 104, 0x920, 12), + MTK_PIN_IES_SMT_SPEC(105, 105, 0x920, 11), + MTK_PIN_IES_SMT_SPEC(106, 106, 0x930, 0), + MTK_PIN_IES_SMT_SPEC(107, 107, 0x920, 15), + MTK_PIN_IES_SMT_SPEC(108, 108, 0x920, 14), + MTK_PIN_IES_SMT_SPEC(109, 109, 0x920, 13), + MTK_PIN_IES_SMT_SPEC(110, 110, 0x920, 9), + MTK_PIN_IES_SMT_SPEC(111, 111, 0x920, 8), + MTK_PIN_IES_SMT_SPEC(112, 112, 0x920, 7), + MTK_PIN_IES_SMT_SPEC(113, 113, 0x920, 6), + MTK_PIN_IES_SMT_SPEC(114, 114, 0x920, 10), + MTK_PIN_IES_SMT_SPEC(115, 115, 0x920, 1), + MTK_PIN_IES_SMT_SPEC(116, 116, 0x920, 0), + MTK_PIN_IES_SMT_SPEC(117, 117, 0x920, 5), + MTK_PIN_IES_SMT_SPEC(118, 118, 0x920, 4), + MTK_PIN_IES_SMT_SPEC(119, 119, 0x920, 3), + MTK_PIN_IES_SMT_SPEC(120, 120, 0x920, 2), + MTK_PIN_IES_SMT_SPEC(121, 124, 0x910, 9), +}; + +static const struct mtk_pin_ies_smt_set mt8167_smt_set[] = { + MTK_PIN_IES_SMT_SPEC(0, 6, 0xA00, 2), + MTK_PIN_IES_SMT_SPEC(7, 10, 0xA00, 3), + MTK_PIN_IES_SMT_SPEC(11, 13, 0xA00, 12), + MTK_PIN_IES_SMT_SPEC(14, 17, 0xA00, 13), + MTK_PIN_IES_SMT_SPEC(18, 20, 0xA10, 10), + MTK_PIN_IES_SMT_SPEC(21, 23, 0xA00, 13), + MTK_PIN_IES_SMT_SPEC(24, 25, 0xA00, 12), + MTK_PIN_IES_SMT_SPEC(26, 30, 0xA00, 0), + MTK_PIN_IES_SMT_SPEC(31, 33, 0xA00, 1), + MTK_PIN_IES_SMT_SPEC(34, 39, 0xA900, 2), + MTK_PIN_IES_SMT_SPEC(40, 40, 0xA10, 11), + MTK_PIN_IES_SMT_SPEC(41, 43, 0xA00, 10), + MTK_PIN_IES_SMT_SPEC(44, 47, 0xA00, 11), + MTK_PIN_IES_SMT_SPEC(48, 51, 0xA00, 14), + MTK_PIN_IES_SMT_SPEC(52, 53, 0xA10, 0), + MTK_PIN_IES_SMT_SPEC(54, 54, 0xA10, 2), + MTK_PIN_IES_SMT_SPEC(55, 57, 0xA10, 4), + MTK_PIN_IES_SMT_SPEC(58, 59, 0xA00, 15), + MTK_PIN_IES_SMT_SPEC(60, 61, 0xA10, 1), + MTK_PIN_IES_SMT_SPEC(62, 65, 0xA10, 5), + MTK_PIN_IES_SMT_SPEC(66, 67, 0xA10, 6), + MTK_PIN_IES_SMT_SPEC(68, 68, 0xA30, 2), + MTK_PIN_IES_SMT_SPEC(69, 69, 0xA30, 1), + MTK_PIN_IES_SMT_SPEC(70, 70, 0xA30, 3), + MTK_PIN_IES_SMT_SPEC(71, 71, 0xA30, 4), + MTK_PIN_IES_SMT_SPEC(72, 72, 0xA30, 5), + MTK_PIN_IES_SMT_SPEC(73, 73, 0xA30, 6), + + MTK_PIN_IES_SMT_SPEC(100, 103, 0xA10, 7), + MTK_PIN_IES_SMT_SPEC(104, 104, 0xA20, 12), + MTK_PIN_IES_SMT_SPEC(105, 105, 0xA20, 11), + MTK_PIN_IES_SMT_SPEC(106, 106, 0xA30, 13), + MTK_PIN_IES_SMT_SPEC(107, 107, 0xA20, 14), + MTK_PIN_IES_SMT_SPEC(108, 108, 0xA20, 15), + MTK_PIN_IES_SMT_SPEC(109, 109, 0xA30, 0), + MTK_PIN_IES_SMT_SPEC(110, 110, 0xA20, 9), + MTK_PIN_IES_SMT_SPEC(111, 111, 0xA20, 8), + MTK_PIN_IES_SMT_SPEC(112, 112, 0xA20, 7), + MTK_PIN_IES_SMT_SPEC(113, 113, 0xA20, 6), + MTK_PIN_IES_SMT_SPEC(114, 114, 0xA20, 10), + MTK_PIN_IES_SMT_SPEC(115, 115, 0xA20, 1), + MTK_PIN_IES_SMT_SPEC(116, 116, 0xA20, 0), + MTK_PIN_IES_SMT_SPEC(117, 117, 0xA20, 5), + MTK_PIN_IES_SMT_SPEC(118, 118, 0xA20, 4), + MTK_PIN_IES_SMT_SPEC(119, 119, 0xA20, 3), + MTK_PIN_IES_SMT_SPEC(120, 120, 0xA20, 2), + MTK_PIN_IES_SMT_SPEC(121, 124, 0xA10, 9), +}; + +static int mt8167_ies_smt_set(struct regmap *regmap, unsigned int pin, + unsigned char align, int value, enum pin_config_param arg) +{ + if (arg == PIN_CONFIG_INPUT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_ies_set, + ARRAY_SIZE(mt8167_ies_set), pin, align, value); + else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE) + return mtk_pconf_spec_set_ies_smt_range(regmap, mt8167_smt_set, + ARRAY_SIZE(mt8167_smt_set), pin, align, value); + return -EINVAL; +} + +static const struct mtk_pinctrl_devdata mt8167_pinctrl_data = { + .pins = mtk_pins_mt8167, + .npins = ARRAY_SIZE(mtk_pins_mt8167), + .grp_desc = mt8167_drv_grp, + .n_grp_cls = ARRAY_SIZE(mt8167_drv_grp), + .pin_drv_grp = mt8167_pin_drv, + .n_pin_drv_grps = ARRAY_SIZE(mt8167_pin_drv), + .spec_pull_set = mt8167_spec_pull_set, + .spec_ies_smt_set = mt8167_ies_smt_set, + .dir_offset = 0x0000, + .pullen_offset = 0x0500, + .pullsel_offset = 0x0600, + .dout_offset = 0x0100, + .din_offset = 0x0200, + .pinmux_offset = 0x0300, + .type1_start = 125, + .type1_end = 125, + .port_shf = 4, + .port_mask = 0xf, + .port_align = 4, + .eint_hw = { + .port_mask = 7, + .ports = 6, + .ap_num = 169, + .db_cnt = 64, + }, +}; + +static int mt8167_pinctrl_probe(struct platform_device *pdev) +{ + return mtk_pctrl_init(pdev, &mt8167_pinctrl_data, NULL); +} + +static const struct of_device_id mt8167_pctrl_match[] = { + { + .compatible = "mediatek,mt8167-pinctrl", + }, + {} +}; + +MODULE_DEVICE_TABLE(of, mt8167_pctrl_match); + +static struct platform_driver mtk_pinctrl_driver = { + .probe = mt8167_pinctrl_probe, + .driver = { + .name = "mediatek-mt8167-pinctrl", + .of_match_table = mt8167_pctrl_match, + .pm = &mtk_eint_pm_ops, + }, +}; + +static int __init mtk_pinctrl_init(void) +{ + return platform_driver_register(&mtk_pinctrl_driver); +} +arch_initcall(mtk_pinctrl_init); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h new file mode 100644 index 000000000000..225c41fc9b75 --- /dev/null +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8167.h @@ -0,0 +1,1248 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020 MediaTek Inc. + */ +#ifndef __PINCTRL_MTK_MT8167_H +#define __PINCTRL_MTK_MT8167_H + +#include +#include "pinctrl-mtk-common.h" + +static const struct mtk_desc_pin mtk_pins_mt8167[] = { + MTK_PIN( + PINCTRL_PIN(0, "EINT0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 0), + MTK_FUNCTION(0, "GPIO0"), + MTK_FUNCTION(1, "PWM_B"), + MTK_FUNCTION(2, "DPI_CK"), + MTK_FUNCTION(3, "I2S2_BCK"), + MTK_FUNCTION(4, "EXT_TXD0"), + MTK_FUNCTION(6, "SQICS"), + MTK_FUNCTION(7, "DBG_MON_A[6]") + ), + MTK_PIN( + PINCTRL_PIN(1, "EINT1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 1), + MTK_FUNCTION(0, "GPIO1"), + MTK_FUNCTION(1, "PWM_C"), + MTK_FUNCTION(2, "DPI_D12"), + MTK_FUNCTION(3, "I2S2_DI"), + MTK_FUNCTION(4, "EXT_TXD1"), + MTK_FUNCTION(5, "CONN_MCU_TDO"), + MTK_FUNCTION(6, "SQISO"), + MTK_FUNCTION(7, "DBG_MON_A[7]") + ), + MTK_PIN( + PINCTRL_PIN(2, "EINT2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 2), + MTK_FUNCTION(0, "GPIO2"), + MTK_FUNCTION(1, "CLKM0"), + MTK_FUNCTION(2, "DPI_D13"), + MTK_FUNCTION(3, "I2S2_LRCK"), + MTK_FUNCTION(4, "EXT_TXD2"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "SQISI"), + MTK_FUNCTION(7, "DBG_MON_A[8]") + ), + MTK_PIN( + PINCTRL_PIN(3, "EINT3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 3), + MTK_FUNCTION(0, "GPIO3"), + MTK_FUNCTION(1, "CLKM1"), + MTK_FUNCTION(2, "DPI_D14"), + MTK_FUNCTION(3, "SPI_MI"), + MTK_FUNCTION(4, "EXT_TXD3"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "SQIWP"), + MTK_FUNCTION(7, "DBG_MON_A[9]") + ), + MTK_PIN( + PINCTRL_PIN(4, "EINT4"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 4), + MTK_FUNCTION(0, "GPIO4"), + MTK_FUNCTION(1, "CLKM2"), + MTK_FUNCTION(2, "DPI_D15"), + MTK_FUNCTION(3, "SPI_MO"), + MTK_FUNCTION(4, "EXT_TXC"), + MTK_FUNCTION(5, "CONN_MCU_TCK"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(7, "DBG_MON_A[10]") + ), + MTK_PIN( + PINCTRL_PIN(5, "EINT5"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 5), + MTK_FUNCTION(0, "GPIO5"), + MTK_FUNCTION(1, "UCTS2"), + MTK_FUNCTION(2, "DPI_D16"), + MTK_FUNCTION(3, "SPI_CSB"), + MTK_FUNCTION(4, "EXT_RXER"), + MTK_FUNCTION(5, "CONN_MCU_TDI"), + MTK_FUNCTION(6, "CONN_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A[11]") + ), + MTK_PIN( + PINCTRL_PIN(6, "EINT6"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 6), + MTK_FUNCTION(0, "GPIO6"), + MTK_FUNCTION(1, "URTS2"), + MTK_FUNCTION(2, "DPI_D17"), + MTK_FUNCTION(3, "SPI_CLK"), + MTK_FUNCTION(4, "EXT_RXC"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "MM_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_A[12]") + ), + MTK_PIN( + PINCTRL_PIN(7, "EINT7"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 7), + MTK_FUNCTION(0, "GPIO7"), + MTK_FUNCTION(1, "SQIRST"), + MTK_FUNCTION(2, "DPI_D6"), + MTK_FUNCTION(3, "SDA1_0"), + MTK_FUNCTION(4, "EXT_RXDV"), + MTK_FUNCTION(5, "CONN_MCU_TMS"), + MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(7, "DBG_MON_A[13]") + ), + MTK_PIN( + PINCTRL_PIN(8, "EINT8"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 8), + MTK_FUNCTION(0, "GPIO8"), + MTK_FUNCTION(1, "SQICK"), + MTK_FUNCTION(2, "CLKM3"), + MTK_FUNCTION(3, "SCL1_0"), + MTK_FUNCTION(4, "EXT_RXD0"), + MTK_FUNCTION(5, "ANT_SEL0"), + MTK_FUNCTION(6, "DPI_D7"), + MTK_FUNCTION(7, "DBG_MON_A[14]") + ), + MTK_PIN( + PINCTRL_PIN(9, "EINT9"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 9), + MTK_FUNCTION(0, "GPIO9"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "SDA2_0"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD1"), + MTK_FUNCTION(5, "ANT_SEL1"), + MTK_FUNCTION(6, "DPI_D8"), + MTK_FUNCTION(7, "DBG_MON_A[15]") + ), + MTK_PIN( + PINCTRL_PIN(10, "EINT10"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 10), + MTK_FUNCTION(0, "GPIO10"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "SCL2_0"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "EXT_RXD2"), + MTK_FUNCTION(5, "ANT_SEL2"), + MTK_FUNCTION(6, "DPI_D9"), + MTK_FUNCTION(7, "DBG_MON_A[16]") + ), + MTK_PIN( + PINCTRL_PIN(11, "EINT11"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 11), + MTK_FUNCTION(0, "GPIO11"), + MTK_FUNCTION(1, "CLKM4"), + MTK_FUNCTION(2, "PWM_C"), + MTK_FUNCTION(3, "CONN_TEST_CK"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "DPI_D10"), + MTK_FUNCTION(6, "EXT_RXD3"), + MTK_FUNCTION(7, "DBG_MON_A[17]") + ), + MTK_PIN( + PINCTRL_PIN(12, "EINT12"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 12), + MTK_FUNCTION(0, "GPIO12"), + MTK_FUNCTION(1, "CLKM5"), + MTK_FUNCTION(2, "PWM_A"), + MTK_FUNCTION(3, "SPDIF_OUT"), + MTK_FUNCTION(4, "ANT_SEL4"), + MTK_FUNCTION(5, "DPI_D11"), + MTK_FUNCTION(6, "EXT_TXEN"), + MTK_FUNCTION(7, "DBG_MON_A[18]") + ), + MTK_PIN( + PINCTRL_PIN(13, "EINT13"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 13), + MTK_FUNCTION(0, "GPIO13"), + MTK_FUNCTION(3, "TSF_IN"), + MTK_FUNCTION(4, "ANT_SEL5"), + MTK_FUNCTION(5, "DPI_D0"), + MTK_FUNCTION(6, "SPDIF_IN"), + MTK_FUNCTION(7, "DBG_MON_A[19]") + ), + MTK_PIN( + PINCTRL_PIN(14, "EINT14"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 14), + MTK_FUNCTION(0, "GPIO14"), + MTK_FUNCTION(2, "I2S_8CH_DO1"), + MTK_FUNCTION(3, "TDM_RX_MCK"), + MTK_FUNCTION(4, "ANT_SEL1"), + MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"), + MTK_FUNCTION(6, "NCLE"), + MTK_FUNCTION(7, "DBG_MON_B[8]") + ), + MTK_PIN( + PINCTRL_PIN(15, "EINT15"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 15), + MTK_FUNCTION(0, "GPIO15"), + MTK_FUNCTION(2, "I2S_8CH_LRCK"), + MTK_FUNCTION(3, "TDM_RX_BCK"), + MTK_FUNCTION(4, "ANT_SEL2"), + MTK_FUNCTION(5, "CONN_MCU_DBGI_N"), + MTK_FUNCTION(6, "NCEB1"), + MTK_FUNCTION(7, "DBG_MON_B[9]") + ), + MTK_PIN( + PINCTRL_PIN(16, "EINT16"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 16), + MTK_FUNCTION(0, "GPIO16"), + MTK_FUNCTION(2, "I2S_8CH_BCK"), + MTK_FUNCTION(3, "TDM_RX_LRCK"), + MTK_FUNCTION(4, "ANT_SEL3"), + MTK_FUNCTION(5, "CONN_MCU_TRST_B"), + MTK_FUNCTION(6, "NCEB0"), + MTK_FUNCTION(7, "DBG_MON_B[10]") + ), + MTK_PIN( + PINCTRL_PIN(17, "EINT17"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 17), + MTK_FUNCTION(0, "GPIO17"), + MTK_FUNCTION(2, "I2S_8CH_MCK"), + MTK_FUNCTION(3, "TDM_RX_DI"), + MTK_FUNCTION(4, "IDDIG"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "NREB"), + MTK_FUNCTION(7, "DBG_MON_B[11]") + ), + MTK_PIN( + PINCTRL_PIN(18, "EINT18"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 18), + MTK_FUNCTION(0, "GPIO18"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "CLKM1"), + MTK_FUNCTION(5, "ANT_SEL3"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A[20]") + ), + MTK_PIN( + PINCTRL_PIN(19, "EINT19"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 19), + MTK_FUNCTION(0, "GPIO19"), + MTK_FUNCTION(1, "UCTS1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "CLKM2"), + MTK_FUNCTION(5, "ANT_SEL4"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A[21]") + ), + MTK_PIN( + PINCTRL_PIN(20, "EINT20"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 20), + MTK_FUNCTION(0, "GPIO20"), + MTK_FUNCTION(1, "URTS1"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "CLKM3"), + MTK_FUNCTION(5, "ANT_SEL5"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A[22]") + ), + MTK_PIN( + PINCTRL_PIN(21, "EINT21"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 21), + MTK_FUNCTION(0, "GPIO21"), + MTK_FUNCTION(1, "NRNB"), + MTK_FUNCTION(2, "ANT_SEL0"), + MTK_FUNCTION(3, "I2S_8CH_DO4"), + MTK_FUNCTION(7, "DBG_MON_B[31]") + ), + MTK_PIN( + PINCTRL_PIN(22, "EINT22"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 22), + MTK_FUNCTION(0, "GPIO22"), + MTK_FUNCTION(2, "I2S_8CH_DO2"), + MTK_FUNCTION(3, "TSF_IN"), + MTK_FUNCTION(4, "USB_DRVVBUS"), + MTK_FUNCTION(5, "SPDIF_OUT"), + MTK_FUNCTION(6, "NRE_C"), + MTK_FUNCTION(7, "DBG_MON_B[12]") + ), + MTK_PIN( + PINCTRL_PIN(23, "EINT23"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 23), + MTK_FUNCTION(0, "GPIO23"), + MTK_FUNCTION(2, "I2S_8CH_DO3"), + MTK_FUNCTION(3, "CLKM0"), + MTK_FUNCTION(4, "IR"), + MTK_FUNCTION(5, "SPDIF_IN"), + MTK_FUNCTION(6, "NDQS_C"), + MTK_FUNCTION(7, "DBG_MON_B[13]") + ), + MTK_PIN( + PINCTRL_PIN(24, "EINT24"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 24), + MTK_FUNCTION(0, "GPIO24"), + MTK_FUNCTION(1, "DPI_D20"), + MTK_FUNCTION(2, "DPI_DE"), + MTK_FUNCTION(3, "ANT_SEL1"), + MTK_FUNCTION(4, "UCTS2"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "I2S0_MCK"), + MTK_FUNCTION(7, "DBG_MON_A[0]") + ), + MTK_PIN( + PINCTRL_PIN(25, "EINT25"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 25), + MTK_FUNCTION(0, "GPIO25"), + MTK_FUNCTION(1, "DPI_D19"), + MTK_FUNCTION(2, "DPI_VSYNC"), + MTK_FUNCTION(3, "ANT_SEL0"), + MTK_FUNCTION(4, "URTS2"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(6, "I2S_8CH_MCK"), + MTK_FUNCTION(7, "DBG_MON_A[1]") + ), + MTK_PIN( + PINCTRL_PIN(26, "PWRAP_SPI0_MI"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 26), + MTK_FUNCTION(0, "GPIO26"), + MTK_FUNCTION(1, "PWRAP_SPI0_MO"), + MTK_FUNCTION(2, "PWRAP_SPI0_MI") + ), + MTK_PIN( + PINCTRL_PIN(27, "PWRAP_SPI0_MO"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 27), + MTK_FUNCTION(0, "GPIO27"), + MTK_FUNCTION(1, "PWRAP_SPI0_MI"), + MTK_FUNCTION(2, "PWRAP_SPI0_MO") + ), + MTK_PIN( + PINCTRL_PIN(28, "PWRAP_INT"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 28), + MTK_FUNCTION(0, "GPIO28"), + MTK_FUNCTION(1, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S_8CH_MCK"), + MTK_FUNCTION(5, "I2S2_MCK"), + MTK_FUNCTION(6, "I2S3_MCK") + ), + MTK_PIN( + PINCTRL_PIN(29, "PWRAP_SPI0_CK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 29), + MTK_FUNCTION(0, "GPIO29"), + MTK_FUNCTION(1, "PWRAP_SPI0_CK") + ), + MTK_PIN( + PINCTRL_PIN(30, "PWRAP_SPI0_CSN"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 30), + MTK_FUNCTION(0, "GPIO30"), + MTK_FUNCTION(1, "PWRAP_SPI0_CSN") + ), + MTK_PIN( + PINCTRL_PIN(31, "RTC32K_CK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 31), + MTK_FUNCTION(0, "GPIO31"), + MTK_FUNCTION(1, "RTC32K_CK") + ), + MTK_PIN( + PINCTRL_PIN(32, "WATCHDOG"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 32), + MTK_FUNCTION(0, "GPIO32"), + MTK_FUNCTION(1, "WATCHDOG") + ), + MTK_PIN( + PINCTRL_PIN(33, "SRCLKENA"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 33), + MTK_FUNCTION(0, "GPIO33"), + MTK_FUNCTION(1, "SRCLKENA0") + ), + MTK_PIN( + PINCTRL_PIN(34, "URXD2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 34), + MTK_FUNCTION(0, "GPIO34"), + MTK_FUNCTION(1, "URXD2"), + MTK_FUNCTION(2, "DPI_D5"), + MTK_FUNCTION(3, "UTXD2"), + MTK_FUNCTION(4, "DBG_SCL"), + MTK_FUNCTION(6, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[0]") + ), + MTK_PIN( + PINCTRL_PIN(35, "UTXD2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 35), + MTK_FUNCTION(0, "GPIO35"), + MTK_FUNCTION(1, "UTXD2"), + MTK_FUNCTION(2, "DPI_HSYNC"), + MTK_FUNCTION(3, "URXD2"), + MTK_FUNCTION(4, "DBG_SDA"), + MTK_FUNCTION(5, "DPI_D18"), + MTK_FUNCTION(6, "I2S3_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[1]") + ), + MTK_PIN( + PINCTRL_PIN(36, "MRG_CLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 36), + MTK_FUNCTION(0, "GPIO36"), + MTK_FUNCTION(1, "MRG_CLK"), + MTK_FUNCTION(2, "DPI_D4"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "I2S3_BCK"), + MTK_FUNCTION(5, "PCM0_CLK"), + MTK_FUNCTION(6, "IR"), + MTK_FUNCTION(7, "DBG_MON_A[2]") + ), + MTK_PIN( + PINCTRL_PIN(37, "MRG_SYNC"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 37), + MTK_FUNCTION(0, "GPIO37"), + MTK_FUNCTION(1, "MRG_SYNC"), + MTK_FUNCTION(2, "DPI_D3"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S3_LRCK"), + MTK_FUNCTION(5, "PCM0_SYNC"), + MTK_FUNCTION(6, "EXT_COL"), + MTK_FUNCTION(7, "DBG_MON_A[3]") + ), + MTK_PIN( + PINCTRL_PIN(38, "MRG_DI"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 38), + MTK_FUNCTION(0, "GPIO38"), + MTK_FUNCTION(1, "MRG_DI"), + MTK_FUNCTION(2, "DPI_D1"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "I2S3_DO"), + MTK_FUNCTION(5, "PCM0_DI"), + MTK_FUNCTION(6, "EXT_MDIO"), + MTK_FUNCTION(7, "DBG_MON_A[4]") + ), + MTK_PIN( + PINCTRL_PIN(39, "MRG_DO"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 39), + MTK_FUNCTION(0, "GPIO39"), + MTK_FUNCTION(1, "MRG_DO"), + MTK_FUNCTION(2, "DPI_D2"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "PCM0_DO"), + MTK_FUNCTION(6, "EXT_MDC"), + MTK_FUNCTION(7, "DBG_MON_A[5]") + ), + MTK_PIN( + PINCTRL_PIN(40, "KPROW0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 40), + MTK_FUNCTION(0, "GPIO40"), + MTK_FUNCTION(1, "KPROW0"), + MTK_FUNCTION(4, "IMG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[4]") + ), + MTK_PIN( + PINCTRL_PIN(41, "KPROW1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 41), + MTK_FUNCTION(0, "GPIO41"), + MTK_FUNCTION(1, "KPROW1"), + MTK_FUNCTION(2, "IDDIG"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "MFG_TEST_CK"), + MTK_FUNCTION(7, "DBG_MON_B[5]") + ), + MTK_PIN( + PINCTRL_PIN(42, "KPCOL0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 42), + MTK_FUNCTION(0, "GPIO42"), + MTK_FUNCTION(1, "KPCOL0"), + MTK_FUNCTION(7, "DBG_MON_B[6]") + ), + MTK_PIN( + PINCTRL_PIN(43, "KPCOL1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 43), + MTK_FUNCTION(0, "GPIO43"), + MTK_FUNCTION(1, "KPCOL1"), + MTK_FUNCTION(2, "USB_DRVVBUS"), + MTK_FUNCTION(3, "EXT_FRAME_SYNC"), + MTK_FUNCTION(4, "TSF_IN"), + MTK_FUNCTION(5, "DFD_NTRST_XI"), + MTK_FUNCTION(6, "UDI_NTRST_XI"), + MTK_FUNCTION(7, "DBG_MON_B[7]") + ), + MTK_PIN( + PINCTRL_PIN(44, "JTMS"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 44), + MTK_FUNCTION(0, "GPIO44"), + MTK_FUNCTION(1, "JTMS"), + MTK_FUNCTION(2, "CONN_MCU_TMS"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC"), + MTK_FUNCTION(4, "GPUDFD_TMS_XI"), + MTK_FUNCTION(5, "DFD_TMS_XI"), + MTK_FUNCTION(6, "UDI_TMS_XI") + ), + MTK_PIN( + PINCTRL_PIN(45, "JTCK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 45), + MTK_FUNCTION(0, "GPIO45"), + MTK_FUNCTION(1, "JTCK"), + MTK_FUNCTION(2, "CONN_MCU_TCK"), + MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC"), + MTK_FUNCTION(4, "GPUDFD_TCK_XI"), + MTK_FUNCTION(5, "DFD_TCK_XI"), + MTK_FUNCTION(6, "UDI_TCK_XI") + ), + MTK_PIN( + PINCTRL_PIN(46, "JTDI"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 46), + MTK_FUNCTION(0, "GPIO46"), + MTK_FUNCTION(1, "JTDI"), + MTK_FUNCTION(2, "CONN_MCU_TDI"), + MTK_FUNCTION(4, "GPUDFD_TDI_XI"), + MTK_FUNCTION(5, "DFD_TDI_XI"), + MTK_FUNCTION(6, "UDI_TDI_XI") + ), + MTK_PIN( + PINCTRL_PIN(47, "JTDO"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 47), + MTK_FUNCTION(0, "GPIO47"), + MTK_FUNCTION(1, "JTDO"), + MTK_FUNCTION(2, "CONN_MCU_TDO"), + MTK_FUNCTION(4, "GPUDFD_TDO"), + MTK_FUNCTION(5, "DFD_TDO"), + MTK_FUNCTION(6, "UDI_TDO") + ), + MTK_PIN( + PINCTRL_PIN(48, "SPI_CS"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 48), + MTK_FUNCTION(0, "GPIO48"), + MTK_FUNCTION(1, "SPI_CSB"), + MTK_FUNCTION(3, "I2S0_DI"), + MTK_FUNCTION(4, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A[23]") + ), + MTK_PIN( + PINCTRL_PIN(49, "SPI_CK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 49), + MTK_FUNCTION(0, "GPIO49"), + MTK_FUNCTION(1, "SPI_CLK"), + MTK_FUNCTION(3, "I2S0_LRCK"), + MTK_FUNCTION(4, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A[24]") + ), + MTK_PIN( + PINCTRL_PIN(50, "SPI_MI"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 50), + MTK_FUNCTION(0, "GPIO50"), + MTK_FUNCTION(1, "SPI_MI"), + MTK_FUNCTION(2, "SPI_MO"), + MTK_FUNCTION(3, "I2S0_BCK"), + MTK_FUNCTION(4, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A[25]") + ), + MTK_PIN( + PINCTRL_PIN(51, "SPI_MO"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 51), + MTK_FUNCTION(0, "GPIO51"), + MTK_FUNCTION(1, "SPI_MO"), + MTK_FUNCTION(2, "SPI_MI"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(4, "I2S2_MCK"), + MTK_FUNCTION(7, "DBG_MON_A[26]") + ), + MTK_PIN( + PINCTRL_PIN(52, "SDA1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 52), + MTK_FUNCTION(0, "GPIO52"), + MTK_FUNCTION(1, "SDA1_0") + ), + MTK_PIN( + PINCTRL_PIN(53, "SCL1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 53), + MTK_FUNCTION(0, "GPIO53"), + MTK_FUNCTION(1, "SCL1_0") + ), + MTK_PIN( + PINCTRL_PIN(54, "DISP_PWM"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 54), + MTK_FUNCTION(0, "GPIO54"), + MTK_FUNCTION(1, "DISP_PWM"), + MTK_FUNCTION(2, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_B[2]") + ), + MTK_PIN( + PINCTRL_PIN(55, "I2S_DATA_IN"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 55), + MTK_FUNCTION(0, "GPIO55"), + MTK_FUNCTION(1, "I2S0_DI"), + MTK_FUNCTION(2, "UCTS0"), + MTK_FUNCTION(3, "I2S3_DO"), + MTK_FUNCTION(4, "I2S_8CH_DO1"), + MTK_FUNCTION(5, "PWM_A"), + MTK_FUNCTION(6, "I2S2_BCK"), + MTK_FUNCTION(7, "DBG_MON_A[28]") + ), + MTK_PIN( + PINCTRL_PIN(56, "I2S_LRCK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 56), + MTK_FUNCTION(0, "GPIO56"), + MTK_FUNCTION(1, "I2S0_LRCK"), + MTK_FUNCTION(3, "I2S3_LRCK"), + MTK_FUNCTION(4, "I2S_8CH_LRCK"), + MTK_FUNCTION(5, "PWM_B"), + MTK_FUNCTION(6, "I2S2_DI"), + MTK_FUNCTION(7, "DBG_MON_A[29]") + ), + MTK_PIN( + PINCTRL_PIN(57, "I2S_BCK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 57), + MTK_FUNCTION(0, "GPIO57"), + MTK_FUNCTION(1, "I2S0_BCK"), + MTK_FUNCTION(2, "URTS0"), + MTK_FUNCTION(3, "I2S3_BCK"), + MTK_FUNCTION(4, "I2S_8CH_BCK"), + MTK_FUNCTION(5, "PWM_C"), + MTK_FUNCTION(6, "I2S2_LRCK"), + MTK_FUNCTION(7, "DBG_MON_A[30]") + ), + MTK_PIN( + PINCTRL_PIN(58, "SDA0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 58), + MTK_FUNCTION(0, "GPIO58"), + MTK_FUNCTION(1, "SDA0_0") + ), + MTK_PIN( + PINCTRL_PIN(59, "SCL0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 59), + MTK_FUNCTION(0, "GPIO59"), + MTK_FUNCTION(1, "SCL0_0") + ), + MTK_PIN( + PINCTRL_PIN(60, "SDA2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 60), + MTK_FUNCTION(0, "GPIO60"), + MTK_FUNCTION(1, "SDA2_0"), + MTK_FUNCTION(2, "PWM_B") + ), + MTK_PIN( + PINCTRL_PIN(61, "SCL2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 61), + MTK_FUNCTION(0, "GPIO61"), + MTK_FUNCTION(1, "SCL2_0"), + MTK_FUNCTION(2, "PWM_C") + ), + MTK_PIN( + PINCTRL_PIN(62, "URXD0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 62), + MTK_FUNCTION(0, "GPIO62"), + MTK_FUNCTION(1, "URXD0"), + MTK_FUNCTION(2, "UTXD0") + ), + MTK_PIN( + PINCTRL_PIN(63, "UTXD0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 63), + MTK_FUNCTION(0, "GPIO63"), + MTK_FUNCTION(1, "UTXD0"), + MTK_FUNCTION(2, "URXD0") + ), + MTK_PIN( + PINCTRL_PIN(64, "URXD1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 64), + MTK_FUNCTION(0, "GPIO64"), + MTK_FUNCTION(1, "URXD1"), + MTK_FUNCTION(2, "UTXD1"), + MTK_FUNCTION(7, "DBG_MON_A[27]") + ), + MTK_PIN( + PINCTRL_PIN(65, "UTXD1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 65), + MTK_FUNCTION(0, "GPIO65"), + MTK_FUNCTION(1, "UTXD1"), + MTK_FUNCTION(2, "URXD1"), + MTK_FUNCTION(7, "DBG_MON_A[31]") + ), + MTK_PIN( + PINCTRL_PIN(66, "LCM_RST"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 66), + MTK_FUNCTION(0, "GPIO66"), + MTK_FUNCTION(1, "LCM_RST"), + MTK_FUNCTION(3, "I2S0_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[3]") + ), + MTK_PIN( + PINCTRL_PIN(67, "DSI_TE"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 67), + MTK_FUNCTION(0, "GPIO67"), + MTK_FUNCTION(1, "DSI_TE"), + MTK_FUNCTION(3, "I2S_8CH_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[14]") + ), + MTK_PIN( + PINCTRL_PIN(68, "MSDC2_CMD"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 68), + MTK_FUNCTION(0, "GPIO68"), + MTK_FUNCTION(1, "MSDC2_CMD"), + MTK_FUNCTION(2, "I2S_8CH_DO4"), + MTK_FUNCTION(3, "SDA1_0"), + MTK_FUNCTION(5, "USB_SDA"), + MTK_FUNCTION(6, "I2S3_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[15]") + ), + MTK_PIN( + PINCTRL_PIN(69, "MSDC2_CLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 69), + MTK_FUNCTION(0, "GPIO69"), + MTK_FUNCTION(1, "MSDC2_CLK"), + MTK_FUNCTION(2, "I2S_8CH_DO3"), + MTK_FUNCTION(3, "SCL1_0"), + MTK_FUNCTION(4, "DPI_D21"), + MTK_FUNCTION(5, "USB_SCL"), + MTK_FUNCTION(6, "I2S3_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[16]") + ), + MTK_PIN( + PINCTRL_PIN(70, "MSDC2_DAT0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 70), + MTK_FUNCTION(0, "GPIO70"), + MTK_FUNCTION(1, "MSDC2_DAT0"), + MTK_FUNCTION(2, "I2S_8CH_DO2"), + MTK_FUNCTION(4, "DPI_D22"), + MTK_FUNCTION(5, "UTXD0"), + MTK_FUNCTION(6, "I2S3_DO"), + MTK_FUNCTION(7, "DBG_MON_B[17]") + ), + MTK_PIN( + PINCTRL_PIN(71, "MSDC2_DAT1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 71), + MTK_FUNCTION(0, "GPIO71"), + MTK_FUNCTION(1, "MSDC2_DAT1"), + MTK_FUNCTION(2, "I2S_8CH_DO1"), + MTK_FUNCTION(3, "PWM_A"), + MTK_FUNCTION(4, "I2S3_MCK"), + MTK_FUNCTION(5, "URXD0"), + MTK_FUNCTION(6, "PWM_B"), + MTK_FUNCTION(7, "DBG_MON_B[18]") + ), + MTK_PIN( + PINCTRL_PIN(72, "MSDC2_DAT2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 72), + MTK_FUNCTION(0, "GPIO72"), + MTK_FUNCTION(1, "MSDC2_DAT2"), + MTK_FUNCTION(2, "I2S_8CH_LRCK"), + MTK_FUNCTION(3, "SDA2_0"), + MTK_FUNCTION(4, "DPI_D23"), + MTK_FUNCTION(5, "UTXD1"), + MTK_FUNCTION(6, "PWM_C"), + MTK_FUNCTION(7, "DBG_MON_B[19]") + ), + MTK_PIN( + PINCTRL_PIN(73, "MSDC2_DAT3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 73), + MTK_FUNCTION(0, "GPIO73"), + MTK_FUNCTION(1, "MSDC2_DAT3"), + MTK_FUNCTION(2, "I2S_8CH_BCK"), + MTK_FUNCTION(3, "SCL2_0"), + MTK_FUNCTION(4, "EXT_FRAME_SYNC"), + MTK_FUNCTION(5, "URXD1"), + MTK_FUNCTION(6, "PWM_A"), + MTK_FUNCTION(7, "DBG_MON_B[20]") + ), + MTK_PIN( + PINCTRL_PIN(74, "TDN3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 74), + MTK_FUNCTION(0, "GPI74"), + MTK_FUNCTION(1, "TDN3") + ), + MTK_PIN( + PINCTRL_PIN(75, "TDP3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 75), + MTK_FUNCTION(0, "GPI75"), + MTK_FUNCTION(1, "TDP3") + ), + MTK_PIN( + PINCTRL_PIN(76, "TDN2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 76), + MTK_FUNCTION(0, "GPI76"), + MTK_FUNCTION(1, "TDN2") + ), + MTK_PIN( + PINCTRL_PIN(77, "TDP2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 77), + MTK_FUNCTION(0, "GPI77"), + MTK_FUNCTION(1, "TDP2") + ), + MTK_PIN( + PINCTRL_PIN(78, "TCN"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 78), + MTK_FUNCTION(0, "GPI78"), + MTK_FUNCTION(1, "TCN") + ), + MTK_PIN( + PINCTRL_PIN(79, "TCP"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 79), + MTK_FUNCTION(0, "GPI79"), + MTK_FUNCTION(1, "TCP") + ), + MTK_PIN( + PINCTRL_PIN(80, "TDN1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 80), + MTK_FUNCTION(0, "GPI80"), + MTK_FUNCTION(1, "TDN1") + ), + MTK_PIN( + PINCTRL_PIN(81, "TDP1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 81), + MTK_FUNCTION(0, "GPI81"), + MTK_FUNCTION(1, "TDP1") + ), + MTK_PIN( + PINCTRL_PIN(82, "TDN0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 82), + MTK_FUNCTION(0, "GPI82"), + MTK_FUNCTION(1, "TDN0") + ), + MTK_PIN( + PINCTRL_PIN(83, "TDP0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 83), + MTK_FUNCTION(0, "GPI83"), + MTK_FUNCTION(1, "TDP0") + ), + MTK_PIN( + PINCTRL_PIN(84, "RDN0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 84), + MTK_FUNCTION(0, "GPI84"), + MTK_FUNCTION(1, "RDN0") + ), + MTK_PIN( + PINCTRL_PIN(85, "RDP0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 85), + MTK_FUNCTION(0, "GPI85"), + MTK_FUNCTION(1, "RDP0") + ), + MTK_PIN( + PINCTRL_PIN(86, "RDN1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 86), + MTK_FUNCTION(0, "GPI86"), + MTK_FUNCTION(1, "RDN1") + ), + MTK_PIN( + PINCTRL_PIN(87, "RDP1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 87), + MTK_FUNCTION(0, "GPI87"), + MTK_FUNCTION(1, "RDP1") + ), + MTK_PIN( + PINCTRL_PIN(88, "RCN"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 88), + MTK_FUNCTION(0, "GPI88"), + MTK_FUNCTION(1, "RCN") + ), + MTK_PIN( + PINCTRL_PIN(89, "RCP"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 89), + MTK_FUNCTION(0, "GPI89"), + MTK_FUNCTION(1, "RCP") + ), + MTK_PIN( + PINCTRL_PIN(90, "RDN2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 90), + MTK_FUNCTION(0, "GPI90"), + MTK_FUNCTION(1, "RDN2"), + MTK_FUNCTION(2, "CMDAT8") + ), + MTK_PIN( + PINCTRL_PIN(91, "RDP2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 91), + MTK_FUNCTION(0, "GPI91"), + MTK_FUNCTION(1, "RDP2"), + MTK_FUNCTION(2, "CMDAT9") + ), + MTK_PIN( + PINCTRL_PIN(92, "RDN3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 92), + MTK_FUNCTION(0, "GPI92"), + MTK_FUNCTION(1, "RDN3"), + MTK_FUNCTION(2, "CMDAT4") + ), + MTK_PIN( + PINCTRL_PIN(93, "RDP3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 93), + MTK_FUNCTION(0, "GPI93"), + MTK_FUNCTION(1, "RDP3"), + MTK_FUNCTION(2, "CMDAT5") + ), + MTK_PIN( + PINCTRL_PIN(94, "RCN_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 94), + MTK_FUNCTION(0, "GPI94"), + MTK_FUNCTION(1, "RCN_A"), + MTK_FUNCTION(2, "CMDAT6") + ), + MTK_PIN( + PINCTRL_PIN(95, "RCP_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 95), + MTK_FUNCTION(0, "GPI95"), + MTK_FUNCTION(1, "RCP_A"), + MTK_FUNCTION(2, "CMDAT7") + ), + MTK_PIN( + PINCTRL_PIN(96, "RDN1_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 96), + MTK_FUNCTION(0, "GPI96"), + MTK_FUNCTION(1, "RDN1_A"), + MTK_FUNCTION(2, "CMDAT2"), + MTK_FUNCTION(3, "CMCSD2") + ), + MTK_PIN( + PINCTRL_PIN(97, "RDP1_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 97), + MTK_FUNCTION(0, "GPI97"), + MTK_FUNCTION(1, "RDP1_A"), + MTK_FUNCTION(2, "CMDAT3"), + MTK_FUNCTION(3, "CMCSD3") + ), + MTK_PIN( + PINCTRL_PIN(98, "RDN0_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 98), + MTK_FUNCTION(0, "GPI98"), + MTK_FUNCTION(1, "RDN0_A"), + MTK_FUNCTION(2, "CMHSYNC") + ), + MTK_PIN( + PINCTRL_PIN(99, "RDP0_A"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 99), + MTK_FUNCTION(0, "GPI99"), + MTK_FUNCTION(1, "RDP0_A"), + MTK_FUNCTION(2, "CMVSYNC") + ), + MTK_PIN( + PINCTRL_PIN(100, "CMDAT0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 100), + MTK_FUNCTION(0, "GPIO100"), + MTK_FUNCTION(1, "CMDAT0"), + MTK_FUNCTION(2, "CMCSD0"), + MTK_FUNCTION(3, "ANT_SEL2"), + MTK_FUNCTION(5, "TDM_RX_MCK"), + MTK_FUNCTION(7, "DBG_MON_B[21]") + ), + MTK_PIN( + PINCTRL_PIN(101, "CMDAT1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 101), + MTK_FUNCTION(0, "GPIO101"), + MTK_FUNCTION(1, "CMDAT1"), + MTK_FUNCTION(2, "CMCSD1"), + MTK_FUNCTION(3, "ANT_SEL3"), + MTK_FUNCTION(4, "CMFLASH"), + MTK_FUNCTION(5, "TDM_RX_BCK"), + MTK_FUNCTION(7, "DBG_MON_B[22]") + ), + MTK_PIN( + PINCTRL_PIN(102, "CMMCLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 102), + MTK_FUNCTION(0, "GPIO102"), + MTK_FUNCTION(1, "CMMCLK"), + MTK_FUNCTION(3, "ANT_SEL4"), + MTK_FUNCTION(5, "TDM_RX_LRCK"), + MTK_FUNCTION(7, "DBG_MON_B[23]") + ), + MTK_PIN( + PINCTRL_PIN(103, "CMPCLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 103), + MTK_FUNCTION(0, "GPIO103"), + MTK_FUNCTION(1, "CMPCLK"), + MTK_FUNCTION(2, "CMCSK"), + MTK_FUNCTION(3, "ANT_SEL5"), + MTK_FUNCTION(5, " TDM_RX_DI"), + MTK_FUNCTION(7, "DBG_MON_B[24]") + ), + MTK_PIN( + PINCTRL_PIN(104, "MSDC1_CMD"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 104), + MTK_FUNCTION(0, "GPIO104"), + MTK_FUNCTION(1, "MSDC1_CMD"), + MTK_FUNCTION(4, "SQICS"), + MTK_FUNCTION(7, "DBG_MON_B[25]") + ), + MTK_PIN( + PINCTRL_PIN(105, "MSDC1_CLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 105), + MTK_FUNCTION(0, "GPIO105"), + MTK_FUNCTION(1, "MSDC1_CLK"), + MTK_FUNCTION(2, "UDI_NTRST_XI"), + MTK_FUNCTION(3, "DFD_NTRST_XI"), + MTK_FUNCTION(4, "SQISO"), + MTK_FUNCTION(5, "GPUEJ_NTRST_XI"), + MTK_FUNCTION(7, "DBG_MON_B[26]") + ), + MTK_PIN( + PINCTRL_PIN(106, "MSDC1_DAT0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 106), + MTK_FUNCTION(0, "GPIO106"), + MTK_FUNCTION(1, "MSDC1_DAT0"), + MTK_FUNCTION(2, "UDI_TMS_XI"), + MTK_FUNCTION(3, "DFD_TMS_XI"), + MTK_FUNCTION(4, "SQISI"), + MTK_FUNCTION(5, "GPUEJ_TMS_XI"), + MTK_FUNCTION(7, "DBG_MON_B[27]") + ), + MTK_PIN( + PINCTRL_PIN(107, "MSDC1_DAT1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 107), + MTK_FUNCTION(0, "GPIO107"), + MTK_FUNCTION(1, "MSDC1_DAT1"), + MTK_FUNCTION(2, "UDI_TCK_XI"), + MTK_FUNCTION(3, "DFD_TCK_XI"), + MTK_FUNCTION(4, "SQIWP"), + MTK_FUNCTION(5, "GPUEJ_TCK_XI"), + MTK_FUNCTION(7, "DBG_MON_B[28]") + ), + MTK_PIN( + PINCTRL_PIN(108, "MSDC1_DAT2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 108), + MTK_FUNCTION(0, "GPIO108"), + MTK_FUNCTION(1, "MSDC1_DAT2"), + MTK_FUNCTION(2, "UDI_TDI_XI"), + MTK_FUNCTION(3, "DFD_TDI_XI"), + MTK_FUNCTION(4, "SQIRST"), + MTK_FUNCTION(5, "GPUEJ_TDI_XI"), + MTK_FUNCTION(7, "DBG_MON_B[29]") + ), + MTK_PIN( + PINCTRL_PIN(109, "MSDC1_DAT3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 109), + MTK_FUNCTION(0, "GPIO109"), + MTK_FUNCTION(1, "MSDC1_DAT3"), + MTK_FUNCTION(2, "UDI_TDO"), + MTK_FUNCTION(3, "DFD_TDO"), + MTK_FUNCTION(4, "SQICK"), + MTK_FUNCTION(5, "GPUEJ_TDO"), + MTK_FUNCTION(7, "DBG_MON_B[30]") + ), + MTK_PIN( + PINCTRL_PIN(110, "MSDC0_DAT7"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 110), + MTK_FUNCTION(0, "GPIO110"), + MTK_FUNCTION(1, "MSDC0_DAT7"), + MTK_FUNCTION(4, "NLD7") + ), + MTK_PIN( + PINCTRL_PIN(111, "MSDC0_DAT6"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 111), + MTK_FUNCTION(0, "GPIO111"), + MTK_FUNCTION(1, "MSDC0_DAT6"), + MTK_FUNCTION(4, "NLD6") + ), + MTK_PIN( + PINCTRL_PIN(112, "MSDC0_DAT5"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 112), + MTK_FUNCTION(0, "GPIO112"), + MTK_FUNCTION(1, "MSDC0_DAT5"), + MTK_FUNCTION(4, "NLD4") + ), + MTK_PIN( + PINCTRL_PIN(113, "MSDC0_DAT4"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 113), + MTK_FUNCTION(0, "GPIO113"), + MTK_FUNCTION(1, "MSDC0_DAT4"), + MTK_FUNCTION(4, "NLD3") + ), + MTK_PIN( + PINCTRL_PIN(114, "MSDC0_RSTB"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 114), + MTK_FUNCTION(0, "GPIO114"), + MTK_FUNCTION(1, "MSDC0_RSTB"), + MTK_FUNCTION(4, "NLD0") + ), + MTK_PIN( + PINCTRL_PIN(115, "MSDC0_CMD"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 115), + MTK_FUNCTION(0, "GPIO115"), + MTK_FUNCTION(1, "MSDC0_CMD"), + MTK_FUNCTION(4, "NALE") + ), + MTK_PIN( + PINCTRL_PIN(116, "MSDC0_CLK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 116), + MTK_FUNCTION(0, "GPIO116"), + MTK_FUNCTION(1, "MSDC0_CLK"), + MTK_FUNCTION(4, "NWEB") + ), + MTK_PIN( + PINCTRL_PIN(117, "MSDC0_DAT3"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 117), + MTK_FUNCTION(0, "GPIO117"), + MTK_FUNCTION(1, "MSDC0_DAT3"), + MTK_FUNCTION(4, "NLD1") + ), + MTK_PIN( + PINCTRL_PIN(118, "MSDC0_DAT2"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 118), + MTK_FUNCTION(0, "GPIO118"), + MTK_FUNCTION(1, "MSDC0_DAT2"), + MTK_FUNCTION(4, "NLD5") + ), + MTK_PIN( + PINCTRL_PIN(119, "MSDC0_DAT1"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 119), + MTK_FUNCTION(0, "GPIO119"), + MTK_FUNCTION(1, "MSDC0_DAT1"), + MTK_FUNCTION(4, "NLD8") + ), + MTK_PIN( + PINCTRL_PIN(120, "MSDC0_DAT0"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 120), + MTK_FUNCTION(0, "GPIO120"), + MTK_FUNCTION(1, "MSDC0_DAT0"), + MTK_FUNCTION(4, "WATCHDOG"), + MTK_FUNCTION(5, "NLD2") + ), + MTK_PIN( + PINCTRL_PIN(121, "CEC"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 121), + MTK_FUNCTION(0, "GPIO121"), + MTK_FUNCTION(1, "CEC") + ), + MTK_PIN( + PINCTRL_PIN(122, "HTPLG"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 122), + MTK_FUNCTION(0, "GPIO122"), + MTK_FUNCTION(1, "HTPLG") + ), + MTK_PIN( + PINCTRL_PIN(123, "HDMISCK"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 123), + MTK_FUNCTION(0, "GPIO123"), + MTK_FUNCTION(1, "HDMISCK") + ), + MTK_PIN( + PINCTRL_PIN(124, "HDMISD"), + NULL, "mt8167", + MTK_EINT_FUNCTION(0, 124), + MTK_FUNCTION(0, "GPIO124"), + MTK_FUNCTION(1, "HDMISD") + ), +}; + +#endif /* __PINCTRL_MTK_MT8167_H */ From 07ae3f0784c14c3ae8e20ed11c62139f45a8ac7b Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 8 Sep 2020 16:11:59 +0800 Subject: [PATCH 50/78] pinctrl: imx: Use function callbacks for SCU related functions Use function callbacks for SCU related functions in pinctrl-imx.c in order to support the scenario of PINCTRL_IMX is built in while PINCTRL_IMX_SCU is built as module, all drivers using SCU pinctrl driver need to initialize the SCU related function callback, and no need to check CONFIG_PINCTRL_IMX_SCU anymore, hence stub functions also can be removed. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/1599552721-24872-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 8 +-- drivers/pinctrl/freescale/pinctrl-imx.h | 57 ++++++++------------- drivers/pinctrl/freescale/pinctrl-imx8dxl.c | 3 ++ drivers/pinctrl/freescale/pinctrl-imx8qm.c | 3 ++ drivers/pinctrl/freescale/pinctrl-imx8qxp.c | 3 ++ 5 files changed, 35 insertions(+), 39 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 507e4affcd73..b80c450819e5 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -373,7 +373,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, const struct imx_pinctrl_soc_info *info = ipctl->info; if (info->flags & IMX_USE_SCU) - return imx_pinconf_get_scu(pctldev, pin_id, config); + return info->imx_pinconf_get(pctldev, pin_id, config); else return imx_pinconf_get_mmio(pctldev, pin_id, config); } @@ -423,7 +423,7 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, const struct imx_pinctrl_soc_info *info = ipctl->info; if (info->flags & IMX_USE_SCU) - return imx_pinconf_set_scu(pctldev, pin_id, + return info->imx_pinconf_set(pctldev, pin_id, configs, num_configs); else return imx_pinconf_set_mmio(pctldev, pin_id, @@ -440,7 +440,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, int ret; if (info->flags & IMX_USE_SCU) { - ret = imx_pinconf_get_scu(pctldev, pin_id, &config); + ret = info->imx_pinconf_get(pctldev, pin_id, &config); if (ret) { dev_err(ipctl->dev, "failed to get %s pinconf\n", pin_get_name(pctldev, pin_id)); @@ -629,7 +629,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np, for (i = 0; i < grp->num_pins; i++) { pin = &((struct imx_pin *)(grp->data))[i]; if (info->flags & IMX_USE_SCU) - imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i], + info->imx_pinctrl_parse_pin(ipctl, &grp->pins[i], pin, &list); else imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 333d32b947b1..fd8c4b6b3e36 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -75,6 +75,21 @@ struct imx_cfg_params_decode { bool invert; }; +/** + * @dev: a pointer back to containing device + * @base: the offset to the controller in virtual memory + */ +struct imx_pinctrl { + struct device *dev; + struct pinctrl_dev *pctl; + void __iomem *base; + void __iomem *input_sel_base; + const struct imx_pinctrl_soc_info *info; + struct imx_pin_reg *pin_regs; + unsigned int group_index; + struct mutex mutex; +}; + struct imx_pinctrl_soc_info { const struct pinctrl_pin_desc *pins; unsigned int npins; @@ -98,21 +113,13 @@ struct imx_pinctrl_soc_info { struct pinctrl_gpio_range *range, unsigned offset, bool input); -}; - -/** - * @dev: a pointer back to containing device - * @base: the offset to the controller in virtual memory - */ -struct imx_pinctrl { - struct device *dev; - struct pinctrl_dev *pctl; - void __iomem *base; - void __iomem *input_sel_base; - const struct imx_pinctrl_soc_info *info; - struct imx_pin_reg *pin_regs; - unsigned int group_index; - struct mutex mutex; + int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *config); + int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id, + unsigned long *configs, unsigned int num_configs); + void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p); }; #define IMX_CFG_PARAMS_DECODE(p, m, o) \ @@ -137,7 +144,6 @@ struct imx_pinctrl { int imx_pinctrl_probe(struct platform_device *pdev, const struct imx_pinctrl_soc_info *info); -#ifdef CONFIG_PINCTRL_IMX_SCU #define BM_PAD_CTL_GP_ENABLE BIT(30) #define BM_PAD_CTL_IFMUX_ENABLE BIT(31) #define BP_PAD_CTL_IFMUX 27 @@ -150,23 +156,4 @@ int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, unsigned int *pin_id, struct imx_pin *pin, const __be32 **list_p); -#else -static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) -{ - return -EINVAL; -} -static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) -{ - return -EINVAL; -} -static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, - unsigned int *pin_id, - struct imx_pin *pin, - const __be32 **list_p) -{ -} -#endif #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c index 12b97daa0407..d3020c0cd55d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -159,6 +159,9 @@ static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { .pins = imx8dxl_pinctrl_pads, .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), .flags = IMX_USE_SCU, + .imx_pinconf_get = imx_pinconf_get_scu, + .imx_pinconf_set = imx_pinconf_set_scu, + .imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu, }; static const struct of_device_id imx8dxl_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qm.c b/drivers/pinctrl/freescale/pinctrl-imx8qm.c index 095acf494641..8f46b9404cd7 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qm.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qm.c @@ -292,6 +292,9 @@ static const struct imx_pinctrl_soc_info imx8qm_pinctrl_info = { .pins = imx8qm_pinctrl_pads, .npins = ARRAY_SIZE(imx8qm_pinctrl_pads), .flags = IMX_USE_SCU, + .imx_pinconf_get = imx_pinconf_get_scu, + .imx_pinconf_set = imx_pinconf_set_scu, + .imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu, }; static const struct of_device_id imx8qm_pinctrl_of_match[] = { diff --git a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c index 81ebd4c952ec..6776ad6a3a27 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx8qxp.c +++ b/drivers/pinctrl/freescale/pinctrl-imx8qxp.c @@ -198,6 +198,9 @@ static struct imx_pinctrl_soc_info imx8qxp_pinctrl_info = { .pins = imx8qxp_pinctrl_pads, .npins = ARRAY_SIZE(imx8qxp_pinctrl_pads), .flags = IMX_USE_SCU, + .imx_pinconf_get = imx_pinconf_get_scu, + .imx_pinconf_set = imx_pinconf_set_scu, + .imx_pinctrl_parse_pin = imx_pinctrl_parse_pin_scu, }; static const struct of_device_id imx8qxp_pinctrl_of_match[] = { From 0080c5342826ad2b0df7e8804f94dd65836ecff6 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 8 Sep 2020 16:12:00 +0800 Subject: [PATCH 51/78] pinctrl: imx: Support building SCU pinctrl core driver as module Change PINCTR_IMX_SCU to tristate, add module author, description and license to support building SCU pinctrl core driver as module. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/1599552721-24872-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 2 +- drivers/pinctrl/freescale/pinctrl-scu.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 08fcf5c79296..71989162c4bc 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -7,7 +7,7 @@ config PINCTRL_IMX select REGMAP config PINCTRL_IMX_SCU - bool + tristate depends on IMX_SCU select PINCTRL_IMX diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c index 9df45d3e3226..59b5f8a35111 100644 --- a/drivers/pinctrl/freescale/pinctrl-scu.c +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -123,3 +124,7 @@ void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, pin_scu->mux_mode, pin_scu->config); } EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu); + +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver"); +MODULE_LICENSE("GPL v2"); From 7233f7cf4b025ce3bddf9ae34cab45fba74c9ea0 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 8 Sep 2020 16:12:01 +0800 Subject: [PATCH 52/78] pinctrl: imx: Support building i.MX pinctrl core driver as module Change PINCTRL_IMX to tristate to support loadable module build. And i.MX common pinctrl driver should depend on CONFIG_OF to make sure no build error when i.MX common pinctrl driver is enabled for different architectures without CONFIG_OF. Also add module author, description and license. Signed-off-by: Anson Huang Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/1599552721-24872-3-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 3 ++- drivers/pinctrl/freescale/pinctrl-imx.c | 5 +++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index 71989162c4bc..a1fbb3b9ae34 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only config PINCTRL_IMX - bool + tristate + depends on OF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index b80c450819e5..daf28bc5661d 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -898,3 +899,7 @@ const struct dev_pm_ops imx_pinctrl_pm_ops = { imx_pinctrl_resume) }; EXPORT_SYMBOL_GPL(imx_pinctrl_pm_ops); + +MODULE_AUTHOR("Dong Aisheng "); +MODULE_DESCRIPTION("NXP i.MX common pinctrl driver"); +MODULE_LICENSE("GPL v2"); From cdfd8606e096a94265984efc247e938f8dad8034 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 28 Sep 2020 20:45:15 +0200 Subject: [PATCH 53/78] dt-bindings: pinctrl: renesas,pfc: align example GPIO hog name with dtschema The convention for node names is to use hyphens, not underscores. dtschema expects GPIO hogs to end with 'hog' suffix. Adjust the example DTS in the binding. No changes to binding itself. Reported-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200928184515.7345-1-krzk@kernel.org Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml index 4efe117550bd..5b5b1b9d2ec7 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -148,7 +148,7 @@ examples: <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; power-domains = <&pd_c5>; - lcd0_mux { + lcd0-mux-hog { /* DBGMD/LCDC0/FSIA MUX */ gpio-hog; gpios = <176 0>; From 7e8d8ac78f35b2fc8cb1548f4ea5f5d9eaf3b3f8 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Sep 2020 12:26:29 +0930 Subject: [PATCH 54/78] pinctrl: aspeed: Format pinconf debug consistent with pinmux When displaying which pinconf register and field is being touched, format the field mask so that it's consistent with the way the pinmux portion formats the mask. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Link: https://lore.kernel.org/r/20200910025631.2996342-2-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 53f3f8aec695..2e0260c1a57c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -539,9 +539,9 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (rc < 0) return rc; - pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n", - __func__, pconf->reg, __ffs(pconf->mask), - pmap->val, param, arg, offset); + pr_debug("%s: Set SCU%02X[0x%08X]=0x%X for param %d(=%d) on pin %d\n", + __func__, pconf->reg, pconf->mask, + val, param, arg, offset); } return 0; From 1d6db5ae6b090d1a8edfcb36b9bf47c5f4fe27f6 Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Sep 2020 12:26:30 +0930 Subject: [PATCH 55/78] pinctrl: aspeed: Use the right pinconf mask The Aspeed pinconf data structures are split into 'conf' and 'map' types, where the 'conf' struct defines which register and bitfield to manipulate, while the 'map' struct defines what value to write to the register and bitfield. Both structs have a mask member, and the wrong mask was being used to tell the regmap which bits to update. A todo is to look at whether we can remove the mask from the 'map' struct. Fixes: 5f52c853847f ("pinctrl: aspeed: Use masks to describe pinconf bitfields") Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Cc: Johnny Huang Link: https://lore.kernel.org/r/20200910025631.2996342-3-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 2e0260c1a57c..6a94eaecf638 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -534,7 +534,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, val = pmap->val << __ffs(pconf->mask); rc = regmap_update_bits(pdata->scu, pconf->reg, - pmap->mask, val); + pconf->mask, val); if (rc < 0) return rc; From 05c0a8a9feda386f7ba4ee65f07f2541cead369f Mon Sep 17 00:00:00 2001 From: Andrew Jeffery Date: Thu, 10 Sep 2020 12:26:31 +0930 Subject: [PATCH 56/78] pinctrl: aspeed-g6: Add bias controls for 1.8V GPIO banks These were skipped in the original patches adding pinconf support for the AST2600. Signed-off-by: Andrew Jeffery Reviewed-by: Joel Stanley Cc: Johnny Huang Link: https://lore.kernel.org/r/20200910025631.2996342-4-andrew@aj.id.au Signed-off-by: Linus Walleij --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 7efe6dbe4398..34803a6c7664 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -19,6 +19,7 @@ #define SCU400 0x400 /* Multi-function Pin Control #1 */ #define SCU404 0x404 /* Multi-function Pin Control #2 */ +#define SCU40C 0x40C /* Multi-function Pin Control #3 */ #define SCU410 0x410 /* Multi-function Pin Control #4 */ #define SCU414 0x414 /* Multi-function Pin Control #5 */ #define SCU418 0x418 /* Multi-function Pin Control #6 */ @@ -2591,6 +2592,22 @@ static struct aspeed_pin_config aspeed_g6_configs[] = { /* MAC4 */ { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)}, { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)}, + + /* GPIO18E */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, Y4, SCU40C, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, Y4, SCU40C, 4), + /* GPIO18D */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AB4, AC5, SCU40C, 3), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AB4, AC5, SCU40C, 3), + /* GPIO18C */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E4, E1, SCU40C, 2), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E4, E1, SCU40C, 2), + /* GPIO18B */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D3, SCU40C, 1), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D3, SCU40C, 1), + /* GPIO18A */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C6, A2, SCU40C, 0), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C6, A2, SCU40C, 0), }; /** From d3ef8c6b22861232d38934aa9b85123fdd6563b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Sun, 13 Sep 2020 14:58:34 +0800 Subject: [PATCH 57/78] pinctrl: Ingenic: Add SSI pins support for JZ4770 and JZ4780. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SSI pins support for the JZ4770 SoC and the JZ4780 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20200913065836.12156-2-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 267 ++++++++++++++++++++++++++++++ 1 file changed, 267 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index a8d1b53ec4c1..00f29fd684fa 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -633,6 +633,46 @@ static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, }; static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, }; static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, }; static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, }; +static int jz4770_ssi0_dt_a_pins[] = { 0x15, }; +static int jz4770_ssi0_dt_b_pins[] = { 0x35, }; +static int jz4770_ssi0_dt_d_pins[] = { 0x55, }; +static int jz4770_ssi0_dt_e_pins[] = { 0x71, }; +static int jz4770_ssi0_dr_a_pins[] = { 0x14, }; +static int jz4770_ssi0_dr_b_pins[] = { 0x34, }; +static int jz4770_ssi0_dr_d_pins[] = { 0x54, }; +static int jz4770_ssi0_dr_e_pins[] = { 0x6e, }; +static int jz4770_ssi0_clk_a_pins[] = { 0x12, }; +static int jz4770_ssi0_clk_b_pins[] = { 0x3c, }; +static int jz4770_ssi0_clk_d_pins[] = { 0x58, }; +static int jz4770_ssi0_clk_e_pins[] = { 0x6f, }; +static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, }; +static int jz4770_ssi0_gpc_d_pins[] = { 0x56, }; +static int jz4770_ssi0_gpc_e_pins[] = { 0x73, }; +static int jz4770_ssi0_ce0_a_pins[] = { 0x13, }; +static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, }; +static int jz4770_ssi0_ce0_d_pins[] = { 0x59, }; +static int jz4770_ssi0_ce0_e_pins[] = { 0x70, }; +static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, }; +static int jz4770_ssi0_ce1_d_pins[] = { 0x57, }; +static int jz4770_ssi0_ce1_e_pins[] = { 0x72, }; +static int jz4770_ssi1_dt_b_pins[] = { 0x35, }; +static int jz4770_ssi1_dt_d_pins[] = { 0x55, }; +static int jz4770_ssi1_dt_e_pins[] = { 0x71, }; +static int jz4770_ssi1_dr_b_pins[] = { 0x34, }; +static int jz4770_ssi1_dr_d_pins[] = { 0x54, }; +static int jz4770_ssi1_dr_e_pins[] = { 0x6e, }; +static int jz4770_ssi1_clk_b_pins[] = { 0x3c, }; +static int jz4770_ssi1_clk_d_pins[] = { 0x58, }; +static int jz4770_ssi1_clk_e_pins[] = { 0x6f, }; +static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, }; +static int jz4770_ssi1_gpc_d_pins[] = { 0x56, }; +static int jz4770_ssi1_gpc_e_pins[] = { 0x73, }; +static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, }; +static int jz4770_ssi1_ce0_d_pins[] = { 0x59, }; +static int jz4770_ssi1_ce0_e_pins[] = { 0x70, }; +static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, }; +static int jz4770_ssi1_ce1_d_pins[] = { 0x57, }; +static int jz4770_ssi1_ce1_e_pins[] = { 0x72, }; static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, }; static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, }; static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, }; @@ -703,6 +743,46 @@ static int jz4770_uart2_data_funcs[] = { 0, 0, }; static int jz4770_uart2_hwflow_funcs[] = { 0, 0, }; static int jz4770_uart3_data_funcs[] = { 0, 1, }; static int jz4770_uart3_hwflow_funcs[] = { 0, 0, }; +static int jz4770_ssi0_dt_a_funcs[] = { 2, }; +static int jz4770_ssi0_dt_b_funcs[] = { 1, }; +static int jz4770_ssi0_dt_d_funcs[] = { 1, }; +static int jz4770_ssi0_dt_e_funcs[] = { 0, }; +static int jz4770_ssi0_dr_a_funcs[] = { 1, }; +static int jz4770_ssi0_dr_b_funcs[] = { 1, }; +static int jz4770_ssi0_dr_d_funcs[] = { 1, }; +static int jz4770_ssi0_dr_e_funcs[] = { 0, }; +static int jz4770_ssi0_clk_a_funcs[] = { 2, }; +static int jz4770_ssi0_clk_b_funcs[] = { 1, }; +static int jz4770_ssi0_clk_d_funcs[] = { 1, }; +static int jz4770_ssi0_clk_e_funcs[] = { 0, }; +static int jz4770_ssi0_gpc_b_funcs[] = { 1, }; +static int jz4770_ssi0_gpc_d_funcs[] = { 1, }; +static int jz4770_ssi0_gpc_e_funcs[] = { 0, }; +static int jz4770_ssi0_ce0_a_funcs[] = { 2, }; +static int jz4770_ssi0_ce0_b_funcs[] = { 1, }; +static int jz4770_ssi0_ce0_d_funcs[] = { 1, }; +static int jz4770_ssi0_ce0_e_funcs[] = { 0, }; +static int jz4770_ssi0_ce1_b_funcs[] = { 1, }; +static int jz4770_ssi0_ce1_d_funcs[] = { 1, }; +static int jz4770_ssi0_ce1_e_funcs[] = { 0, }; +static int jz4770_ssi1_dt_b_funcs[] = { 2, }; +static int jz4770_ssi1_dt_d_funcs[] = { 2, }; +static int jz4770_ssi1_dt_e_funcs[] = { 1, }; +static int jz4770_ssi1_dr_b_funcs[] = { 2, }; +static int jz4770_ssi1_dr_d_funcs[] = { 2, }; +static int jz4770_ssi1_dr_e_funcs[] = { 1, }; +static int jz4770_ssi1_clk_b_funcs[] = { 2, }; +static int jz4770_ssi1_clk_d_funcs[] = { 2, }; +static int jz4770_ssi1_clk_e_funcs[] = { 1, }; +static int jz4770_ssi1_gpc_b_funcs[] = { 2, }; +static int jz4770_ssi1_gpc_d_funcs[] = { 2, }; +static int jz4770_ssi1_gpc_e_funcs[] = { 1, }; +static int jz4770_ssi1_ce0_b_funcs[] = { 2, }; +static int jz4770_ssi1_ce0_d_funcs[] = { 2, }; +static int jz4770_ssi1_ce0_e_funcs[] = { 1, }; +static int jz4770_ssi1_ce1_b_funcs[] = { 2, }; +static int jz4770_ssi1_ce1_d_funcs[] = { 2, }; +static int jz4770_ssi1_ce1_e_funcs[] = { 1, }; static int jz4770_mmc0_1bit_a_funcs[] = { 1, 1, 0, }; static int jz4770_mmc0_4bit_a_funcs[] = { 1, 1, 1, }; static int jz4770_mmc0_1bit_e_funcs[] = { 0, 0, 0, }; @@ -763,6 +843,46 @@ static const struct group_desc jz4770_groups[] = { INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow), INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), + INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a), + INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b), + INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d), + INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), + INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a), + INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b), + INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d), + INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), + INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a), + INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b), + INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d), + INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), + INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b), + INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d), + INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), + INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a), + INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b), + INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d), + INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), + INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b), + INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d), + INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), + INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b), + INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d), + INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), + INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b), + INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d), + INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), + INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b), + INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d), + INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), + INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b), + INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d), + INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), + INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b), + INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d), + INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), + INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b), + INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d), + INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e), @@ -815,6 +935,22 @@ static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", }; static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", }; static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", }; +static const char *jz4770_ssi0_groups[] = { + "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", + "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", + "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e", + "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", + "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", + "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", +}; +static const char *jz4770_ssi1_groups[] = { + "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", + "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", + "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", + "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", + "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", + "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", +}; static const char *jz4770_mmc0_groups[] = { "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e", @@ -858,6 +994,8 @@ static const struct function_desc jz4770_functions[] = { { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), }, { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), }, { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, + { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), }, + { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), }, { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), }, { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), }, { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), }, @@ -900,6 +1038,39 @@ static const struct ingenic_chip_info jz4770_chip_info = { static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; +static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, }; +static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, }; +static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, }; +static int jz4780_ssi0_dt_b_pins[] = { 0x3d, }; +static int jz4780_ssi0_dt_d_pins[] = { 0x59, }; +static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, }; +static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, }; +static int jz4780_ssi0_dr_b_pins[] = { 0x34, }; +static int jz4780_ssi0_dr_d_pins[] = { 0x54, }; +static int jz4780_ssi0_clk_a_pins[] = { 0x12, }; +static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, }; +static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, }; +static int jz4780_ssi0_clk_d_pins[] = { 0x58, }; +static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, }; +static int jz4780_ssi0_gpc_d_pins[] = { 0x56, }; +static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, }; +static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, }; +static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, }; +static int jz4780_ssi0_ce0_d_pins[] = { 0x57, }; +static int jz4780_ssi0_ce1_b_pins[] = { 0x35, }; +static int jz4780_ssi0_ce1_d_pins[] = { 0x55, }; +static int jz4780_ssi1_dt_b_pins[] = { 0x3d, }; +static int jz4780_ssi1_dt_d_pins[] = { 0x59, }; +static int jz4780_ssi1_dr_b_pins[] = { 0x34, }; +static int jz4780_ssi1_dr_d_pins[] = { 0x54, }; +static int jz4780_ssi1_clk_b_pins[] = { 0x3c, }; +static int jz4780_ssi1_clk_d_pins[] = { 0x58, }; +static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, }; +static int jz4780_ssi1_gpc_d_pins[] = { 0x56, }; +static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, }; +static int jz4780_ssi1_ce0_d_pins[] = { 0x57, }; +static int jz4780_ssi1_ce1_b_pins[] = { 0x35, }; +static int jz4780_ssi1_ce1_d_pins[] = { 0x55, }; static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; @@ -909,6 +1080,39 @@ static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; static int jz4780_uart2_data_funcs[] = { 1, 1, }; static int jz4780_uart2_hwflow_funcs[] = { 1, 1, }; static int jz4780_uart4_data_funcs[] = { 2, 2, }; +static int jz4780_ssi0_dt_a_19_funcs[] = { 2, }; +static int jz4780_ssi0_dt_a_21_funcs[] = { 2, }; +static int jz4780_ssi0_dt_a_28_funcs[] = { 2, }; +static int jz4780_ssi0_dt_b_funcs[] = { 1, }; +static int jz4780_ssi0_dt_d_funcs[] = { 1, }; +static int jz4780_ssi0_dr_a_20_funcs[] = { 2, }; +static int jz4780_ssi0_dr_a_27_funcs[] = { 2, }; +static int jz4780_ssi0_dr_b_funcs[] = { 1, }; +static int jz4780_ssi0_dr_d_funcs[] = { 1, }; +static int jz4780_ssi0_clk_a_funcs[] = { 2, }; +static int jz4780_ssi0_clk_b_5_funcs[] = { 1, }; +static int jz4780_ssi0_clk_b_28_funcs[] = { 1, }; +static int jz4780_ssi0_clk_d_funcs[] = { 1, }; +static int jz4780_ssi0_gpc_b_funcs[] = { 1, }; +static int jz4780_ssi0_gpc_d_funcs[] = { 1, }; +static int jz4780_ssi0_ce0_a_23_funcs[] = { 2, }; +static int jz4780_ssi0_ce0_a_25_funcs[] = { 2, }; +static int jz4780_ssi0_ce0_b_funcs[] = { 1, }; +static int jz4780_ssi0_ce0_d_funcs[] = { 1, }; +static int jz4780_ssi0_ce1_b_funcs[] = { 1, }; +static int jz4780_ssi0_ce1_d_funcs[] = { 1, }; +static int jz4780_ssi1_dt_b_funcs[] = { 2, }; +static int jz4780_ssi1_dt_d_funcs[] = { 2, }; +static int jz4780_ssi1_dr_b_funcs[] = { 2, }; +static int jz4780_ssi1_dr_d_funcs[] = { 2, }; +static int jz4780_ssi1_clk_b_funcs[] = { 2, }; +static int jz4780_ssi1_clk_d_funcs[] = { 2, }; +static int jz4780_ssi1_gpc_b_funcs[] = { 2, }; +static int jz4780_ssi1_gpc_d_funcs[] = { 2, }; +static int jz4780_ssi1_ce0_b_funcs[] = { 2, }; +static int jz4780_ssi1_ce0_d_funcs[] = { 2, }; +static int jz4780_ssi1_ce1_b_funcs[] = { 2, }; +static int jz4780_ssi1_ce1_d_funcs[] = { 2, }; static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; static int jz4780_i2c3_funcs[] = { 1, 1, }; static int jz4780_i2c4_e_funcs[] = { 1, 1, }; @@ -925,6 +1129,51 @@ static const struct group_desc jz4780_groups[] = { INGENIC_PIN_GROUP("uart3-data", jz4770_uart3_data), INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow), INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data), + INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19), + INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21), + INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28), + INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b), + INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d), + INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e), + INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20), + INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27), + INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b), + INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d), + INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e), + INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a), + INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5), + INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28), + INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d), + INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e), + INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b), + INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d), + INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e), + INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23), + INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25), + INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b), + INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d), + INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e), + INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b), + INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d), + INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e), + INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b), + INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d), + INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e), + INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b), + INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d), + INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e), + INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b), + INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d), + INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e), + INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b), + INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d), + INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e), + INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b), + INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d), + INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e), + INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b), + INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d), + INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e), INGENIC_PIN_GROUP("mmc0-1bit-a", jz4770_mmc0_1bit_a), INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a), INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a), @@ -972,6 +1221,22 @@ static const struct group_desc jz4780_groups[] = { static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", }; static const char *jz4780_uart4_groups[] = { "uart4-data", }; +static const char *jz4780_ssi0_groups[] = { + "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e", + "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e", + "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e", + "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e", + "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e", + "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e", +}; +static const char *jz4780_ssi1_groups[] = { + "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e", + "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e", + "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e", + "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e", + "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e", + "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e", +}; static const char *jz4780_mmc0_groups[] = { "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a", "mmc0-1bit-e", "mmc0-4bit-e", @@ -997,6 +1262,8 @@ static const struct function_desc jz4780_functions[] = { { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), }, { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), }, { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), }, + { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), }, + { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), }, { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), }, { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), }, { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), }, From d9f5dc495278605c42fb9e649688d1f03ac9a6da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Sun, 13 Sep 2020 14:58:35 +0800 Subject: [PATCH 58/78] pinctrl: Ingenic: Correct the pullup and pulldown parameters of JZ4780. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct the pullup and pulldown parameters of JZ4780 to make them consistent with the parameters on the datasheet. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20200913065836.12156-3-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 00f29fd684fa..d5ac8489ba3d 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1035,6 +1035,14 @@ static const struct ingenic_chip_info jz4770_chip_info = { .pull_downs = jz4770_pull_downs, }; +static const u32 jz4780_pull_ups[6] = { + 0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f, +}; + +static const u32 jz4780_pull_downs[6] = { + 0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0, +}; + static int jz4780_uart2_data_pins[] = { 0x66, 0x67, }; static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, }; static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, }; @@ -1301,8 +1309,8 @@ static const struct ingenic_chip_info jz4780_chip_info = { .num_groups = ARRAY_SIZE(jz4780_groups), .functions = jz4780_functions, .num_functions = ARRAY_SIZE(jz4780_functions), - .pull_ups = jz4770_pull_ups, - .pull_downs = jz4770_pull_downs, + .pull_ups = jz4780_pull_ups, + .pull_downs = jz4780_pull_downs, }; static const u32 x1000_pull_ups[4] = { From f4b5c348d65b7c76931a7f36e8240a85e4cbad29 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= Date: Sun, 13 Sep 2020 14:58:36 +0800 Subject: [PATCH 59/78] pinctrl: Ingenic: Add I2S pins support for Ingenic SoCs. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1.Add I2S pins support for the JZ4780 SoC. 2.Add I2S pins support for the X1000 SoC. 3.Add I2S pins support for the X1500 SoC. 4.Add I2S pins support for the X1830 SoC. Signed-off-by: 周琰杰 (Zhou Yanjie) Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20200913065836.12156-4-zhouyanjie@wanyeetech.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 70 +++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index d5ac8489ba3d..c8e50a58a5e5 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1083,6 +1083,11 @@ static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, }; static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, }; static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, }; static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, }; +static int jz4780_i2s_data_tx_pins[] = { 0x87, }; +static int jz4780_i2s_data_rx_pins[] = { 0x86, }; +static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, }; +static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, }; +static int jz4780_i2s_sysclk_pins[] = { 0x85, }; static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, }; static int jz4780_uart2_data_funcs[] = { 1, 1, }; @@ -1125,6 +1130,11 @@ static int jz4780_mmc0_8bit_a_funcs[] = { 1, 1, 1, 1, 1, }; static int jz4780_i2c3_funcs[] = { 1, 1, }; static int jz4780_i2c4_e_funcs[] = { 1, 1, }; static int jz4780_i2c4_f_funcs[] = { 1, 1, }; +static int jz4780_i2s_data_tx_funcs[] = { 0, }; +static int jz4780_i2s_data_rx_funcs[] = { 0, }; +static int jz4780_i2s_clk_txrx_funcs[] = { 1, 0, }; +static int jz4780_i2s_clk_rx_funcs[] = { 1, 1, }; +static int jz4780_i2s_sysclk_funcs[] = { 2, }; static int jz4780_hdmi_ddc_funcs[] = { 0, 0, }; static const struct group_desc jz4780_groups[] = { @@ -1213,6 +1223,11 @@ static const struct group_desc jz4780_groups[] = { INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3), INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e), INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f), + INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx), + INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx), + INGENIC_PIN_GROUP("i2s-clk-txrx", jz4780_i2s_clk_txrx), + INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx), + INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk), INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc), INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit), INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit), @@ -1261,6 +1276,9 @@ static const char *jz4780_nemc_groups[] = { }; static const char *jz4780_i2c3_groups[] = { "i2c3-data", }; static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", }; +static const char *jz4780_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", +}; static const char *jz4780_cim_groups[] = { "cim-data", }; static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", }; @@ -1287,6 +1305,7 @@ static const struct function_desc jz4780_functions[] = { { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), }, { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), }, { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), }, + { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), }, { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), }, { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), }, { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), }, @@ -1368,6 +1387,10 @@ static int x1000_i2c0_pins[] = { 0x38, 0x37, }; static int x1000_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, }; static int x1000_i2c2_pins[] = { 0x61, 0x60, }; +static int x1000_i2s_data_tx_pins[] = { 0x24, }; +static int x1000_i2s_data_rx_pins[] = { 0x23, }; +static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; +static int x1000_i2s_sysclk_pins[] = { 0x20, }; static int x1000_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -1430,6 +1453,10 @@ static int x1000_i2c0_funcs[] = { 0, 0, }; static int x1000_i2c1_a_funcs[] = { 2, 2, }; static int x1000_i2c1_c_funcs[] = { 0, 0, }; static int x1000_i2c2_funcs[] = { 1, 1, }; +static int x1000_i2s_data_tx_funcs[] = { 1, }; +static int x1000_i2s_data_rx_funcs[] = { 1, }; +static int x1000_i2s_clk_txrx_funcs[] = { 1, 1, }; +static int x1000_i2s_sysclk_funcs[] = { 1, }; static int x1000_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; static int x1000_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -1483,6 +1510,10 @@ static const struct group_desc x1000_groups[] = { INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c), INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2), + INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx), + INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx), + INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk), INGENIC_PIN_GROUP("cim-data", x1000_cim), INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit), INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit), @@ -1524,6 +1555,9 @@ static const char *x1000_cs2_groups[] = { "emc-cs2", }; static const char *x1000_i2c0_groups[] = { "i2c0-data", }; static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1000_i2c2_groups[] = { "i2c2-data", }; +static const char *x1000_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", +}; static const char *x1000_cim_groups[] = { "cim-data", }; static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", "lcd-no-pins", @@ -1549,6 +1583,7 @@ static const struct function_desc x1000_functions[] = { { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), }, { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), }, { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), }, + { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), }, { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), }, { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), }, { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), }, @@ -1584,6 +1619,10 @@ static int x1500_i2c0_pins[] = { 0x38, 0x37, }; static int x1500_i2c1_a_pins[] = { 0x01, 0x00, }; static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, }; static int x1500_i2c2_pins[] = { 0x61, 0x60, }; +static int x1500_i2s_data_tx_pins[] = { 0x24, }; +static int x1500_i2s_data_rx_pins[] = { 0x23, }; +static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, }; +static int x1500_i2s_sysclk_pins[] = { 0x20, }; static int x1500_cim_pins[] = { 0x08, 0x09, 0x0a, 0x0b, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c, @@ -1607,6 +1646,10 @@ static int x1500_i2c0_funcs[] = { 0, 0, }; static int x1500_i2c1_a_funcs[] = { 2, 2, }; static int x1500_i2c1_c_funcs[] = { 0, 0, }; static int x1500_i2c2_funcs[] = { 1, 1, }; +static int x1500_i2s_data_tx_funcs[] = { 1, }; +static int x1500_i2s_data_rx_funcs[] = { 1, }; +static int x1500_i2s_clk_txrx_funcs[] = { 1, 1, }; +static int x1500_i2s_sysclk_funcs[] = { 1, }; static int x1500_cim_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; static int x1500_pwm_pwm0_funcs[] = { 0, }; static int x1500_pwm_pwm1_funcs[] = { 1, }; @@ -1629,6 +1672,10 @@ static const struct group_desc x1500_groups[] = { INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a), INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c), INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2), + INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx), + INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx), + INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk), INGENIC_PIN_GROUP("cim-data", x1500_cim), { "lcd-no-pins", }, INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0), @@ -1647,6 +1694,9 @@ static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", }; static const char *x1500_i2c0_groups[] = { "i2c0-data", }; static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", }; static const char *x1500_i2c2_groups[] = { "i2c2-data", }; +static const char *x1500_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk", +}; static const char *x1500_cim_groups[] = { "cim-data", }; static const char *x1500_lcd_groups[] = { "lcd-no-pins", }; static const char *x1500_pwm0_groups[] = { "pwm0", }; @@ -1664,6 +1714,7 @@ static const struct function_desc x1500_functions[] = { { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), }, { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), }, { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), }, + { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), }, { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), }, { "lcd", x1500_lcd_groups, ARRAY_SIZE(x1500_lcd_groups), }, { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), }, @@ -1722,6 +1773,11 @@ static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, }; static int x1830_i2c0_pins[] = { 0x0c, 0x0d, }; static int x1830_i2c1_pins[] = { 0x39, 0x3a, }; static int x1830_i2c2_pins[] = { 0x5b, 0x5c, }; +static int x1830_i2s_data_tx_pins[] = { 0x53, }; +static int x1830_i2s_data_rx_pins[] = { 0x54, }; +static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, }; +static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, }; +static int x1830_i2s_sysclk_pins[] = { 0x57, }; static int x1830_lcd_rgb_18bit_pins[] = { 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6c, 0x6d, 0x6e, 0x6f, @@ -1784,6 +1840,11 @@ static int x1830_mmc1_4bit_funcs[] = { 0, 0, 0, }; static int x1830_i2c0_funcs[] = { 1, 1, }; static int x1830_i2c1_funcs[] = { 0, 0, }; static int x1830_i2c2_funcs[] = { 1, 1, }; +static int x1830_i2s_data_tx_funcs[] = { 0, }; +static int x1830_i2s_data_rx_funcs[] = { 0, }; +static int x1830_i2s_clk_txrx_funcs[] = { 0, 0, }; +static int x1830_i2s_clk_rx_funcs[] = { 0, 0, }; +static int x1830_i2s_sysclk_funcs[] = { 0, }; static int x1830_lcd_rgb_18bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1842,6 +1903,11 @@ static const struct group_desc x1830_groups[] = { INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0), INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1), INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2), + INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx), + INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx), + INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx), + INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx), + INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk), INGENIC_PIN_GROUP("lcd-rgb-18bit", x1830_lcd_rgb_18bit), INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit), INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit), @@ -1884,6 +1950,9 @@ static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; static const char *x1830_i2c0_groups[] = { "i2c0-data", }; static const char *x1830_i2c1_groups[] = { "i2c1-data", }; static const char *x1830_i2c2_groups[] = { "i2c2-data", }; +static const char *x1830_i2s_groups[] = { + "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk", +}; static const char *x1830_lcd_groups[] = { "lcd-rgb-18bit", "lcd-slcd-8bit", "lcd-slcd-16bit", "lcd-no-pins", }; @@ -1908,6 +1977,7 @@ static const struct function_desc x1830_functions[] = { { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), }, { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), }, { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), }, + { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), }, { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), }, { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), }, { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), }, From da2ab12f99d36b233d2bba0aecf55204c1bfa9e3 Mon Sep 17 00:00:00 2001 From: Liu Shixin Date: Mon, 14 Sep 2020 14:54:02 +0800 Subject: [PATCH 60/78] pinctrl: sprd: use module_platform_driver to simplify the code module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Liu Shixin Acked-by: Chunyan Zhang Link: https://lore.kernel.org/r/20200914065402.3726408-1-liushixin2@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c index 06c8671b40e7..d14f382f2392 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd-sc9860.c @@ -946,18 +946,7 @@ static struct platform_driver sprd_pinctrl_driver = { .remove = sprd_pinctrl_remove, .shutdown = sprd_pinctrl_shutdown, }; - -static int sprd_pinctrl_init(void) -{ - return platform_driver_register(&sprd_pinctrl_driver); -} -module_init(sprd_pinctrl_init); - -static void sprd_pinctrl_exit(void) -{ - platform_driver_unregister(&sprd_pinctrl_driver); -} -module_exit(sprd_pinctrl_exit); +module_platform_driver(sprd_pinctrl_driver); MODULE_DESCRIPTION("SPREADTRUM Pin Controller Driver"); MODULE_AUTHOR("Baolin Wang "); From 43b7229ef86ffb1c6720316cda8bea330fc8bc2c Mon Sep 17 00:00:00 2001 From: Liu Shixin Date: Mon, 21 Sep 2020 16:24:48 +0800 Subject: [PATCH 61/78] pinctrl: spear: simplify the return expression of spear310_pinctrl_probe Simplify the return expression. Signed-off-by: Liu Shixin Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20200921082448.2591929-1-liushixin2@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear310.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c index 393b2b97d527..9d9facc4a6e4 100644 --- a/drivers/pinctrl/spear/pinctrl-spear310.c +++ b/drivers/pinctrl/spear/pinctrl-spear310.c @@ -379,8 +379,6 @@ static const struct of_device_id spear310_pinctrl_of_match[] = { static int spear310_pinctrl_probe(struct platform_device *pdev) { - int ret; - spear3xx_machdata.groups = spear310_pingroups; spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); spear3xx_machdata.functions = spear310_functions; @@ -392,11 +390,7 @@ static int spear310_pinctrl_probe(struct platform_device *pdev) spear3xx_machdata.modes_supported = false; - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; + return spear_pinctrl_probe(pdev, &spear3xx_machdata); } static struct platform_driver spear310_pinctrl_driver = { From 5608215665b905632dc0dd43c075aeffc00b3818 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Mon, 21 Sep 2020 21:10:58 +0800 Subject: [PATCH 62/78] pinctrl: spear: simplify the return expression of tvc_connect() Simplify the return expression. Signed-off-by: Qinglang Miao Acked-by: Viresh Kumar Link: https://lore.kernel.org/r/20200921131058.92941-1-miaoqinglang@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/spear/pinctrl-spear320.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c index 99c10fc3d9b5..e629e3035543 100644 --- a/drivers/pinctrl/spear/pinctrl-spear320.c +++ b/drivers/pinctrl/spear/pinctrl-spear320.c @@ -3418,8 +3418,6 @@ static const struct of_device_id spear320_pinctrl_of_match[] = { static int spear320_pinctrl_probe(struct platform_device *pdev) { - int ret; - spear3xx_machdata.groups = spear320_pingroups; spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); spear3xx_machdata.functions = spear320_functions; @@ -3433,11 +3431,7 @@ static int spear320_pinctrl_probe(struct platform_device *pdev) pmx_init_gpio_pingroup_addr(spear3xx_machdata.gpio_pingroups, spear3xx_machdata.ngpio_pingroups, PMX_CONFIG_REG); - ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); - if (ret) - return ret; - - return 0; + return spear_pinctrl_probe(pdev, &spear3xx_machdata); } static struct platform_driver spear320_pinctrl_driver = { From 1e871d0c0bde1f7180c610d1f01f25250be20f7d Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 17 Sep 2020 16:12:56 +0300 Subject: [PATCH 63/78] dt-bindings: pinctrl: at91-pio4: add microchip,sama7g5 Add compatible string for microchip sama7g5 SoC. Signed-off-by: Eugen Hristev Reviewed-by: Nicolas Ferre Acked-by: Ludovic Desroches Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200917131257.273882-1-eugen.hristev@microchip.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt index 04d16fb69eb7..265015bc0603 100644 --- a/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt @@ -4,7 +4,9 @@ The Atmel PIO4 controller is used to select the function of a pin and to configure it. Required properties: -- compatible: "atmel,sama5d2-pinctrl". +- compatible: + "atmel,sama5d2-pinctrl" + "microchip,sama7g5-pinctrl" - reg: base address and length of the PIO controller. - interrupts: interrupt outputs from the controller, one for each bank. - interrupt-controller: mark the device node as an interrupt controller. From 737894d2654395d88e12c196b129ea018daa4bdf Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 17 Sep 2020 16:12:57 +0300 Subject: [PATCH 64/78] pinctrl: at91-pio4: add support for sama7g5 SoC Add support for sama7g5 pinctrl block, which has 5 PIO banks. Signed-off-by: Eugen Hristev Reviewed-by: Nicolas Ferre Acked-by: Ludovic Desroches Link: https://lore.kernel.org/r/20200917131257.273882-2-eugen.hristev@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-at91-pio4.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 8e5a5053a47e..578b387100d9 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -983,10 +983,17 @@ static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { .nbanks = 4, }; +static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = { + .nbanks = 5, +}; + static const struct of_device_id atmel_pctrl_of_match[] = { { .compatible = "atmel,sama5d2-pinctrl", .data = &atmel_sama5d2_pioctrl_data, + }, { + .compatible = "microchip,sama7g5-pinctrl", + .data = µchip_sama7g5_pioctrl_data, }, { /* sentinel */ } From 17f2c8d36f8c37d230bda4d2e6e9a903f57dcd19 Mon Sep 17 00:00:00 2001 From: Qinglang Miao Date: Mon, 21 Sep 2020 21:10:57 +0800 Subject: [PATCH 65/78] pinctrl: ocelot: simplify the return expression of ocelot_gpiochip_register() Simplify the return expression. Signed-off-by: Qinglang Miao Link: https://lore.kernel.org/r/20200921131057.92895-1-miaoqinglang@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 425a3d764f00..a4a1b00f7f0d 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -1120,7 +1120,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, { struct gpio_chip *gc; struct gpio_irq_chip *girq; - int ret, irq; + int irq; info->gpio_chip = ocelot_gpiolib_chip; @@ -1147,11 +1147,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, girq->handler = handle_edge_irq; } - ret = devm_gpiochip_add_data(&pdev->dev, gc, info); - if (ret) - return ret; - - return 0; + return devm_gpiochip_add_data(&pdev->dev, gc, info); } static const struct of_device_id ocelot_pinctrl_of_match[] = { From 19f599e83ac56dda5b35df1d23fb24efeecfadad Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Wed, 23 Sep 2020 00:41:57 +0800 Subject: [PATCH 66/78] pinctrl: mediatek: mt7622: add antsel pins/groups These pins are named ANTSEL[0~29] in datasheet and are used by wmac for various functions. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20200922164159.120920-1-gch981213@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mt7622.c | 103 ++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c index ce4a8a0cc19c..38c5e166fd0f 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c @@ -263,6 +263,68 @@ static const struct mtk_pin_desc mt7622_pins[] = { * hardware probably has multiple combinations of these pinouts. */ +/* ANTSEL */ +static int mt7622_antsel0_pins[] = { 91, }; +static int mt7622_antsel0_funcs[] = { 5, }; +static int mt7622_antsel1_pins[] = { 92, }; +static int mt7622_antsel1_funcs[] = { 5, }; +static int mt7622_antsel2_pins[] = { 93, }; +static int mt7622_antsel2_funcs[] = { 5, }; +static int mt7622_antsel3_pins[] = { 94, }; +static int mt7622_antsel3_funcs[] = { 5, }; +static int mt7622_antsel4_pins[] = { 95, }; +static int mt7622_antsel4_funcs[] = { 5, }; +static int mt7622_antsel5_pins[] = { 96, }; +static int mt7622_antsel5_funcs[] = { 5, }; +static int mt7622_antsel6_pins[] = { 97, }; +static int mt7622_antsel6_funcs[] = { 5, }; +static int mt7622_antsel7_pins[] = { 98, }; +static int mt7622_antsel7_funcs[] = { 5, }; +static int mt7622_antsel8_pins[] = { 99, }; +static int mt7622_antsel8_funcs[] = { 5, }; +static int mt7622_antsel9_pins[] = { 100, }; +static int mt7622_antsel9_funcs[] = { 5, }; +static int mt7622_antsel10_pins[] = { 101, }; +static int mt7622_antsel10_funcs[] = { 5, }; +static int mt7622_antsel11_pins[] = { 102, }; +static int mt7622_antsel11_funcs[] = { 5, }; +static int mt7622_antsel12_pins[] = { 73, }; +static int mt7622_antsel12_funcs[] = { 5, }; +static int mt7622_antsel13_pins[] = { 74, }; +static int mt7622_antsel13_funcs[] = { 5, }; +static int mt7622_antsel14_pins[] = { 75, }; +static int mt7622_antsel14_funcs[] = { 5, }; +static int mt7622_antsel15_pins[] = { 76, }; +static int mt7622_antsel15_funcs[] = { 5, }; +static int mt7622_antsel16_pins[] = { 77, }; +static int mt7622_antsel16_funcs[] = { 5, }; +static int mt7622_antsel17_pins[] = { 22, }; +static int mt7622_antsel17_funcs[] = { 5, }; +static int mt7622_antsel18_pins[] = { 79, }; +static int mt7622_antsel18_funcs[] = { 5, }; +static int mt7622_antsel19_pins[] = { 80, }; +static int mt7622_antsel19_funcs[] = { 5, }; +static int mt7622_antsel20_pins[] = { 81, }; +static int mt7622_antsel20_funcs[] = { 5, }; +static int mt7622_antsel21_pins[] = { 82, }; +static int mt7622_antsel21_funcs[] = { 5, }; +static int mt7622_antsel22_pins[] = { 14, }; +static int mt7622_antsel22_funcs[] = { 5, }; +static int mt7622_antsel23_pins[] = { 15, }; +static int mt7622_antsel23_funcs[] = { 5, }; +static int mt7622_antsel24_pins[] = { 16, }; +static int mt7622_antsel24_funcs[] = { 5, }; +static int mt7622_antsel25_pins[] = { 17, }; +static int mt7622_antsel25_funcs[] = { 5, }; +static int mt7622_antsel26_pins[] = { 18, }; +static int mt7622_antsel26_funcs[] = { 5, }; +static int mt7622_antsel27_pins[] = { 19, }; +static int mt7622_antsel27_funcs[] = { 5, }; +static int mt7622_antsel28_pins[] = { 20, }; +static int mt7622_antsel28_funcs[] = { 5, }; +static int mt7622_antsel29_pins[] = { 21, }; +static int mt7622_antsel29_funcs[] = { 5, }; + /* EMMC */ static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, }; static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, }; @@ -543,6 +605,36 @@ static int mt7622_wled_pins[] = { 85, }; static int mt7622_wled_funcs[] = { 0, }; static const struct group_desc mt7622_groups[] = { + PINCTRL_PIN_GROUP("antsel0", mt7622_antsel0), + PINCTRL_PIN_GROUP("antsel1", mt7622_antsel1), + PINCTRL_PIN_GROUP("antsel2", mt7622_antsel2), + PINCTRL_PIN_GROUP("antsel3", mt7622_antsel3), + PINCTRL_PIN_GROUP("antsel4", mt7622_antsel4), + PINCTRL_PIN_GROUP("antsel5", mt7622_antsel5), + PINCTRL_PIN_GROUP("antsel6", mt7622_antsel6), + PINCTRL_PIN_GROUP("antsel7", mt7622_antsel7), + PINCTRL_PIN_GROUP("antsel8", mt7622_antsel8), + PINCTRL_PIN_GROUP("antsel9", mt7622_antsel9), + PINCTRL_PIN_GROUP("antsel10", mt7622_antsel10), + PINCTRL_PIN_GROUP("antsel11", mt7622_antsel11), + PINCTRL_PIN_GROUP("antsel12", mt7622_antsel12), + PINCTRL_PIN_GROUP("antsel13", mt7622_antsel13), + PINCTRL_PIN_GROUP("antsel14", mt7622_antsel14), + PINCTRL_PIN_GROUP("antsel15", mt7622_antsel15), + PINCTRL_PIN_GROUP("antsel16", mt7622_antsel16), + PINCTRL_PIN_GROUP("antsel17", mt7622_antsel17), + PINCTRL_PIN_GROUP("antsel18", mt7622_antsel18), + PINCTRL_PIN_GROUP("antsel19", mt7622_antsel19), + PINCTRL_PIN_GROUP("antsel20", mt7622_antsel20), + PINCTRL_PIN_GROUP("antsel21", mt7622_antsel21), + PINCTRL_PIN_GROUP("antsel22", mt7622_antsel22), + PINCTRL_PIN_GROUP("antsel23", mt7622_antsel23), + PINCTRL_PIN_GROUP("antsel24", mt7622_antsel24), + PINCTRL_PIN_GROUP("antsel25", mt7622_antsel25), + PINCTRL_PIN_GROUP("antsel26", mt7622_antsel26), + PINCTRL_PIN_GROUP("antsel27", mt7622_antsel27), + PINCTRL_PIN_GROUP("antsel28", mt7622_antsel28), + PINCTRL_PIN_GROUP("antsel29", mt7622_antsel29), PINCTRL_PIN_GROUP("emmc", mt7622_emmc), PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst), PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds), @@ -663,6 +755,16 @@ static const struct group_desc mt7622_groups[] = { /* Joint those groups owning the same capability in user point of view which * allows that people tend to use through the device tree. */ +static const char *mt7622_antsel_groups[] = { "antsel0", "antsel1", "antsel2", + "antsel3", "antsel4", "antsel5", + "antsel6", "antsel7", "antsel8", + "antsel9", "antsel10", "antsel11", + "antsel12", "antsel13", "antsel14", + "antsel15", "antsel16", "antsel17", + "antsel18", "antsel19", "antsel20", + "antsel21", "antsel22", "antsel23", + "antsel24", "antsel25", "antsel26", + "antsel27", "antsel28", "antsel29",}; static const char *mt7622_emmc_groups[] = { "emmc", "emmc_rst", }; static const char *mt7622_ethernet_groups[] = { "esw", "esw_p0_p1", "esw_p2_p3_p4", "mdc_mdio", @@ -732,6 +834,7 @@ static const char *mt7622_uart_groups[] = { "uart0_0_tx_rx", static const char *mt7622_wdt_groups[] = { "watchdog", }; static const struct function_desc mt7622_functions[] = { + {"antsel", mt7622_antsel_groups, ARRAY_SIZE(mt7622_antsel_groups)}, {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)}, {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)}, {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)}, From 98a40a34e0b669d10a09fd90ec7dc425280e9e7f Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Sat, 26 Sep 2020 22:23:42 +0200 Subject: [PATCH 67/78] pinctrl: nuvoton: npcm7xx: Constify static ops structs The only usage of these structs is to assign their address to various ops fields in the pinctrl_desc struct, which are const pointers. Make them const to allow the compiler to put them in read-only memory. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20200926202342.31014-1-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index a935065cdac4..6de31b5ee358 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1601,7 +1601,7 @@ static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev, kfree(map); } -static struct pinctrl_ops npcm7xx_pinctrl_ops = { +static const struct pinctrl_ops npcm7xx_pinctrl_ops = { .get_groups_count = npcm7xx_get_groups_count, .get_group_name = npcm7xx_get_group_name, .get_group_pins = npcm7xx_get_group_pins, @@ -1701,7 +1701,7 @@ static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev, return 0; } -static struct pinmux_ops npcm7xx_pinmux_ops = { +static const struct pinmux_ops npcm7xx_pinmux_ops = { .get_functions_count = npcm7xx_get_functions_count, .get_function_name = npcm7xx_get_function_name, .get_function_groups = npcm7xx_get_function_groups, @@ -1842,7 +1842,7 @@ static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin, return 0; } -static struct pinconf_ops npcm7xx_pinconf_ops = { +static const struct pinconf_ops npcm7xx_pinconf_ops = { .is_generic = true, .pin_config_get = npcm7xx_config_get, .pin_config_set = npcm7xx_config_set, From 48548c786572f96cae5b7238da5338aa11cc9d34 Mon Sep 17 00:00:00 2001 From: Wang Xiaojun Date: Thu, 17 Sep 2020 14:41:51 +0800 Subject: [PATCH 68/78] pinctrl: mediatek: use devm_platform_ioremap_resource_byname() Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Wang Xiaojun Acked-by: Sean Wang Link: https://lore.kernel.org/r/20200917064151.2184010-1-wangxiaojun11@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-moore.c | 11 ++--------- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 9 +-------- drivers/pinctrl/mediatek/pinctrl-paris.c | 11 ++--------- 3 files changed, 5 insertions(+), 26 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index aa1068d2867f..5e00f93ac998 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -589,7 +589,6 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, const struct mtk_pin_soc *soc) { struct pinctrl_pin_desc *pins; - struct resource *res; struct mtk_pinctrl *hw; int err, i; @@ -612,14 +611,8 @@ int mtk_moore_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; for (i = 0; i < hw->soc->nbase_names; i++) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - hw->soc->base_names[i]); - if (!res) { - dev_err(&pdev->dev, "missing IO resource\n"); - return -ENXIO; - } - - hw->base[i] = devm_ioremap_resource(&pdev->dev, res); + hw->base[i] = devm_platform_ioremap_resource_byname(pdev, + hw->soc->base_names[i]); if (IS_ERR(hw->base[i])) return PTR_ERR(hw->base[i]); } diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 2f3dfb56c3fa..e8622c7e117a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -354,7 +354,6 @@ static const struct mtk_eint_xt mtk_eint_xt = { int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct resource *res; if (!IS_ENABLED(CONFIG_EINT_MTK)) return 0; @@ -366,13 +365,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) if (!hw->eint) return -ENOMEM; - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eint"); - if (!res) { - dev_err(&pdev->dev, "Unable to get eint resource\n"); - return -ENODEV; - } - - hw->eint->base = devm_ioremap_resource(&pdev->dev, res); + hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint"); if (IS_ERR(hw->eint->base)) return PTR_ERR(hw->eint->base); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index a23c18251965..623af4410b07 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -940,7 +940,6 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, { struct pinctrl_pin_desc *pins; struct mtk_pinctrl *hw; - struct resource *res; int err, i; hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL); @@ -963,14 +962,8 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return -ENOMEM; for (i = 0; i < hw->soc->nbase_names; i++) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - hw->soc->base_names[i]); - if (!res) { - dev_err(&pdev->dev, "missing IO resource\n"); - return -ENXIO; - } - - hw->base[i] = devm_ioremap_resource(&pdev->dev, res); + hw->base[i] = devm_platform_ioremap_resource_byname(pdev, + hw->soc->base_names[i]); if (IS_ERR(hw->base[i])) return PTR_ERR(hw->base[i]); } From 3163508b207f4622ba6f288127d68656a98e36a6 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Sat, 19 Sep 2020 22:08:37 +0200 Subject: [PATCH 69/78] pinctrl: Document pinctrl-single,pins when #pinctrl-cells = 2 Document the values in pinctrl-single,pins when #pinctrl-cells = <2> Fixes: 27c90e5e48d0 ("ARM: dts: am33xx-l4: change #pinctrl-cells from 1 to 2") Reported-by: Trent Piepho Signed-off-by: Drew Fustini Reviewed-by: Rob Herring Acked-by: Tony Lindgren Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200919200836.3218536-1-drew@beagleboard.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/pinctrl-single.txt | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index e705acd3612c..f903eb4471f8 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -94,16 +94,23 @@ pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt document in this directory. The pin configuration nodes for pinctrl-single are specified as pinctrl -register offset and value pairs using pinctrl-single,pins. Only the bits -specified in pinctrl-single,function-mask are updated. For example, setting -a pin for a device could be done with: +register offset and values using pinctrl-single,pins. Only the bits specified +in pinctrl-single,function-mask are updated. + +When #pinctrl-cells = 1, then setting a pin for a device could be done with: pinctrl-single,pins = <0xdc 0x118>; -Where 0xdc is the offset from the pinctrl register base address for the -device pinctrl register, and 0x118 contains the desired value of the -pinctrl register. See the device example and static board pins example -below for more information. +Where 0xdc is the offset from the pinctrl register base address for the device +pinctrl register, and 0x118 contains the desired value of the pinctrl register. + +When #pinctrl-cells = 2, then setting a pin for a device could be done with: + + pinctrl-single,pins = <0xdc 0x30 0x07>; + +Where 0x30 is the pin configuration value and 0x07 is the pin mux mode value. +These two values are OR'd together to produce the value stored at offset 0xdc. +See the device example and static board pins example below for more information. In case when one register changes more than one pin's mux the pinctrl-single,bits need to be used which takes three parameters: From cb8cc18508fb0cad74929ffd080bebafe91609e2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 29 Sep 2020 14:03:04 +0300 Subject: [PATCH 70/78] pinctrl: tigerlake: Fix register offsets for TGL-H variant It appears that almost traditionally the H variants have some deviations in the register offsets in comparison to LP ones. This is the case for Intel Tiger Lake as well. Fix register offsets for TGL-H variant. Fixes: 653d96455e1e ("pinctrl: tigerlake: Add support for Tiger Lake-H") Reported-by: Pierre-Louis Bossart Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20200929110306.40852-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 42 ++++++++++++++--------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 8c162dd5f5a1..3e354e02f408 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -15,11 +15,13 @@ #include "pinctrl-intel.h" -#define TGL_PAD_OWN 0x020 -#define TGL_PADCFGLOCK 0x080 -#define TGL_HOSTSW_OWN 0x0b0 -#define TGL_GPI_IS 0x100 -#define TGL_GPI_IE 0x120 +#define TGL_PAD_OWN 0x020 +#define TGL_LP_PADCFGLOCK 0x080 +#define TGL_H_PADCFGLOCK 0x090 +#define TGL_LP_HOSTSW_OWN 0x0b0 +#define TGL_H_HOSTSW_OWN 0x0c0 +#define TGL_GPI_IS 0x100 +#define TGL_GPI_IE 0x120 #define TGL_GPP(r, s, e, g) \ { \ @@ -29,12 +31,12 @@ .gpio_base = (g), \ } -#define TGL_COMMUNITY(b, s, e, g) \ +#define TGL_COMMUNITY(b, s, e, pl, ho, g) \ { \ .barno = (b), \ .padown_offset = TGL_PAD_OWN, \ - .padcfglock_offset = TGL_PADCFGLOCK, \ - .hostown_offset = TGL_HOSTSW_OWN, \ + .padcfglock_offset = (pl), \ + .hostown_offset = (ho), \ .is_offset = TGL_GPI_IS, \ .ie_offset = TGL_GPI_IE, \ .pin_base = (s), \ @@ -43,6 +45,12 @@ .ngpps = ARRAY_SIZE(g), \ } +#define TGL_LP_COMMUNITY(b, s, e, g) \ + TGL_COMMUNITY(b, s, e, TGL_LP_PADCFGLOCK, TGL_LP_HOSTSW_OWN, g) + +#define TGL_H_COMMUNITY(b, s, e, g) \ + TGL_COMMUNITY(b, s, e, TGL_H_PADCFGLOCK, TGL_H_HOSTSW_OWN, g) + /* Tiger Lake-LP */ static const struct pinctrl_pin_desc tgllp_pins[] = { /* GPP_B */ @@ -367,10 +375,10 @@ static const struct intel_padgroup tgllp_community5_gpps[] = { }; static const struct intel_community tgllp_communities[] = { - TGL_COMMUNITY(0, 0, 66, tgllp_community0_gpps), - TGL_COMMUNITY(1, 67, 170, tgllp_community1_gpps), - TGL_COMMUNITY(2, 171, 259, tgllp_community4_gpps), - TGL_COMMUNITY(3, 260, 276, tgllp_community5_gpps), + TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps), + TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps), + TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps), + TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps), }; static const struct intel_pinctrl_soc_data tgllp_soc_data = { @@ -723,11 +731,11 @@ static const struct intel_padgroup tglh_community5_gpps[] = { }; static const struct intel_community tglh_communities[] = { - TGL_COMMUNITY(0, 0, 78, tglh_community0_gpps), - TGL_COMMUNITY(1, 79, 180, tglh_community1_gpps), - TGL_COMMUNITY(2, 181, 217, tglh_community3_gpps), - TGL_COMMUNITY(3, 218, 266, tglh_community4_gpps), - TGL_COMMUNITY(4, 267, 290, tglh_community5_gpps), + TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps), + TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps), + TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps), + TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps), + TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps), }; static const struct intel_pinctrl_soc_data tglh_soc_data = { From 701372c7e8f173f9cd6d1d353606950e77444692 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 29 Sep 2020 14:03:05 +0300 Subject: [PATCH 71/78] pinctrl: cannonlake: Modify COMMUNITY macros to be consistent Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20200929110306.40852-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-cannonlake.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index 515f57a0d180..8078c7739d6a 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,12 +30,12 @@ .gpio_base = (g), \ } -#define CNL_COMMUNITY(b, s, e, o, g) \ +#define CNL_COMMUNITY(b, s, e, ho, g) \ { \ .barno = (b), \ .padown_offset = CNL_PAD_OWN, \ .padcfglock_offset = CNL_PADCFGLOCK, \ - .hostown_offset = (o), \ + .hostown_offset = (ho), \ .is_offset = CNL_GPI_IS, \ .ie_offset = CNL_GPI_IE, \ .pin_base = (s), \ @@ -44,10 +44,10 @@ .ngpps = ARRAY_SIZE(g), \ } -#define CNLLP_COMMUNITY(b, s, e, g) \ +#define CNL_LP_COMMUNITY(b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_LP_HOSTSW_OWN, g) -#define CNLH_COMMUNITY(b, s, e, g) \ +#define CNL_H_COMMUNITY(b, s, e, g) \ CNL_COMMUNITY(b, s, e, CNL_H_HOSTSW_OWN, g) /* Cannon Lake-H */ @@ -449,10 +449,10 @@ static const struct intel_function cnlh_functions[] = { }; static const struct intel_community cnlh_communities[] = { - CNLH_COMMUNITY(0, 0, 50, cnlh_community0_gpps), - CNLH_COMMUNITY(1, 51, 154, cnlh_community1_gpps), - CNLH_COMMUNITY(2, 155, 248, cnlh_community3_gpps), - CNLH_COMMUNITY(3, 249, 298, cnlh_community4_gpps), + CNL_H_COMMUNITY(0, 0, 50, cnlh_community0_gpps), + CNL_H_COMMUNITY(1, 51, 154, cnlh_community1_gpps), + CNL_H_COMMUNITY(2, 155, 248, cnlh_community3_gpps), + CNL_H_COMMUNITY(3, 249, 298, cnlh_community4_gpps), }; static const struct intel_pinctrl_soc_data cnlh_soc_data = { @@ -810,9 +810,9 @@ static const struct intel_padgroup cnllp_community4_gpps[] = { }; static const struct intel_community cnllp_communities[] = { - CNLLP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), - CNLLP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), - CNLLP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), + CNL_LP_COMMUNITY(0, 0, 67, cnllp_community0_gpps), + CNL_LP_COMMUNITY(1, 68, 180, cnllp_community1_gpps), + CNL_LP_COMMUNITY(2, 181, 243, cnllp_community4_gpps), }; static const struct intel_pinctrl_soc_data cnllp_soc_data = { From a0cec28c965285c4debc00b035552f8096f2aee4 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 29 Sep 2020 14:03:06 +0300 Subject: [PATCH 72/78] pinctrl: sunrisepoint: Modify COMMUNITY macros to be consistent Modify COMMUNITY macros to be consistent with Tiger Lake and others. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Link: https://lore.kernel.org/r/20200929110306.40852-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-sunrisepoint.c | 60 +++++++++----------- 1 file changed, 27 insertions(+), 33 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c index 4d7a86a5a37b..14eac924d43d 100644 --- a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c +++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c @@ -22,21 +22,26 @@ #define SPT_GPI_IS 0x100 #define SPT_GPI_IE 0x120 -#define SPT_COMMUNITY(b, s, e) \ +#define SPT_COMMUNITY(b, s, e, pl, gs, gn, g, n) \ { \ .barno = (b), \ .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_LP_PADCFGLOCK, \ + .padcfglock_offset = (pl), \ .hostown_offset = SPT_HOSTSW_OWN, \ .is_offset = SPT_GPI_IS, \ .ie_offset = SPT_GPI_IE, \ - .gpp_size = 24, \ - .gpp_num_padown_regs = 4, \ + .gpp_size = (gs), \ + .gpp_num_padown_regs = (gn), \ .pin_base = (s), \ .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = (n), \ } -#define SPTH_GPP(r, s, e, g) \ +#define SPT_LP_COMMUNITY(b, s, e) \ + SPT_COMMUNITY(b, s, e, SPT_LP_PADCFGLOCK, 24, 4, NULL, 0) + +#define SPT_H_GPP(r, s, e, g) \ { \ .reg_num = (r), \ .base = (s), \ @@ -44,19 +49,8 @@ .gpio_base = (g), \ } -#define SPTH_COMMUNITY(b, s, e, g) \ - { \ - .barno = (b), \ - .padown_offset = SPT_PAD_OWN, \ - .padcfglock_offset = SPT_H_PADCFGLOCK, \ - .hostown_offset = SPT_HOSTSW_OWN, \ - .is_offset = SPT_GPI_IS, \ - .ie_offset = SPT_GPI_IE, \ - .pin_base = (s), \ - .npins = ((e) - (s) + 1), \ - .gpps = (g), \ - .ngpps = ARRAY_SIZE(g), \ - } +#define SPT_H_COMMUNITY(b, s, e, g) \ + SPT_COMMUNITY(b, s, e, SPT_H_PADCFGLOCK, 0, 0, g, ARRAY_SIZE(g)) /* Sunrisepoint-LP */ static const struct pinctrl_pin_desc sptlp_pins[] = { @@ -292,9 +286,9 @@ static const struct intel_function sptlp_functions[] = { }; static const struct intel_community sptlp_communities[] = { - SPT_COMMUNITY(0, 0, 47), - SPT_COMMUNITY(1, 48, 119), - SPT_COMMUNITY(2, 120, 151), + SPT_LP_COMMUNITY(0, 0, 47), + SPT_LP_COMMUNITY(1, 48, 119), + SPT_LP_COMMUNITY(2, 120, 151), }; static const struct intel_pinctrl_soc_data sptlp_soc_data = { @@ -554,27 +548,27 @@ static const struct intel_function spth_functions[] = { }; static const struct intel_padgroup spth_community0_gpps[] = { - SPTH_GPP(0, 0, 23, 0), /* GPP_A */ - SPTH_GPP(1, 24, 47, 24), /* GPP_B */ + SPT_H_GPP(0, 0, 23, 0), /* GPP_A */ + SPT_H_GPP(1, 24, 47, 24), /* GPP_B */ }; static const struct intel_padgroup spth_community1_gpps[] = { - SPTH_GPP(0, 48, 71, 48), /* GPP_C */ - SPTH_GPP(1, 72, 95, 72), /* GPP_D */ - SPTH_GPP(2, 96, 108, 96), /* GPP_E */ - SPTH_GPP(3, 109, 132, 120), /* GPP_F */ - SPTH_GPP(4, 133, 156, 144), /* GPP_G */ - SPTH_GPP(5, 157, 180, 168), /* GPP_H */ + SPT_H_GPP(0, 48, 71, 48), /* GPP_C */ + SPT_H_GPP(1, 72, 95, 72), /* GPP_D */ + SPT_H_GPP(2, 96, 108, 96), /* GPP_E */ + SPT_H_GPP(3, 109, 132, 120), /* GPP_F */ + SPT_H_GPP(4, 133, 156, 144), /* GPP_G */ + SPT_H_GPP(5, 157, 180, 168), /* GPP_H */ }; static const struct intel_padgroup spth_community3_gpps[] = { - SPTH_GPP(0, 181, 191, 192), /* GPP_I */ + SPT_H_GPP(0, 181, 191, 192), /* GPP_I */ }; static const struct intel_community spth_communities[] = { - SPTH_COMMUNITY(0, 0, 47, spth_community0_gpps), - SPTH_COMMUNITY(1, 48, 180, spth_community1_gpps), - SPTH_COMMUNITY(2, 181, 191, spth_community3_gpps), + SPT_H_COMMUNITY(0, 0, 47, spth_community0_gpps), + SPT_H_COMMUNITY(1, 48, 180, spth_community1_gpps), + SPT_H_COMMUNITY(2, 181, 191, spth_community3_gpps), }; static const struct intel_pinctrl_soc_data spth_soc_data = { From 9b9448f39e83d8e6fdfed006c5db8c304a98c2cd Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Wed, 30 Sep 2020 12:48:40 -0500 Subject: [PATCH 73/78] pinctrl: single: fix pinctrl_spec.args_count bounds check The property #pinctrl-cells can either be 1 or 2: - if #pinctrl-cells = <1>, then pinctrl_spec.args_count = 2 - if #pinctrl-cells = <2>, then pinctrl_spec.args_count = 3 All other values of pinctrl_spec.args_count are incorrect. This fix checks the upper bound instead of just the lower bound. Fixes: a13395418888 ("pinctrl: single: parse #pinctrl-cells = 2") Reported-by: Trent Piepho Signed-off-by: Drew Fustini Acked-by: Tony Lindgren Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200930174839.1308344-1-drew@beagleboard.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index efe41abc5d47..5cbf0e55087c 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1014,7 +1014,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, if (res) return res; - if (pinctrl_spec.args_count < 2) { + if (pinctrl_spec.args_count < 2 || pinctrl_spec.args_count > 3) { dev_err(pcs->dev, "invalid args_count for spec: %i\n", pinctrl_spec.args_count); break; From f4a2b19c37caf40f3b8487ccb9032b974a84a3a7 Mon Sep 17 00:00:00 2001 From: Drew Fustini Date: Mon, 14 Sep 2020 01:03:07 +0200 Subject: [PATCH 74/78] pinctrl: single: fix debug output when #pinctrl-cells = 2 The debug output in pcs_parse_one_pinctrl_entry() needs to be updated to print the correct pinctrl register value when #pinctrl-cells is 2. Fixes: a13395418888 ("pinctrl: single: parse #pinctrl-cells = 2") Reported-by: Trent Piepho Signed-off-by: Drew Fustini Acked-by: Tony Lindgren Link: https://lore.kernel.org/linux-omap/3139716.CMS8C0sQ7x@zen.local/ Link: https://lore.kernel.org/r/20200913230306.2061645-1-drew@beagleboard.org Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-single.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c index 5cbf0e55087c..f3cd7e296712 100644 --- a/drivers/pinctrl/pinctrl-single.c +++ b/drivers/pinctrl/pinctrl-single.c @@ -1033,7 +1033,7 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, } dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", - pinctrl_spec.np, offset, pinctrl_spec.args[1]); + pinctrl_spec.np, offset, vals[found].val); pin = pcs_get_pin_by_offset(pcs, offset); if (pin < 0) { From db7515783b99f6ae8b21470cab9ee871956b57fb Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Thu, 1 Oct 2020 16:25:11 +0200 Subject: [PATCH 75/78] pinctrl: mediatek: Free eint data on failure The pinctrl driver can work without the EINT resource, but, if it is expected to have this resource but the mtk_build_eint() function fails after allocating their data (because can't get the resource or can't map the irq), the data is not freed and you end with a NULL pointer dereference. Fix this by freeing the data if mtk_build_eint() fails, so pinctrl still works and doesn't hang. This is noticeable after commit f97dbf48ca43 ("irqchip/mtk-sysirq: Convert to a platform driver") on MT8183 because, due this commit, the pinctrl driver fails to map the irq and spots the following bug: [ 1.947597] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000004 [ 1.956404] Mem abort info: [ 1.959203] ESR = 0x96000004 [ 1.962259] EC = 0x25: DABT (current EL), IL = 32 bits [ 1.967565] SET = 0, FnV = 0 [ 1.970613] EA = 0, S1PTW = 0 [ 1.973747] Data abort info: [ 1.976619] ISV = 0, ISS = 0x00000004 [ 1.980447] CM = 0, WnR = 0 [ 1.983410] [0000000000000004] user address but active_mm is swapper [ 1.989759] Internal error: Oops: 96000004 [#1] PREEMPT SMP [ 1.995322] Modules linked in: [ 1.998371] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc1+ #44 [ 2.004715] Hardware name: MediaTek krane sku176 board (DT) [ 2.010280] pstate: 60000005 (nZCv daif -PAN -UAO BTYPE=--) [ 2.015850] pc : mtk_eint_set_debounce+0x48/0x1b8 [ 2.020546] lr : mtk_eint_set_debounce+0x34/0x1b8 [ 2.025239] sp : ffff80001008baa0 [ 2.028544] x29: ffff80001008baa0 x28: ffff0000ff7ff790 [ 2.033847] x27: ffff0000f9ec34b0 x26: ffff0000f9ec3480 [ 2.039150] x25: ffff0000fa576410 x24: ffff0000fa502800 [ 2.044453] x23: 0000000000001388 x22: ffff0000fa635f80 [ 2.049755] x21: 0000000000000008 x20: 0000000000000000 [ 2.055058] x19: 0000000000000071 x18: 0000000000000001 [ 2.060360] x17: 0000000000000000 x16: 0000000000000000 [ 2.065662] x15: ffff0000facc8470 x14: ffffffffffffffff [ 2.070965] x13: 0000000000000001 x12: 00000000000000c0 [ 2.076267] x11: 0000000000000040 x10: 0000000000000070 [ 2.081569] x9 : ffffaec0063d24d8 x8 : ffff0000fa800270 [ 2.086872] x7 : 0000000000000000 x6 : 0000000000000011 [ 2.092174] x5 : ffff0000fa800248 x4 : ffff0000fa800270 [ 2.097476] x3 : ffff8000100c5000 x2 : 0000000000000000 [ 2.102778] x1 : 0000000000000000 x0 : 0000000000000000 [ 2.108081] Call trace: [ 2.110520] mtk_eint_set_debounce+0x48/0x1b8 [ 2.114870] mtk_gpio_set_config+0x5c/0x78 [ 2.118958] gpiod_set_config+0x5c/0x78 [ 2.122786] gpiod_set_debounce+0x18/0x28 [ 2.126789] gpio_keys_probe+0x50c/0x910 [ 2.130705] platform_drv_probe+0x54/0xa8 [ 2.134705] really_probe+0xe4/0x3b0 [ 2.138271] driver_probe_device+0x58/0xb8 [ 2.142358] device_driver_attach+0x74/0x80 [ 2.146532] __driver_attach+0x58/0xe0 [ 2.150274] bus_for_each_dev+0x70/0xc0 [ 2.154100] driver_attach+0x24/0x30 [ 2.157666] bus_add_driver+0x14c/0x1f0 [ 2.161493] driver_register+0x64/0x120 [ 2.165319] __platform_driver_register+0x48/0x58 [ 2.170017] gpio_keys_init+0x1c/0x28 [ 2.173672] do_one_initcall+0x54/0x1b4 [ 2.177499] kernel_init_freeable+0x1d0/0x238 [ 2.181848] kernel_init+0x14/0x118 [ 2.185328] ret_from_fork+0x10/0x34 [ 2.188899] Code: a9438ac1 12001266 f94006c3 121e766a (b9400421) [ 2.194991] ---[ end trace 168cf7b3324b6570 ]--- [ 2.199611] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b [ 2.207260] SMP: stopping secondary CPUs [ 2.211294] Kernel Offset: 0x2ebff4800000 from 0xffff800010000000 [ 2.217377] PHYS_OFFSET: 0xffffb50500000000 [ 2.221551] CPU features: 0x0240002,2188200c [ 2.225811] Memory Limit: none [ 2.228860] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b ]--- Fixes: 89132dd8ffd2 ("pinctrl: mediatek: extend eint build to pinctrl-mtk-common-v2.c") Signed-off-by: Enric Balletbo i Serra Acked-by: Sean Wang Link: https://lore.kernel.org/r/20201001142511.3560143-1-enric.balletbo@collabora.com [rebased on changed infrastructure] Signed-off-by: Linus Walleij --- .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index e8622c7e117a..ebc049792623 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -354,6 +354,7 @@ static const struct mtk_eint_xt mtk_eint_xt = { int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; + int ret; if (!IS_ENABLED(CONFIG_EINT_MTK)) return 0; @@ -366,15 +367,21 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return -ENOMEM; hw->eint->base = devm_platform_ioremap_resource_byname(pdev, "eint"); - if (IS_ERR(hw->eint->base)) - return PTR_ERR(hw->eint->base); + if (IS_ERR(hw->eint->base)) { + ret = PTR_ERR(hw->eint->base); + goto err_free_eint; + } hw->eint->irq = irq_of_parse_and_map(np, 0); - if (!hw->eint->irq) - return -EINVAL; + if (!hw->eint->irq) { + ret = -EINVAL; + goto err_free_eint; + } - if (!hw->soc->eint_hw) - return -ENODEV; + if (!hw->soc->eint_hw) { + ret = -ENODEV; + goto err_free_eint; + } hw->eint->dev = &pdev->dev; hw->eint->hw = hw->soc->eint_hw; @@ -382,6 +389,11 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) hw->eint->gpio_xlate = &mtk_eint_xt; return mtk_eint_do_init(hw->eint); + +err_free_eint: + devm_kfree(hw->dev, hw->eint); + hw->eint = NULL; + return ret; } EXPORT_SYMBOL_GPL(mtk_build_eint); From c6662da804c465f73d2faa61dd33f1e9376cac3d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 5 Oct 2020 14:50:49 +0200 Subject: [PATCH 76/78] pinctrl: visconti: PINCTRL_TMPV7700 should depend on ARCH_VISCONTI The Toshiba Visconti TMPV7700 series pin controller is only present on Visconti SoCs. Hence add a dependency on ARCH_VISCONTI, to prevent asking the user about this driver when configuring a kernel without Visconti platform support. Fixes: a68a7844264e4fb9 ("pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support") Signed-off-by: Geert Uytterhoeven Acked-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20201005125049.26926-1-geert+renesas@glider.be Signed-off-by: Linus Walleij --- drivers/pinctrl/visconti/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/visconti/Kconfig b/drivers/pinctrl/visconti/Kconfig index 198ec33189cc..42653fc60413 100644 --- a/drivers/pinctrl/visconti/Kconfig +++ b/drivers/pinctrl/visconti/Kconfig @@ -9,6 +9,6 @@ config PINCTRL_VISCONTI config PINCTRL_TMPV7700 bool "Toshiba Visconti TMPV7700 series pinctrl driver" depends on OF - depends on ARM64 || COMPILE_TEST + depends on ARCH_VISCONTI || COMPILE_TEST select PINCTRL_VISCONTI - default ARM64 && ARCH_VISCONTI + default ARCH_VISCONTI From 4e787e0405342e9c21558ead99d39d1cdef1b388 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= Date: Mon, 5 Oct 2020 21:09:39 +0200 Subject: [PATCH 77/78] dt-bindings: pinctrl: sunxi: Allow pinctrl with more interrupt banks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recently introduced Allwinner A100 pinctrl block has 7 interrupts. This trig a warning when running dtb_checks: sun50i-a100-allwinner-perf1.dt.yaml: pinctrl@300b000: interrupts: [...] is too long From schema: .../allwinner,sun4i-a10-pinctrl.yaml Fix this by allowing up to 7 interrupts. Signed-off-by: Clément Péron Acked-by: Rob Herring Link: https://lore.kernel.org/r/20201005190939.21016-1-peron.clem@gmail.com Signed-off-by: Linus Walleij --- .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml index 34a17d5c6135..5240487dfe50 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml @@ -61,7 +61,7 @@ properties: interrupts: minItems: 1 - maxItems: 5 + maxItems: 7 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. From 55596c5445566cf43b83238198fd038d21172d99 Mon Sep 17 00:00:00 2001 From: Shyam Sundar S K Date: Wed, 7 Oct 2020 16:42:20 +0530 Subject: [PATCH 78/78] pinctrl: amd: Add missing pins to the pin group list Some of the pins were not exposed in the initial driver or kept as reserved. Exposing all of them now. Signed-off-by: Shyam Sundar S K Link: https://lore.kernel.org/r/20201007111220.744348-1-Shyam-sundar.S-k@amd.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-amd.h | 69 ++++++++++++++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index d4a192df5fab..95e763424042 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -123,13 +123,31 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(18, "GPIO_18"), PINCTRL_PIN(19, "GPIO_19"), PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), PINCTRL_PIN(23, "GPIO_23"), PINCTRL_PIN(24, "GPIO_24"), PINCTRL_PIN(25, "GPIO_25"), PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), PINCTRL_PIN(39, "GPIO_39"), PINCTRL_PIN(40, "GPIO_40"), - PINCTRL_PIN(43, "GPIO_42"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), PINCTRL_PIN(46, "GPIO_46"), PINCTRL_PIN(47, "GPIO_47"), PINCTRL_PIN(48, "GPIO_48"), @@ -150,14 +168,23 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(64, "GPIO_64"), PINCTRL_PIN(65, "GPIO_65"), PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), PINCTRL_PIN(68, "GPIO_68"), PINCTRL_PIN(69, "GPIO_69"), PINCTRL_PIN(70, "GPIO_70"), PINCTRL_PIN(71, "GPIO_71"), PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), PINCTRL_PIN(74, "GPIO_74"), PINCTRL_PIN(75, "GPIO_75"), PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), PINCTRL_PIN(84, "GPIO_84"), PINCTRL_PIN(85, "GPIO_85"), PINCTRL_PIN(86, "GPIO_86"), @@ -168,6 +195,7 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(91, "GPIO_91"), PINCTRL_PIN(92, "GPIO_92"), PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), PINCTRL_PIN(95, "GPIO_95"), PINCTRL_PIN(96, "GPIO_96"), PINCTRL_PIN(97, "GPIO_97"), @@ -176,6 +204,16 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(100, "GPIO_100"), PINCTRL_PIN(101, "GPIO_101"), PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), PINCTRL_PIN(113, "GPIO_113"), PINCTRL_PIN(114, "GPIO_114"), PINCTRL_PIN(115, "GPIO_115"), @@ -186,12 +224,18 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(120, "GPIO_120"), PINCTRL_PIN(121, "GPIO_121"), PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), PINCTRL_PIN(129, "GPIO_129"), PINCTRL_PIN(130, "GPIO_130"), PINCTRL_PIN(131, "GPIO_131"), PINCTRL_PIN(132, "GPIO_132"), PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), PINCTRL_PIN(135, "GPIO_135"), PINCTRL_PIN(136, "GPIO_136"), PINCTRL_PIN(137, "GPIO_137"), @@ -206,6 +250,23 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(146, "GPIO_146"), PINCTRL_PIN(147, "GPIO_147"), PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), PINCTRL_PIN(166, "GPIO_166"), PINCTRL_PIN(167, "GPIO_167"), PINCTRL_PIN(168, "GPIO_168"), @@ -218,6 +279,12 @@ static const struct pinctrl_pin_desc kerncz_pins[] = { PINCTRL_PIN(175, "GPIO_175"), PINCTRL_PIN(176, "GPIO_176"), PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "GPIO_180"), + PINCTRL_PIN(181, "GPIO_181"), + PINCTRL_PIN(182, "GPIO_182"), + PINCTRL_PIN(183, "GPIO_183"), }; static const unsigned i2c0_pins[] = {145, 146};