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mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()

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Let the callers pass the pointer to the DMA-able buffer where
the value of the Configuration Register will be written. This way we
avoid the casts between int and u8, which can be confusing.

Callers stop compare the return value of spi_nor_read_cr() with negative,
spi_nor_read_cr() returns 0 on success and -errno otherwise.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
This commit is contained in:
Tudor Ambarus 2019-10-24 16:59:55 +03:00
parent 5ce1b49ccb
commit b662d398cc
No known key found for this signature in database
GPG Key ID: 4B554F47A58D14E9
1 changed files with 30 additions and 25 deletions
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55
drivers/mtd/spi-nor/spi-nor.c
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@ -487,12 +487,16 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
return ret;
}
/*
* Read configuration register, returning its value in the
* location. Return the configuration register value.
* Returns negative if error occurred.
/**
* spi_nor_read_cr() - Read the Configuration Register using the
* SPINOR_OP_RDCR (35h) command.
* @nor: pointer to 'struct spi_nor'
* @cr: pointer to a DMA-able buffer where the value of the
* Configuration Register will be written.
*
* Return: 0 on success, -errno otherwise.
*/
static int spi_nor_read_cr(struct spi_nor *nor)
static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)
{
int ret;
@ -501,20 +505,17 @@ static int spi_nor_read_cr(struct spi_nor *nor)
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDCR, 1),
SPI_MEM_OP_NO_ADDR,
SPI_MEM_OP_NO_DUMMY,
SPI_MEM_OP_DATA_IN(1, nor->bouncebuf, 1));
SPI_MEM_OP_DATA_IN(1, cr, 1));
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR,
nor->bouncebuf, 1);
ret = nor->controller_ops->read_reg(nor, SPINOR_OP_RDCR, cr, 1);
}
if (ret) {
if (ret)
dev_err(nor->dev, "error %d reading CR\n", ret);
return ret;
}
return nor->bouncebuf[0];
return ret;
}
/*
@ -1820,8 +1821,11 @@ static int spansion_quad_enable(struct spi_nor *nor)
return ret;
/* read back and check it */
ret = spi_nor_read_cr(nor);
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
ret = spi_nor_read_cr(nor, nor->bouncebuf);
if (ret)
return ret;
if (!(nor->bouncebuf[0] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@ -1879,16 +1883,16 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
int ret;
/* Check current Quad Enable bit value. */
ret = spi_nor_read_cr(nor);
if (ret < 0) {
ret = spi_nor_read_cr(nor, &sr_cr[1]);
if (ret) {
dev_err(dev, "error while reading configuration register\n");
return ret;
}
if (ret & CR_QUAD_EN_SPAN)
if (sr_cr[1] & CR_QUAD_EN_SPAN)
return 0;
sr_cr[1] = ret | CR_QUAD_EN_SPAN;
sr_cr[1] |= CR_QUAD_EN_SPAN;
/* Keep the current value of the Status Register. */
ret = spi_nor_read_sr(nor, sr_cr);
@ -1902,8 +1906,11 @@ static int spansion_read_cr_quad_enable(struct spi_nor *nor)
return ret;
/* Read back and check it. */
ret = spi_nor_read_cr(nor);
if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
ret = spi_nor_read_cr(nor, &sr_cr[1]);
if (ret)
return ret;
if (!(sr_cr[1] & CR_QUAD_EN_SPAN)) {
dev_err(nor->dev, "Spansion Quad bit not set\n");
return -EINVAL;
}
@ -2019,8 +2026,8 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
u8 *sr_cr = nor->bouncebuf;
/* Check current Quad Enable bit value. */
ret = spi_nor_read_cr(nor);
if (ret < 0) {
ret = spi_nor_read_cr(nor, &sr_cr[1]);
if (ret) {
dev_err(nor->dev,
"error while reading configuration register\n");
return ret;
@ -2030,9 +2037,7 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor)
* When the configuration register Quad Enable bit is one, only the
* Write Status (01h) command with two data bytes may be used.
*/
if (ret & CR_QUAD_EN_SPAN) {
sr_cr[1] = ret;
if (sr_cr[1] & CR_QUAD_EN_SPAN) {
ret = spi_nor_read_sr(nor, sr_cr);
if (ret) {
dev_err(nor->dev,