forked from luck/tmp_suning_uos_patched
IOMMU Fixes for Linux v4.2-rc3
The fixes include:
* A couple of fixes for the new ARM-SMMUv3 driver to fix issues found
on the first real implementation of that hardware.
* A patch for the Intel VT-d driver to fix a domain-id leak.
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Merge tag 'iommu-fixes-v4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"The fixes include:
- a couple of fixes for the new ARM-SMMUv3 driver to fix issues found
on the first real implementation of that hardware.
- a patch for the Intel VT-d driver to fix a domain-id leak"
* tag 'iommu-fixes-v4.2-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/vt-d: Fix VM domain ID leak
iommu/arm-smmu: Skip the execution of CMD_PREFETCH_CONFIG
iommu/arm-smmu: Enlarge STRTAB_L1_SZ_SHIFT to support larger sidsize
iommu/arm-smmu: Fix the values of ARM64_TCR_{I,O}RGN0_SHIFT
iommu/arm-smmu: Fix LOG2SIZE setting for 2-level stream tables
iommu/arm-smmu: Fix the index calculation of strtab
This commit is contained in:
Linus Torvalds
commit
b681268cb2
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@ -35,3 +35,6 @@ the PCIe specification.
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NOTE: this only applies to the SMMU itself, not
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masters connected upstream of the SMMU.
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- hisilicon,broken-prefetch-cmd
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: Avoid sending CMD_PREFETCH_* commands to the SMMU.
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@ -199,9 +199,10 @@
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* Stream table.
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*
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* Linear: Enough to cover 1 << IDR1.SIDSIZE entries
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* 2lvl: 8k L1 entries, 256 lazy entries per table (each table covers a PCI bus)
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* 2lvl: 128k L1 entries,
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* 256 lazy entries per table (each table covers a PCI bus)
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*/
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#define STRTAB_L1_SZ_SHIFT 16
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#define STRTAB_L1_SZ_SHIFT 20
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#define STRTAB_SPLIT 8
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#define STRTAB_L1_DESC_DWORDS 1
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@ -269,10 +270,10 @@
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#define ARM64_TCR_TG0_SHIFT 14
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#define ARM64_TCR_TG0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_IRGN0_SHIFT 8
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#define ARM64_TCR_IRGN0_SHIFT 24
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#define ARM64_TCR_IRGN0_SHIFT 8
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#define ARM64_TCR_IRGN0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_ORGN0_SHIFT 10
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#define ARM64_TCR_ORGN0_SHIFT 26
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#define ARM64_TCR_ORGN0_SHIFT 10
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#define ARM64_TCR_ORGN0_MASK 0x3UL
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#define CTXDESC_CD_0_TCR_SH0_SHIFT 12
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#define ARM64_TCR_SH0_SHIFT 12
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@ -542,6 +543,9 @@ struct arm_smmu_device {
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#define ARM_SMMU_FEAT_HYP (1 << 12)
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u32 features;
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#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
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u32 options;
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struct arm_smmu_cmdq cmdq;
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struct arm_smmu_evtq evtq;
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struct arm_smmu_priq priq;
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@ -602,11 +606,35 @@ struct arm_smmu_domain {
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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
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static LIST_HEAD(arm_smmu_devices);
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struct arm_smmu_option_prop {
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u32 opt;
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const char *prop;
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};
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static struct arm_smmu_option_prop arm_smmu_options[] = {
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{ ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
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{ 0, NULL},
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};
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static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
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{
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return container_of(dom, struct arm_smmu_domain, domain);
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}
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static void parse_driver_options(struct arm_smmu_device *smmu)
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{
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int i = 0;
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do {
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if (of_property_read_bool(smmu->dev->of_node,
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arm_smmu_options[i].prop)) {
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smmu->options |= arm_smmu_options[i].opt;
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dev_notice(smmu->dev, "option %s\n",
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arm_smmu_options[i].prop);
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}
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} while (arm_smmu_options[++i].opt);
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}
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/* Low-level queue manipulation functions */
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static bool queue_full(struct arm_smmu_queue *q)
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{
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@ -1036,7 +1064,8 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_device *smmu, u32 sid,
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arm_smmu_sync_ste_for_sid(smmu, sid);
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/* It's likely that we'll want to use the new STE soon */
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arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
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if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH))
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arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd);
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}
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static void arm_smmu_init_bypass_stes(u64 *strtab, unsigned int nent)
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@ -1064,7 +1093,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
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return 0;
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size = 1 << (STRTAB_SPLIT + ilog2(STRTAB_STE_DWORDS) + 3);
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strtab = &cfg->strtab[sid >> STRTAB_SPLIT << STRTAB_L1_DESC_DWORDS];
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strtab = &cfg->strtab[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS];
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desc->span = STRTAB_SPLIT + 1;
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desc->l2ptr = dma_zalloc_coherent(smmu->dev, size, &desc->l2ptr_dma,
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@ -2020,21 +2049,23 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
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{
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void *strtab;
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u64 reg;
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u32 size;
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u32 size, l1size;
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int ret;
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struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg;
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/* Calculate the L1 size, capped to the SIDSIZE */
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size = STRTAB_L1_SZ_SHIFT - (ilog2(STRTAB_L1_DESC_DWORDS) + 3);
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size = min(size, smmu->sid_bits - STRTAB_SPLIT);
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if (size + STRTAB_SPLIT < smmu->sid_bits)
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cfg->num_l1_ents = 1 << size;
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size += STRTAB_SPLIT;
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if (size < smmu->sid_bits)
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dev_warn(smmu->dev,
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"2-level strtab only covers %u/%u bits of SID\n",
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size + STRTAB_SPLIT, smmu->sid_bits);
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size, smmu->sid_bits);
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cfg->num_l1_ents = 1 << size;
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size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
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strtab = dma_zalloc_coherent(smmu->dev, size, &cfg->strtab_dma,
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l1size = cfg->num_l1_ents * (STRTAB_L1_DESC_DWORDS << 3);
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strtab = dma_zalloc_coherent(smmu->dev, l1size, &cfg->strtab_dma,
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GFP_KERNEL);
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if (!strtab) {
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dev_err(smmu->dev,
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@ -2055,8 +2086,7 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
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ret = arm_smmu_init_l1_strtab(smmu);
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if (ret)
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dma_free_coherent(smmu->dev,
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cfg->num_l1_ents *
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(STRTAB_L1_DESC_DWORDS << 3),
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l1size,
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strtab,
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cfg->strtab_dma);
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return ret;
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@ -2573,6 +2603,8 @@ static int arm_smmu_device_dt_probe(struct platform_device *pdev)
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if (irq > 0)
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smmu->gerr_irq = irq;
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parse_driver_options(smmu);
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/* Probe the h/w */
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ret = arm_smmu_device_probe(smmu);
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if (ret)
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@ -1830,8 +1830,9 @@ static int domain_init(struct dmar_domain *domain, int guest_width)
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static void domain_exit(struct dmar_domain *domain)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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struct page *freelist = NULL;
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int i;
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/* Domain 0 is reserved, so dont process it */
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if (!domain)
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@ -1851,8 +1852,10 @@ static void domain_exit(struct dmar_domain *domain)
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/* clear attached or cached domains */
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rcu_read_lock();
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for_each_set_bit(i, domain->iommu_bmp, g_num_of_iommus)
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iommu_detach_domain(domain, g_iommus[i]);
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for_each_active_iommu(iommu, drhd)
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if (domain_type_is_vm(domain) ||
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test_bit(iommu->seq_id, domain->iommu_bmp))
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iommu_detach_domain(domain, iommu);
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rcu_read_unlock();
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dma_free_pagelist(freelist);
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