AcoSail/kernel_optimize_test
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Code Pull Requests Activity

Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2600' into clk-next

Browse Source 
* clk-unisoc:
  clk: sprd: add mipi_csi_xx gate clocks
  clk: sprd: add dt-bindings include for mipi_csi_xx clocks
  dt-bindings: clk: sprd: add mipi_csi_xx clocks for SC9863A
  clk: sprd: check its parent status before reading gate clock
  clk: sprd: return correct type of value for _sprd_pll_recalc_rate
  clk: sprd: mark the local clock symbols static

* clk-trivial:
  clk: versatile: remove redundant assignment to pointer clk
  clk: clk-xgene: Fix a typo in Kconfig
  clk: Remove unused inline function clk_debug_reparent

* clk-bcm:
  clk: bcm2835: Constify struct debugfs_reg32
  clk: bcm2835: Remove casting to bcm2835_clk_register
  clk: bcm2835: Fix return type of bcm2835_register_gate

* clk-st:
  clk: clk-flexgen: fix clock-critical handling

* clk-ast2600:
  clk: ast2600: Fix AHB clock divider for A1
This commit is contained in:
Stephen Boyd 2020-06-01 13:00:21 -07:00
commit b6f3162d0e
12 changed files with 142 additions and 66 deletions
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1
Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
View File

@ -28,6 +28,7 @@ properties:
- sprd,sc9863a-rpll
- sprd,sc9863a-dpll
- sprd,sc9863a-mm-gate
- sprd,sc9863a-mm-clk
- sprd,sc9863a-apapb-gate
clocks:

2
drivers/clk/Kconfig
View File

@ -267,7 +267,7 @@ config COMMON_CLK_XGENE
default ARCH_XGENE
depends on ARM64 || COMPILE_TEST
---help---
Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
Support for the APM X-Gene SoC reference, PLL, and device clocks.
config COMMON_CLK_LOCHNAGAR
tristate "Cirrus Logic Lochnagar clock driver"

80
drivers/clk/bcm/clk-bcm2835.c
View File

@ -396,8 +396,8 @@ static unsigned long bcm2835_measure_tcnt_mux(struct bcm2835_cprman *cprman,
}
static void bcm2835_debugfs_regset(struct bcm2835_cprman *cprman, u32 base,
struct debugfs_reg32 *regs, size_t nregs,
struct dentry *dentry)
const struct debugfs_reg32 *regs,
size_t nregs, struct dentry *dentry)
{
struct debugfs_regset32 *regset;
@ -1240,7 +1240,7 @@ static u8 bcm2835_clock_get_parent(struct clk_hw *hw)
return (src & CM_SRC_MASK) >> CM_SRC_SHIFT;
}
static struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
static const struct debugfs_reg32 bcm2835_debugfs_clock_reg32[] = {
{
.name = "ctl",
.offset = 0,
@ -1296,8 +1296,9 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = {
};
static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
const struct bcm2835_pll_data *data)
const void *data)
{
const struct bcm2835_pll_data *pll_data = data;
struct bcm2835_pll *pll;
struct clk_init_data init;
int ret;
@ -1307,7 +1308,7 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
/* All of the PLLs derive from the external oscillator. */
init.parent_names = &cprman->real_parent_names[0];
init.num_parents = 1;
init.name = data->name;
init.name = pll_data->name;
init.ops = &bcm2835_pll_clk_ops;
init.flags = CLK_IGNORE_UNUSED;
@ -1316,7 +1317,7 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
return NULL;
pll->cprman = cprman;
pll->data = data;
pll->data = pll_data;
pll->hw.init = &init;
ret = devm_clk_hw_register(cprman->dev, &pll->hw);
@ -1327,35 +1328,36 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman,
static struct clk_hw *
bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
const struct bcm2835_pll_divider_data *data)
const void *data)
{
const struct bcm2835_pll_divider_data *divider_data = data;
struct bcm2835_pll_divider *divider;
struct clk_init_data init;
const char *divider_name;
int ret;
if (data->fixed_divider != 1) {
if (divider_data->fixed_divider != 1) {
divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
"%s_prediv", data->name);
"%s_prediv", divider_data->name);
if (!divider_name)
return NULL;
} else {
divider_name = data->name;
divider_name = divider_data->name;
}
memset(&init, 0, sizeof(init));
init.parent_names = &data->source_pll;
init.parent_names = &divider_data->source_pll;
init.num_parents = 1;
init.name = divider_name;
init.ops = &bcm2835_pll_divider_clk_ops;
init.flags = data->flags | CLK_IGNORE_UNUSED;
init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
if (!divider)
return NULL;
divider->div.reg = cprman->regs + data->a2w_reg;
divider->div.reg = cprman->regs + divider_data->a2w_reg;
divider->div.shift = A2W_PLL_DIV_SHIFT;
divider->div.width = A2W_PLL_DIV_BITS;
divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
@ -1364,7 +1366,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
divider->div.table = NULL;
divider->cprman = cprman;
divider->data = data;
divider->data = divider_data;
ret = devm_clk_hw_register(cprman->dev, &divider->div.hw);
if (ret)
@ -1374,20 +1376,22 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
* PLLH's channels have a fixed divide by 10 afterwards, which
* is what our consumers are actually using.
*/
if (data->fixed_divider != 1) {
return clk_hw_register_fixed_factor(cprman->dev, data->name,
if (divider_data->fixed_divider != 1) {
return clk_hw_register_fixed_factor(cprman->dev,
divider_data->name,
divider_name,
CLK_SET_RATE_PARENT,
1,
data->fixed_divider);
divider_data->fixed_divider);
}
return &divider->div.hw;
}
static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
const struct bcm2835_clock_data *data)
const void *data)
{
const struct bcm2835_clock_data *clock_data = data;
struct bcm2835_clock *clock;
struct clk_init_data init;
const char *parents[1 << CM_SRC_BITS];
@ -1398,8 +1402,8 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
* Replace our strings referencing parent clocks with the
* actual clock-output-name of the parent.
*/
for (i = 0; i < data->num_mux_parents; i++) {
parents[i] = data->parents[i];
for (i = 0; i < clock_data->num_mux_parents; i++) {
parents[i] = clock_data->parents[i];
ret = match_string(cprman_parent_names,
ARRAY_SIZE(cprman_parent_names),
@ -1410,18 +1414,18 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
memset(&init, 0, sizeof(init));
init.parent_names = parents;
init.num_parents = data->num_mux_parents;
init.name = data->name;
init.flags = data->flags | CLK_IGNORE_UNUSED;
init.num_parents = clock_data->num_mux_parents;
init.name = clock_data->name;
init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
/*
* Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate
* rate changes on at least of the parents.
*/
if (data->set_rate_parent)
if (clock_data->set_rate_parent)
init.flags |= CLK_SET_RATE_PARENT;
if (data->is_vpu_clock) {
if (clock_data->is_vpu_clock) {
init.ops = &bcm2835_vpu_clock_clk_ops;
} else {
init.ops = &bcm2835_clock_clk_ops;
@ -1430,7 +1434,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
/* If the clock wasn't actually enabled at boot, it's not
* critical.
*/
if (!(cprman_read(cprman, data->ctl_reg) & CM_ENABLE))
if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
init.flags &= ~CLK_IS_CRITICAL;
}
@ -1439,7 +1443,7 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
return NULL;
clock->cprman = cprman;
clock->data = data;
clock->data = clock_data;
clock->hw.init = &init;
ret = devm_clk_hw_register(cprman->dev, &clock->hw);
@ -1448,25 +1452,27 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman,
return &clock->hw;
}
static struct clk *bcm2835_register_gate(struct bcm2835_cprman *cprman,
const struct bcm2835_gate_data *data)
static struct clk_hw *bcm2835_register_gate(struct bcm2835_cprman *cprman,
const void *data)
{
return clk_register_gate(cprman->dev, data->name, data->parent,
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
cprman->regs + data->ctl_reg,
CM_GATE_BIT, 0, &cprman->regs_lock);
const struct bcm2835_gate_data *gate_data = data;
return clk_hw_register_gate(cprman->dev, gate_data->name,
gate_data->parent,
CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
cprman->regs + gate_data->ctl_reg,
CM_GATE_BIT, 0, &cprman->regs_lock);
}
typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman,
const void *data);
struct bcm2835_clk_desc {
bcm2835_clk_register clk_register;
struct clk_hw *(*clk_register)(struct bcm2835_cprman *cprman,
const void *data);
unsigned int supported;
const void *data;
};
/* assignment helper macros for different clock types */
#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \
#define _REGISTER(f, s, ...) { .clk_register = f, \
.supported = s, \
.data = __VA_ARGS__ }
#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \

31
drivers/clk/clk-ast2600.c
View File

@ -642,14 +642,22 @@ static const u32 ast2600_a0_axi_ahb_div_table[] = {
2, 2, 3, 5,
};
static const u32 ast2600_a1_axi_ahb_div_table[] = {
4, 6, 2, 4,
static const u32 ast2600_a1_axi_ahb_div0_tbl[] = {
3, 2, 3, 4,
};
static const u32 ast2600_a1_axi_ahb_div1_tbl[] = {
3, 4, 6, 8,
};
static const u32 ast2600_a1_axi_ahb200_tbl[] = {
3, 4, 3, 4, 2, 2, 2, 2,
};
static void __init aspeed_g6_cc(struct regmap *map)
{
struct clk_hw *hw;
u32 val, div, chip_id, axi_div, ahb_div;
u32 val, div, divbits, chip_id, axi_div, ahb_div;
clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, 25000000);
@ -679,11 +687,22 @@ static void __init aspeed_g6_cc(struct regmap *map)
else
axi_div = 2;
divbits = (val >> 11) & 0x3;
regmap_read(map, ASPEED_G6_SILICON_REV, &chip_id);
if (chip_id & BIT(16))
ahb_div = ast2600_a1_axi_ahb_div_table[(val >> 11) & 0x3];
else
if (chip_id & BIT(16)) {
if (!divbits) {
ahb_div = ast2600_a1_axi_ahb200_tbl[(val >> 8) & 0x3];
if (val & BIT(16))
ahb_div *= 2;
} else {
if (val & BIT(16))
ahb_div = ast2600_a1_axi_ahb_div1_tbl[divbits];
else
ahb_div = ast2600_a1_axi_ahb_div0_tbl[divbits];
}
} else {
ahb_div = ast2600_a0_axi_ahb_div_table[(val >> 11) & 0x3];
}
hw = clk_hw_register_fixed_factor(NULL, "ahb", "hpll", 0, 1, axi_div * ahb_div);
aspeed_g6_clk_data->hws[ASPEED_CLK_AHB] = hw;

4
drivers/clk/clk.c
View File

@ -3295,10 +3295,6 @@ static int __init clk_debug_init(void)
late_initcall(clk_debug_init);
#else
static inline void clk_debug_register(struct clk_core *core) { }
static inline void clk_debug_reparent(struct clk_core *core,
struct clk_core *new_parent)
{
}
static inline void clk_debug_unregister(struct clk_core *core)
{
}

7
drivers/clk/sprd/gate.c
View File

@ -94,8 +94,15 @@ static int sprd_gate_is_enabled(struct clk_hw *hw)
{
struct sprd_gate *sg = hw_to_sprd_gate(hw);
struct sprd_clk_common *common = &sg->common;
struct clk_hw *parent;
unsigned int reg;
if (sg->flags & SPRD_GATE_NON_AON) {
parent = clk_hw_get_parent(hw);
if (!parent || !clk_hw_is_enabled(parent))
return 0;
}
regmap_read(common->regmap, common->reg, &reg);
if (sg->flags & CLK_GATE_SET_TO_DISABLE)

9
drivers/clk/sprd/gate.h
View File

@ -19,6 +19,15 @@ struct sprd_gate {
struct sprd_clk_common common;
};
/*
* sprd_gate->flags is used for:
* CLK_GATE_SET_TO_DISABLE BIT(0)
* CLK_GATE_HIWORD_MASK BIT(1)
* CLK_GATE_BIG_ENDIAN BIT(2)
* so we define new flags from BIT(3)
*/
#define SPRD_GATE_NON_AON BIT(3) /* not alway powered on, check before read */
#define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
_sc_offset, _enable_mask, _flags, \
_gate_flags, _udelay, _ops, _fn) \

2
drivers/clk/sprd/pll.c
View File

@ -106,7 +106,7 @@ static unsigned long _sprd_pll_recalc_rate(const struct sprd_pll *pll,
cfg = kcalloc(regs_num, sizeof(*cfg), GFP_KERNEL);
if (!cfg)
return -ENOMEM;
return parent_rate;
for (i = 0; i < regs_num; i++)
cfg[i] = sprd_pll_read(pll, i);

64
drivers/clk/sprd/sc9863a-clk.c
View File

@ -23,22 +23,22 @@
#include "pll.h"
/* mpll*_gate clocks control cpu cores, they were enabled by default */
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
0x1000, BIT(0), 0, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m", 0x1e8,
0x1000, BIT(0), 0, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll0_gate, "mpll0-gate", "ext-26m", 0x94,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll0_gate, "dpll0-gate", "ext-26m", 0x98,
0x1000, BIT(0), 0, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(lpll_gate, "lpll-gate", "ext-26m", 0x9c,
0x1000, BIT(0), 0, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(gpll_gate, "gpll-gate", "ext-26m", 0xa8,
0x1000, BIT(0), 0, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(dpll1_gate, "dpll1-gate", "ext-26m", 0x1dc,
0x1000, BIT(0), 0, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll1_gate, "mpll1-gate", "ext-26m", 0x1e0,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(mpll2_gate, "mpll2-gate", "ext-26m", 0x1e4,
0x1000, BIT(0), CLK_IGNORE_UNUSED, 0, 240);
static SPRD_PLL_SC_GATE_CLK_FW_NAME(isppll_gate, "isppll-gate", "ext-26m",
0x1e8, 0x1000, BIT(0), 0, 0, 240);
static struct sprd_clk_common *sc9863a_pmu_gate_clks[] = {
/* address base is 0x402b0000 */
@ -1615,6 +1615,36 @@ static const struct sprd_clk_desc sc9863a_mm_gate_desc = {
.hw_clks = &sc9863a_mm_gate_hws,
};
/* camera sensor clocks */
static SPRD_GATE_CLK_HW(mipi_csi_clk, "mipi-csi-clk", &mahb_ckg_eb.common.hw,
0x20, BIT(16), 0, SPRD_GATE_NON_AON);
static SPRD_GATE_CLK_HW(mipi_csi_s_clk, "mipi-csi-s-clk", &mahb_ckg_eb.common.hw,
0x24, BIT(16), 0, SPRD_GATE_NON_AON);
static SPRD_GATE_CLK_HW(mipi_csi_m_clk, "mipi-csi-m-clk", &mahb_ckg_eb.common.hw,
0x28, BIT(16), 0, SPRD_GATE_NON_AON);
static struct sprd_clk_common *sc9863a_mm_clk_clks[] = {
/* address base is 0x60900000 */
&mipi_csi_clk.common,
&mipi_csi_s_clk.common,
&mipi_csi_m_clk.common,
};
static struct clk_hw_onecell_data sc9863a_mm_clk_hws = {
.hws = {
[CLK_MIPI_CSI] = &mipi_csi_clk.common.hw,
[CLK_MIPI_CSI_S] = &mipi_csi_s_clk.common.hw,
[CLK_MIPI_CSI_M] = &mipi_csi_m_clk.common.hw,
},
.num = CLK_MM_CLK_NUM,
};
static const struct sprd_clk_desc sc9863a_mm_clk_desc = {
.clk_clks = sc9863a_mm_clk_clks,
.num_clk_clks = ARRAY_SIZE(sc9863a_mm_clk_clks),
.hw_clks = &sc9863a_mm_clk_hws,
};
static SPRD_SC_GATE_CLK_FW_NAME(sim0_eb, "sim0-eb", "ext-26m", 0x0,
0x1000, BIT(0), 0, 0);
static SPRD_SC_GATE_CLK_FW_NAME(iis0_eb, "iis0-eb", "ext-26m", 0x0,
@ -1737,6 +1767,8 @@ static const struct of_device_id sprd_sc9863a_clk_ids[] = {
.data = &sc9863a_aonapb_gate_desc },
{ .compatible = "sprd,sc9863a-mm-gate", /* 0x60800000 */
.data = &sc9863a_mm_gate_desc },
{ .compatible = "sprd,sc9863a-mm-clk", /* 0x60900000 */
.data = &sc9863a_mm_clk_desc },
{ .compatible = "sprd,sc9863a-apapb-gate", /* 0x71300000 */
.data = &sc9863a_apapb_gate_desc },
{ }

1
drivers/clk/st/clk-flexgen.c
View File

@ -375,6 +375,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
break;
}
flex_flags &= ~CLK_IS_CRITICAL;
of_clk_detect_critical(np, i, &flex_flags);
/*

2
drivers/clk/versatile/clk-versatile.c
View File

@ -56,7 +56,7 @@ static const struct clk_icst_desc versatile_auxosc_desc __initconst = {
static void __init cm_osc_setup(struct device_node *np,
const struct clk_icst_desc *desc)
{
struct clk *clk = ERR_PTR(-EINVAL);
struct clk *clk;
const char *clk_name = np->name;
const char *parent_name;

5
include/dt-bindings/clock/sprd,sc9863a-clk.h
View File

@ -308,6 +308,11 @@
#define CLK_MCPHY_CFG_EB 14
#define CLK_MM_GATE_NUM (CLK_MCPHY_CFG_EB + 1)
#define CLK_MIPI_CSI 0
#define CLK_MIPI_CSI_S 1
#define CLK_MIPI_CSI_M 2
#define CLK_MM_CLK_NUM (CLK_MIPI_CSI_M + 1)
#define CLK_SIM0_EB 0
#define CLK_IIS0_EB 1
#define CLK_IIS1_EB 2