forked from luck/tmp_suning_uos_patched
net: dsa: mv88e6xxx: prefix Port Default VLAN macros
For implicit namespacing and clarity, prefix the common Port Default VLAN Register macros with MV88E6XXX_PORT_DEFAULT_VLAN. Document the register and prefer ordered hex masks values for all Marvell 16-bit registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1950,7 +1950,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
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/* Default VLAN ID and priority: don't set a default VLAN
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* ID, and set the default packet priority to zero.
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*/
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return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
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return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
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}
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static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
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@ -706,11 +706,12 @@ int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid)
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
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®);
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if (err)
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return err;
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*pvid = reg & PORT_DEFAULT_VLAN_MASK;
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*pvid = reg & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
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return 0;
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}
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@ -720,14 +721,16 @@ int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid)
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u16 reg;
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int err;
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err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
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err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
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®);
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if (err)
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return err;
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reg &= ~PORT_DEFAULT_VLAN_MASK;
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reg |= pvid & PORT_DEFAULT_VLAN_MASK;
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reg &= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
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reg |= pvid & MV88E6XXX_PORT_DEFAULT_VLAN_MASK;
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err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
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err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN,
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reg);
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if (err)
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return err;
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@ -150,8 +150,10 @@
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#define MV88E6XXX_PORT_BASE_VLAN 0x06
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#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000
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#define PORT_DEFAULT_VLAN 0x07
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#define PORT_DEFAULT_VLAN_MASK 0xfff
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/* Offset 0x07: Default Port VLAN ID & Priority */
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#define MV88E6XXX_PORT_DEFAULT_VLAN 0x07
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#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff
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#define PORT_CONTROL_2 0x08
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#define PORT_CONTROL_2_IGNORE_FCS BIT(15)
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#define PORT_CONTROL_2_VTU_PRI_OVERRIDE BIT(14)
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