forked from luck/tmp_suning_uos_patched
[POWERPC] Add mpc8641hpcn PCI/PCI-Express platform files.
Signed-off-by: Xianghua Xiao <x.xiao@freescale.com> Signed-off-by: Wei Zhang <Wei.Zhang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Jon Loeliger
Paul Mackerras
parent
4ca4b6274c
commit
b809b3e86f
173
arch/powerpc/platforms/86xx/mpc86xx_pcie.c
Normal file
173
arch/powerpc/platforms/86xx/mpc86xx_pcie.c
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@ -0,0 +1,173 @@
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/*
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* Support for indirect PCI bridges.
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*
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* Copyright (C) 1998 Gabriel Paubert.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* "Temporary" MPC8548 Errata file -
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* The standard indirect_pci code should work with future silicon versions.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include "mpc86xx.h"
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#define PCI_CFG_OUT out_be32
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/* ERRATA PCI-Ex 14 PCIE Controller timeout */
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#define PCIE_FIX out_be32(hose->cfg_addr+0x4, 0x0400ffff)
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static int
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indirect_read_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u32 temp;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Possible artifact of CDCpp50937 needs further investigation */
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if (devfn != 0x0 && bus->number == 0xff)
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return PCIBIOS_DEVICE_NOT_FOUND;
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PCIE_FIX;
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if (bus->number == 0xff) {
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | ((offset & 0xf00) << 16) |
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((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) )));
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} else {
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000001 | ((offset & 0xf00) << 16) |
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((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) )));
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
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cfg_data = hose->cfg_data;
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PCIE_FIX;
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temp = in_le32(cfg_data);
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switch (len) {
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case 1:
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*val = (temp >> (((offset & 3))*8)) & 0xff;
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break;
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case 2:
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*val = (temp >> (((offset & 3))*8)) & 0xffff;
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break;
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default:
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*val = temp;
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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indirect_write_config_pcie(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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struct pci_controller *hose = bus->sysdata;
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volatile void __iomem *cfg_data;
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u32 temp;
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if (ppc_md.pci_exclude_device)
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if (ppc_md.pci_exclude_device(bus->number, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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/* Possible artifact of CDCpp50937 needs further investigation */
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if (devfn != 0x0 && bus->number == 0xff)
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return PCIBIOS_DEVICE_NOT_FOUND;
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PCIE_FIX;
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if (bus->number == 0xff) {
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000000 | ((offset & 0xf00) << 16) |
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((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) )));
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} else {
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PCI_CFG_OUT(hose->cfg_addr,
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(0x80000001 | ((offset & 0xf00) << 16) |
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((bus->number - hose->bus_offset) << 16)
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| (devfn << 8) | ((offset & 0xfc) )));
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}
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/*
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* Note: the caller has already checked that offset is
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* suitably aligned and that len is 1, 2 or 4.
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*/
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/* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
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cfg_data = hose->cfg_data;
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switch (len) {
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case 1:
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PCIE_FIX;
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temp = in_le32(cfg_data);
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temp = (temp & ~(0xff << ((offset & 3) * 8))) |
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(val << ((offset & 3) * 8));
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PCIE_FIX;
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out_le32(cfg_data, temp);
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break;
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case 2:
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PCIE_FIX;
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temp = in_le32(cfg_data);
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temp = (temp & ~(0xffff << ((offset & 3) * 8)));
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temp |= (val << ((offset & 3) * 8)) ;
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PCIE_FIX;
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out_le32(cfg_data, temp);
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break;
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default:
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PCIE_FIX;
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out_le32(cfg_data, val);
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break;
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}
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PCIE_FIX;
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops indirect_pcie_ops = {
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indirect_read_config_pcie,
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indirect_write_config_pcie
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};
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void __init
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setup_indirect_pcie_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
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void __iomem * cfg_data)
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{
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hose->cfg_addr = cfg_addr;
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hose->cfg_data = cfg_data;
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hose->ops = &indirect_pcie_ops;
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}
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void __init
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setup_indirect_pcie(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
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{
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unsigned long base = cfg_addr & PAGE_MASK;
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void __iomem *mbase, *addr, *data;
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mbase = ioremap(base, PAGE_SIZE);
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addr = mbase + (cfg_addr & ~PAGE_MASK);
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if ((cfg_data & PAGE_MASK) != base)
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mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
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data = mbase + (cfg_data & ~PAGE_MASK);
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setup_indirect_pcie_nomap(hose, addr, data);
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}
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325
arch/powerpc/platforms/86xx/pci.c
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325
arch/powerpc/platforms/86xx/pci.c
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@ -0,0 +1,325 @@
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/*
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* MPC86XX pci setup code
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*
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* Recode: ZHANG WEI <wei.zhang@freescale.com>
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* Initial author: Xianghua Xiao <x.xiao@freescale.com>
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/serial.h>
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#include <asm/system.h>
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#include <asm/atomic.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/immap_86xx.h>
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#include <asm/pci-bridge.h>
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#include <sysdev/fsl_soc.h>
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#include "mpc86xx.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
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#else
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#define DBG(fmt, args...)
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#endif
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struct pcie_outbound_window_regs {
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uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
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uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
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uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
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char res1[4];
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uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
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char res2[12];
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};
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struct pcie_inbound_window_regs {
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uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
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char res1[4];
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uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
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uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
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uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
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char res2[12];
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};
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static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
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{
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volatile struct ccsr_pex *pcie;
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volatile struct pcie_outbound_window_regs *pcieow;
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volatile struct pcie_inbound_window_regs *pcieiw;
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int i = 0;
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DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start,
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rsrc->end - rsrc->start + 1);
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pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
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/* Disable all windows (except pexowar0 since its ignored) */
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pcie->pexowar1 = 0;
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pcie->pexowar2 = 0;
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pcie->pexowar3 = 0;
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pcie->pexowar4 = 0;
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pcie->pexiwar1 = 0;
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pcie->pexiwar2 = 0;
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pcie->pexiwar3 = 0;
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pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1;
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pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1;
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/* Setup outbound MEM window */
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for(i = 0; i < 3; i++)
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if (hose->mem_resources[i].flags & IORESOURCE_MEM){
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DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n",
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hose->mem_resources[i].start,
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hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1);
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pcieow->pexotar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->mem_resources[i].start) >> 12
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& 0x000fffff;
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/* Enable, Mem R/W */
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pcieow->pexowar = 0x80044000 |
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(__ilog2(hose->mem_resources[i].end
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- hose->mem_resources[i].start + 1)
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- 1);
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pcieow++;
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}
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/* Setup outbound IO window */
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if (hose->io_resource.flags & IORESOURCE_IO){
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DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
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hose->io_resource.start,
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hose->io_resource.end - hose->io_resource.start + 1,
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hose->io_base_phys);
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pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff;
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pcieow->pexotear = 0;
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pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff;
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/* Enable, IO R/W */
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pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end
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- hose->io_resource.start + 1) - 1);
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}
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/* Setup 2G inbound Memory Window @ 0 */
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pcieiw->pexitar = 0x00000000;
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pcieiw->pexiwbar = 0x00000000;
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/* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
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pcieiw->pexiwar = 0xa0f5501e;
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}
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static void __init
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mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
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{
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volatile struct ccsr_pex *pcie;
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u16 cmd;
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unsigned int temps;
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DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
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pcie_offset, pcie_size);
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pcie = ioremap(pcie_offset, pcie_size);
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early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
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| PCI_COMMAND_IO;
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early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
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early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
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/* PCIE Bus, Fix the MPC8641D host bridge's location to bus 0xFF. */
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early_read_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, &temps);
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temps = (temps & 0xff000000) | (0xff) | (0x0 << 8) | (0xfe << 16);
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early_write_config_dword(hose, 0, 0, PCI_PRIMARY_BUS, temps);
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}
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int __init add_bridge(struct device_node *dev)
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{
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int len;
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struct pci_controller *hose;
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struct resource rsrc;
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int *bus_range;
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int has_address = 0;
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int primary = 0;
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DBG("Adding PCIE host bridge %s\n", dev->full_name);
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/* Fetch host bridge registers address */
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has_address = (of_address_to_resource(dev, 0, &rsrc) == 0);
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/* Get bus range if any */
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bus_range = (int *) get_property(dev, "bus-range", &len);
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if (bus_range == NULL || len < 2 * sizeof(int))
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printk(KERN_WARNING "Can't get bus-range for %s, assume"
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" bus 0\n", dev->full_name);
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hose = pcibios_alloc_controller();
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if (!hose)
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return -ENOMEM;
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hose->arch_data = dev;
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hose->set_cfg_type = 1;
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/* last_busno = 0xfe cause by MPC8641 PCIE bug */
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hose->first_busno = bus_range ? bus_range[0] : 0x0;
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hose->last_busno = bus_range ? bus_range[1] : 0xfe;
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setup_indirect_pcie(hose, rsrc.start, rsrc.start + 0x4);
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/* Setup the PCIE host controller. */
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mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1);
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if ((rsrc.start & 0xfffff) == 0x8000)
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primary = 1;
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printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. "
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"Firmware bus number: %d->%d\n",
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rsrc.start, hose->first_busno, hose->last_busno);
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DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
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hose, hose->cfg_addr, hose->cfg_data);
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/* Interpret the "ranges" property */
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/* This also maps the I/O region and sets isa_io/mem_base */
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pci_process_bridge_OF_ranges(hose, dev, primary);
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/* Setup PEX window registers */
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setup_pcie_atmu(hose, &rsrc);
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return 0;
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}
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static void __devinit quirk_ali1575(struct pci_dev *dev)
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{
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unsigned short temp;
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/*
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* ALI1575 interrupts route table setup:
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*
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* IRQ pin IRQ#
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* PIRQA ---- 3
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* PIRQB ---- 4
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* PIRQC ---- 5
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* PIRQD ---- 6
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* PIRQE ---- 9
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* PIRQF ---- 10
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* PIRQG ---- 11
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* PIRQH ---- 12
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*
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* interrupts for PCI slot0 -- PIRQA / PIRQB / PIRQC / PIRQD
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* PCI slot1 -- PIRQB / PIRQC / PIRQD / PIRQA
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*/
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pci_write_config_dword(dev, 0x48, 0xb9317542);
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/* USB 1.1 OHCI controller 1, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x86, 0x0c);
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/* USB 1.1 OHCI controller 2, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x87, 0x0d);
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/* USB 1.1 OHCI controller 3, interrupt: PIRQH */
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pci_write_config_byte(dev, 0x88, 0x0f);
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/* USB 2.0 controller, interrupt: PIRQ7 */
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pci_write_config_byte(dev, 0x74, 0x06);
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/* Audio controller, interrupt: PIRQE */
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pci_write_config_byte(dev, 0x8a, 0x0c);
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/* Modem controller, interrupt: PIRQF */
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pci_write_config_byte(dev, 0x8b, 0x0d);
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/* HD audio controller, interrupt: PIRQG */
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pci_write_config_byte(dev, 0x8c, 0x0e);
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/* Serial ATA interrupt: PIRQD */
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pci_write_config_byte(dev, 0x8d, 0x0b);
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/* SMB interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8e, 0x0f);
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/* PMU ACPI SCI interrupt: PIRQH */
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pci_write_config_byte(dev, 0x8f, 0x0f);
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/* Primary PATA IDE IRQ: 14
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* Secondary PATA IDE IRQ: 15
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*/
|
||||
pci_write_config_byte(dev, 0x44, 0x3d);
|
||||
pci_write_config_byte(dev, 0x75, 0x0f);
|
||||
|
||||
/* Set IRQ14 and IRQ15 to legacy IRQs */
|
||||
pci_read_config_word(dev, 0x46, &temp);
|
||||
temp |= 0xc000;
|
||||
pci_write_config_word(dev, 0x46, temp);
|
||||
|
||||
/* Set i8259 interrupt trigger
|
||||
* IRQ 3: Level
|
||||
* IRQ 4: Level
|
||||
* IRQ 5: Level
|
||||
* IRQ 6: Level
|
||||
* IRQ 7: Level
|
||||
* IRQ 9: Level
|
||||
* IRQ 10: Level
|
||||
* IRQ 11: Level
|
||||
* IRQ 12: Level
|
||||
* IRQ 14: Edge
|
||||
* IRQ 15: Edge
|
||||
*/
|
||||
outb(0xfa, 0x4d0);
|
||||
outb(0x1e, 0x4d1);
|
||||
}
|
||||
|
||||
static void __devinit quirk_uli5288(struct pci_dev *dev)
|
||||
{
|
||||
unsigned char c;
|
||||
|
||||
pci_read_config_byte(dev,0x83,&c);
|
||||
c |= 0x80;
|
||||
pci_write_config_byte(dev, 0x83, c);
|
||||
|
||||
pci_write_config_byte(dev, 0x09, 0x01);
|
||||
pci_write_config_byte(dev, 0x0a, 0x06);
|
||||
|
||||
pci_read_config_byte(dev,0x83,&c);
|
||||
c &= 0x7f;
|
||||
pci_write_config_byte(dev, 0x83, c);
|
||||
|
||||
pci_read_config_byte(dev,0x84,&c);
|
||||
c |= 0x01;
|
||||
pci_write_config_byte(dev, 0x84, c);
|
||||
}
|
||||
|
||||
static void __devinit quirk_uli5229(struct pci_dev *dev)
|
||||
{
|
||||
unsigned short temp;
|
||||
pci_write_config_word(dev, 0x04, 0x0405);
|
||||
pci_read_config_word(dev, 0x4a, &temp);
|
||||
temp |= 0x1000;
|
||||
pci_write_config_word(dev, 0x4a, temp);
|
||||
}
|
||||
|
||||
static void __devinit early_uli5249(struct pci_dev *dev)
|
||||
{
|
||||
unsigned char temp;
|
||||
pci_write_config_word(dev, 0x04, 0x0007);
|
||||
pci_read_config_byte(dev, 0x7c, &temp);
|
||||
pci_write_config_byte(dev, 0x7c, 0x80);
|
||||
pci_write_config_byte(dev, 0x09, 0x01);
|
||||
pci_write_config_byte(dev, 0x7c, temp);
|
||||
dev->class |= 0x1;
|
||||
}
|
||||
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1575, quirk_ali1575);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5288, quirk_uli5288);
|
||||
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, quirk_uli5229);
|
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, 0x5249, early_uli5249);
|
||||
Loading…
Reference in New Issue
Block a user