forked from luck/tmp_suning_uos_patched
CRIS v32: arch-v32/hwregs/intr_vect_defs.h moved to machine dependent directory.
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Jesper Nilsson
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#ifndef __intr_vect_defs_h
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#define __intr_vect_defs_h
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/*
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* This file is autogenerated from
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* file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r
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* id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp
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* last modfied: Mon Apr 11 16:08:03 2005
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*
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* by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r
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* id: $Id: intr_vect_defs.h,v 1.8 2005/04/24 18:30:58 starvik Exp $
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* Any changes here will be lost.
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*
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* -*- buffer-read-only: t -*-
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*/
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/* Main access macros */
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#ifndef REG_RD
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#define REG_RD( scope, inst, reg ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR
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#define REG_WR( scope, inst, reg, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_VECT
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#define REG_RD_VECT( scope, inst, reg, index ) \
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REG_READ( reg_##scope##_##reg, \
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(inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_VECT
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#define REG_WR_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( reg_##scope##_##reg, \
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(inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT
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#define REG_RD_INT( scope, inst, reg ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT
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#define REG_WR_INT( scope, inst, reg, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
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#endif
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#ifndef REG_RD_INT_VECT
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#define REG_RD_INT_VECT( scope, inst, reg, index ) \
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REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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#ifndef REG_WR_INT_VECT
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#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
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REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg, (val) )
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#endif
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#ifndef REG_TYPE_CONV
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#define REG_TYPE_CONV( type, orgtype, val ) \
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( { union { orgtype o; type n; } r; r.o = val; r.n; } )
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#endif
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#ifndef reg_page_size
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#define reg_page_size 8192
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#endif
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#ifndef REG_ADDR
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#define REG_ADDR( scope, inst, reg ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg )
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#endif
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#ifndef REG_ADDR_VECT
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#define REG_ADDR_VECT( scope, inst, reg, index ) \
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( (inst) + REG_RD_ADDR_##scope##_##reg + \
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(index) * STRIDE_##scope##_##reg )
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#endif
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/* C-code for register scope intr_vect */
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/* Register rw_mask, scope intr_vect, type rw */
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typedef struct {
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unsigned int memarb : 1;
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unsigned int gen_io : 1;
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unsigned int iop0 : 1;
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unsigned int iop1 : 1;
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unsigned int iop2 : 1;
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unsigned int iop3 : 1;
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unsigned int dma0 : 1;
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unsigned int dma1 : 1;
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unsigned int dma2 : 1;
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unsigned int dma3 : 1;
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unsigned int dma4 : 1;
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unsigned int dma5 : 1;
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unsigned int dma6 : 1;
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unsigned int dma7 : 1;
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unsigned int dma8 : 1;
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unsigned int dma9 : 1;
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unsigned int ata : 1;
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unsigned int sser0 : 1;
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unsigned int sser1 : 1;
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unsigned int ser0 : 1;
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unsigned int ser1 : 1;
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unsigned int ser2 : 1;
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unsigned int ser3 : 1;
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unsigned int p21 : 1;
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unsigned int eth0 : 1;
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unsigned int eth1 : 1;
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unsigned int timer : 1;
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unsigned int bif_arb : 1;
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unsigned int bif_dma : 1;
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unsigned int ext : 1;
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unsigned int dummy1 : 2;
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} reg_intr_vect_rw_mask;
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#define REG_RD_ADDR_intr_vect_rw_mask 0
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#define REG_WR_ADDR_intr_vect_rw_mask 0
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/* Register r_vect, scope intr_vect, type r */
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typedef struct {
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unsigned int memarb : 1;
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unsigned int gen_io : 1;
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unsigned int iop0 : 1;
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unsigned int iop1 : 1;
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unsigned int iop2 : 1;
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unsigned int iop3 : 1;
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unsigned int dma0 : 1;
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unsigned int dma1 : 1;
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unsigned int dma2 : 1;
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unsigned int dma3 : 1;
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unsigned int dma4 : 1;
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unsigned int dma5 : 1;
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unsigned int dma6 : 1;
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unsigned int dma7 : 1;
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unsigned int dma8 : 1;
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unsigned int dma9 : 1;
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unsigned int ata : 1;
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unsigned int sser0 : 1;
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unsigned int sser1 : 1;
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unsigned int ser0 : 1;
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unsigned int ser1 : 1;
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unsigned int ser2 : 1;
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unsigned int ser3 : 1;
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unsigned int p21 : 1;
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unsigned int eth0 : 1;
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unsigned int eth1 : 1;
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unsigned int timer : 1;
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unsigned int bif_arb : 1;
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unsigned int bif_dma : 1;
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unsigned int ext : 1;
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unsigned int dummy1 : 2;
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} reg_intr_vect_r_vect;
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#define REG_RD_ADDR_intr_vect_r_vect 4
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/* Register r_masked_vect, scope intr_vect, type r */
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typedef struct {
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unsigned int memarb : 1;
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unsigned int gen_io : 1;
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unsigned int iop0 : 1;
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unsigned int iop1 : 1;
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unsigned int iop2 : 1;
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unsigned int iop3 : 1;
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unsigned int dma0 : 1;
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unsigned int dma1 : 1;
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unsigned int dma2 : 1;
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unsigned int dma3 : 1;
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unsigned int dma4 : 1;
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unsigned int dma5 : 1;
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unsigned int dma6 : 1;
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unsigned int dma7 : 1;
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unsigned int dma8 : 1;
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unsigned int dma9 : 1;
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unsigned int ata : 1;
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unsigned int sser0 : 1;
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unsigned int sser1 : 1;
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unsigned int ser0 : 1;
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unsigned int ser1 : 1;
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unsigned int ser2 : 1;
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unsigned int ser3 : 1;
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unsigned int p21 : 1;
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unsigned int eth0 : 1;
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unsigned int eth1 : 1;
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unsigned int timer : 1;
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unsigned int bif_arb : 1;
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unsigned int bif_dma : 1;
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unsigned int ext : 1;
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unsigned int dummy1 : 2;
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} reg_intr_vect_r_masked_vect;
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#define REG_RD_ADDR_intr_vect_r_masked_vect 8
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/* Register r_nmi, scope intr_vect, type r */
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typedef struct {
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unsigned int ext : 1;
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unsigned int watchdog : 1;
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unsigned int dummy1 : 30;
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} reg_intr_vect_r_nmi;
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#define REG_RD_ADDR_intr_vect_r_nmi 12
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/* Register r_guru, scope intr_vect, type r */
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typedef struct {
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unsigned int jtag : 1;
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unsigned int dummy1 : 31;
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} reg_intr_vect_r_guru;
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#define REG_RD_ADDR_intr_vect_r_guru 16
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/* Register rw_ipi, scope intr_vect, type rw */
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typedef struct
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{
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unsigned int vector;
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} reg_intr_vect_rw_ipi;
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#define REG_RD_ADDR_intr_vect_rw_ipi 20
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#define REG_WR_ADDR_intr_vect_rw_ipi 20
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/* Constants */
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enum {
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regk_intr_vect_off = 0x00000000,
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regk_intr_vect_on = 0x00000001,
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regk_intr_vect_rw_mask_default = 0x00000000
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};
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#endif /* __intr_vect_defs_h */
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