forked from luck/tmp_suning_uos_patched
drm/i915: Add new chipset register definitions
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Zhenyu Wang
Eric Anholt
parent
280da227c8
commit
b9055052d3
@ -450,6 +450,13 @@
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#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
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#define PLL_REF_INPUT_MASK (3 << 13)
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#define PLL_LOAD_PULSE_PHASE_SHIFT 9
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/* IGDNG */
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# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
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# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
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# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
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# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
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# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
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/*
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* Parallel to Serial Load Pulse phase selection.
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* Selects the phase for the 10X DPLL clock for the PCIe
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@ -1517,4 +1524,444 @@
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# define VGA_2X_MODE (1 << 30)
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# define VGA_PIPE_B_SELECT (1 << 29)
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/* IGDNG */
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#define CPU_VGACNTRL 0x41000
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#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
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#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
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#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
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#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
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#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
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#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
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#define DIGITAL_PORTA_NO_DETECT (0 << 0)
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#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
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#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
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/* refresh rate hardware control */
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#define RR_HW_CTL 0x45300
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#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
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#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
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#define FDI_PLL_BIOS_0 0x46000
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#define FDI_PLL_BIOS_1 0x46004
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#define FDI_PLL_BIOS_2 0x46008
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#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
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#define DISPLAY_PORT_PLL_BIOS_1 0x46010
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#define DISPLAY_PORT_PLL_BIOS_2 0x46014
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#define FDI_PLL_FREQ_CTL 0x46030
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#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
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#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
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#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
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#define PIPEA_DATA_M1 0x60030
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#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
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#define TU_SIZE_MASK 0x7e000000
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#define PIPEA_DATA_M1_OFFSET 0
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#define PIPEA_DATA_N1 0x60034
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#define PIPEA_DATA_N1_OFFSET 0
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#define PIPEA_DATA_M2 0x60038
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#define PIPEA_DATA_M2_OFFSET 0
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#define PIPEA_DATA_N2 0x6003c
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#define PIPEA_DATA_N2_OFFSET 0
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#define PIPEA_LINK_M1 0x60040
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#define PIPEA_LINK_M1_OFFSET 0
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#define PIPEA_LINK_N1 0x60044
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#define PIPEA_LINK_N1_OFFSET 0
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#define PIPEA_LINK_M2 0x60048
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#define PIPEA_LINK_M2_OFFSET 0
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#define PIPEA_LINK_N2 0x6004c
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#define PIPEA_LINK_N2_OFFSET 0
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/* PIPEB timing regs are same start from 0x61000 */
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#define PIPEB_DATA_M1 0x61030
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#define PIPEB_DATA_M1_OFFSET 0
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#define PIPEB_DATA_N1 0x61034
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#define PIPEB_DATA_N1_OFFSET 0
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#define PIPEB_DATA_M2 0x61038
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#define PIPEB_DATA_M2_OFFSET 0
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#define PIPEB_DATA_N2 0x6103c
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#define PIPEB_DATA_N2_OFFSET 0
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#define PIPEB_LINK_M1 0x61040
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#define PIPEB_LINK_M1_OFFSET 0
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#define PIPEB_LINK_N1 0x61044
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#define PIPEB_LINK_N1_OFFSET 0
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#define PIPEB_LINK_M2 0x61048
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#define PIPEB_LINK_M2_OFFSET 0
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#define PIPEB_LINK_N2 0x6104c
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#define PIPEB_LINK_N2_OFFSET 0
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/* CPU panel fitter */
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#define PFA_CTL_1 0x68080
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#define PFB_CTL_1 0x68880
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#define PF_ENABLE (1<<31)
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/* legacy palette */
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#define LGC_PALETTE_A 0x4a000
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#define LGC_PALETTE_B 0x4a800
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/* interrupts */
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#define DE_MASTER_IRQ_CONTROL (1 << 31)
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#define DE_SPRITEB_FLIP_DONE (1 << 29)
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#define DE_SPRITEA_FLIP_DONE (1 << 28)
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#define DE_PLANEB_FLIP_DONE (1 << 27)
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#define DE_PLANEA_FLIP_DONE (1 << 26)
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#define DE_PCU_EVENT (1 << 25)
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#define DE_GTT_FAULT (1 << 24)
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#define DE_POISON (1 << 23)
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#define DE_PERFORM_COUNTER (1 << 22)
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#define DE_PCH_EVENT (1 << 21)
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#define DE_AUX_CHANNEL_A (1 << 20)
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#define DE_DP_A_HOTPLUG (1 << 19)
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#define DE_GSE (1 << 18)
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#define DE_PIPEB_VBLANK (1 << 15)
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#define DE_PIPEB_EVEN_FIELD (1 << 14)
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#define DE_PIPEB_ODD_FIELD (1 << 13)
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#define DE_PIPEB_LINE_COMPARE (1 << 12)
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#define DE_PIPEB_VSYNC (1 << 11)
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#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
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#define DE_PIPEA_VBLANK (1 << 7)
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#define DE_PIPEA_EVEN_FIELD (1 << 6)
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#define DE_PIPEA_ODD_FIELD (1 << 5)
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#define DE_PIPEA_LINE_COMPARE (1 << 4)
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#define DE_PIPEA_VSYNC (1 << 3)
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#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
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#define DEISR 0x44000
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#define DEIMR 0x44004
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#define DEIIR 0x44008
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#define DEIER 0x4400c
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/* GT interrupt */
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#define GT_SYNC_STATUS (1 << 2)
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#define GT_USER_INTERRUPT (1 << 0)
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#define GTISR 0x44010
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#define GTIMR 0x44014
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#define GTIIR 0x44018
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#define GTIER 0x4401c
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/* PCH */
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/* south display engine interrupt */
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#define SDE_CRT_HOTPLUG (1 << 11)
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#define SDE_PORTD_HOTPLUG (1 << 10)
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#define SDE_PORTC_HOTPLUG (1 << 9)
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#define SDE_PORTB_HOTPLUG (1 << 8)
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#define SDE_SDVOB_HOTPLUG (1 << 6)
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#define SDEISR 0xc4000
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#define SDEIMR 0xc4004
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#define SDEIIR 0xc4008
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#define SDEIER 0xc400c
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/* digital port hotplug */
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#define PCH_PORT_HOTPLUG 0xc4030
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#define PORTD_HOTPLUG_ENABLE (1 << 20)
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#define PORTD_PULSE_DURATION_2ms (0)
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#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
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#define PORTD_PULSE_DURATION_6ms (2 << 18)
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#define PORTD_PULSE_DURATION_100ms (3 << 18)
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#define PORTD_HOTPLUG_NO_DETECT (0)
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#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
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#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
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#define PORTC_HOTPLUG_ENABLE (1 << 12)
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#define PORTC_PULSE_DURATION_2ms (0)
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#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
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#define PORTC_PULSE_DURATION_6ms (2 << 10)
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#define PORTC_PULSE_DURATION_100ms (3 << 10)
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#define PORTC_HOTPLUG_NO_DETECT (0)
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#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
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#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
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#define PORTB_HOTPLUG_ENABLE (1 << 4)
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#define PORTB_PULSE_DURATION_2ms (0)
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#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
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#define PORTB_PULSE_DURATION_6ms (2 << 2)
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#define PORTB_PULSE_DURATION_100ms (3 << 2)
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#define PORTB_HOTPLUG_NO_DETECT (0)
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#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
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#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
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#define PCH_GPIOA 0xc5010
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#define PCH_GPIOB 0xc5014
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#define PCH_GPIOC 0xc5018
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#define PCH_GPIOD 0xc501c
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#define PCH_GPIOE 0xc5020
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#define PCH_GPIOF 0xc5024
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#define PCH_DPLL_A 0xc6014
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#define PCH_DPLL_B 0xc6018
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#define PCH_FPA0 0xc6040
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#define PCH_FPA1 0xc6044
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#define PCH_FPB0 0xc6048
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#define PCH_FPB1 0xc604c
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#define PCH_DPLL_TEST 0xc606c
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#define PCH_DREF_CONTROL 0xC6200
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#define DREF_CONTROL_MASK 0x7fc3
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#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
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#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
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#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
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#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
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#define DREF_SSC_SOURCE_DISABLE (0<<11)
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#define DREF_SSC_SOURCE_ENABLE (2<<11)
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#define DREF_SSC_SOURCE_MASK (2<<11)
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#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
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#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
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#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
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#define DREF_NONSPREAD_SOURCE_MASK (2<<9)
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#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
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#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
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#define DREF_SSC4_DOWNSPREAD (0<<6)
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#define DREF_SSC4_CENTERSPREAD (1<<6)
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#define DREF_SSC1_DISABLE (0<<1)
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#define DREF_SSC1_ENABLE (1<<1)
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#define DREF_SSC4_DISABLE (0)
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#define DREF_SSC4_ENABLE (1)
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#define PCH_RAWCLK_FREQ 0xc6204
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#define FDL_TP1_TIMER_SHIFT 12
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#define FDL_TP1_TIMER_MASK (3<<12)
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#define FDL_TP2_TIMER_SHIFT 10
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#define FDL_TP2_TIMER_MASK (3<<10)
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#define RAWCLK_FREQ_MASK 0x3ff
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#define PCH_DPLL_TMR_CFG 0xc6208
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#define PCH_SSC4_PARMS 0xc6210
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#define PCH_SSC4_AUX_PARMS 0xc6214
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/* transcoder */
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#define TRANS_HTOTAL_A 0xe0000
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#define TRANS_HTOTAL_SHIFT 16
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#define TRANS_HACTIVE_SHIFT 0
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#define TRANS_HBLANK_A 0xe0004
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#define TRANS_HBLANK_END_SHIFT 16
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#define TRANS_HBLANK_START_SHIFT 0
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#define TRANS_HSYNC_A 0xe0008
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#define TRANS_HSYNC_END_SHIFT 16
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#define TRANS_HSYNC_START_SHIFT 0
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#define TRANS_VTOTAL_A 0xe000c
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#define TRANS_VTOTAL_SHIFT 16
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#define TRANS_VACTIVE_SHIFT 0
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#define TRANS_VBLANK_A 0xe0010
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#define TRANS_VBLANK_END_SHIFT 16
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#define TRANS_VBLANK_START_SHIFT 0
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#define TRANS_VSYNC_A 0xe0014
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#define TRANS_VSYNC_END_SHIFT 16
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#define TRANS_VSYNC_START_SHIFT 0
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#define TRANSA_DATA_M1 0xe0030
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#define TRANSA_DATA_N1 0xe0034
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#define TRANSA_DATA_M2 0xe0038
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#define TRANSA_DATA_N2 0xe003c
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#define TRANSA_DP_LINK_M1 0xe0040
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#define TRANSA_DP_LINK_N1 0xe0044
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#define TRANSA_DP_LINK_M2 0xe0048
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#define TRANSA_DP_LINK_N2 0xe004c
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#define TRANS_HTOTAL_B 0xe1000
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#define TRANS_HBLANK_B 0xe1004
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#define TRANS_HSYNC_B 0xe1008
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#define TRANS_VTOTAL_B 0xe100c
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#define TRANS_VBLANK_B 0xe1010
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#define TRANS_VSYNC_B 0xe1014
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#define TRANSB_DATA_M1 0xe1030
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#define TRANSB_DATA_N1 0xe1034
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#define TRANSB_DATA_M2 0xe1038
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#define TRANSB_DATA_N2 0xe103c
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#define TRANSB_DP_LINK_M1 0xe1040
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#define TRANSB_DP_LINK_N1 0xe1044
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#define TRANSB_DP_LINK_M2 0xe1048
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#define TRANSB_DP_LINK_N2 0xe104c
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#define TRANSACONF 0xf0008
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#define TRANSBCONF 0xf1008
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#define TRANS_DISABLE (0<<31)
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#define TRANS_ENABLE (1<<31)
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#define TRANS_STATE_MASK (1<<30)
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#define TRANS_STATE_DISABLE (0<<30)
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#define TRANS_STATE_ENABLE (1<<30)
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#define TRANS_FSYNC_DELAY_HB1 (0<<27)
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#define TRANS_FSYNC_DELAY_HB2 (1<<27)
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#define TRANS_FSYNC_DELAY_HB3 (2<<27)
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#define TRANS_FSYNC_DELAY_HB4 (3<<27)
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#define TRANS_DP_AUDIO_ONLY (1<<26)
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#define TRANS_DP_VIDEO_AUDIO (0<<26)
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#define TRANS_PROGRESSIVE (0<<21)
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#define TRANS_8BPC (0<<5)
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#define TRANS_10BPC (1<<5)
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#define TRANS_6BPC (2<<5)
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#define TRANS_12BPC (3<<5)
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#define FDI_RXA_CHICKEN 0xc200c
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#define FDI_RXB_CHICKEN 0xc2010
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#define FDI_RX_PHASE_SYNC_POINTER_ENABLE (1)
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/* CPU: FDI_TX */
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#define FDI_TXA_CTL 0x60100
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#define FDI_TXB_CTL 0x61100
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#define FDI_TX_DISABLE (0<<31)
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#define FDI_TX_ENABLE (1<<31)
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#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
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#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
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#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
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#define FDI_LINK_TRAIN_NONE (3<<28)
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#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
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#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
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#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
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#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
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#define FDI_DP_PORT_WIDTH_X1 (0<<19)
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#define FDI_DP_PORT_WIDTH_X2 (1<<19)
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#define FDI_DP_PORT_WIDTH_X3 (2<<19)
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#define FDI_DP_PORT_WIDTH_X4 (3<<19)
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#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
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/* IGDNG: hardwired to 1 */
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#define FDI_TX_PLL_ENABLE (1<<14)
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/* both Tx and Rx */
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#define FDI_SCRAMBLING_ENABLE (0<<7)
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#define FDI_SCRAMBLING_DISABLE (1<<7)
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/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
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#define FDI_RXA_CTL 0xf000c
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#define FDI_RXB_CTL 0xf100c
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#define FDI_RX_ENABLE (1<<31)
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#define FDI_RX_DISABLE (0<<31)
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/* train, dp width same as FDI_TX */
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#define FDI_DP_PORT_WIDTH_X8 (7<<19)
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#define FDI_8BPC (0<<16)
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#define FDI_10BPC (1<<16)
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#define FDI_6BPC (2<<16)
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#define FDI_12BPC (3<<16)
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#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
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#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
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#define FDI_RX_PLL_ENABLE (1<<13)
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#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
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#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
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#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
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#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
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#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
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#define FDI_SEL_RAWCLK (0<<4)
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#define FDI_SEL_PCDCLK (1<<4)
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#define FDI_RXA_MISC 0xf0010
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#define FDI_RXB_MISC 0xf1010
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#define FDI_RXA_TUSIZE1 0xf0030
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#define FDI_RXA_TUSIZE2 0xf0038
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#define FDI_RXB_TUSIZE1 0xf1030
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#define FDI_RXB_TUSIZE2 0xf1038
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/* FDI_RX interrupt register format */
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#define FDI_RX_INTER_LANE_ALIGN (1<<10)
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#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
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#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
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#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
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#define FDI_RX_FS_CODE_ERR (1<<6)
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#define FDI_RX_FE_CODE_ERR (1<<5)
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#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
|
||||
#define FDI_RX_HDCP_LINK_FAIL (1<<3)
|
||||
#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
|
||||
#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
|
||||
#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
|
||||
|
||||
#define FDI_RXA_IIR 0xf0014
|
||||
#define FDI_RXA_IMR 0xf0018
|
||||
#define FDI_RXB_IIR 0xf1014
|
||||
#define FDI_RXB_IMR 0xf1018
|
||||
|
||||
#define FDI_PLL_CTL_1 0xfe000
|
||||
#define FDI_PLL_CTL_2 0xfe004
|
||||
|
||||
/* CRT */
|
||||
#define PCH_ADPA 0xe1100
|
||||
#define ADPA_TRANS_SELECT_MASK (1<<30)
|
||||
#define ADPA_TRANS_A_SELECT 0
|
||||
#define ADPA_TRANS_B_SELECT (1<<30)
|
||||
#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
|
||||
#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
|
||||
#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
|
||||
#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
|
||||
#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
|
||||
#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
|
||||
#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
|
||||
#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
|
||||
#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
|
||||
#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
|
||||
#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
|
||||
#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
|
||||
#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
|
||||
#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
|
||||
#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
|
||||
#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
|
||||
#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
|
||||
#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
|
||||
#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
|
||||
|
||||
/* or SDVOB */
|
||||
#define HDMIB 0xe1140
|
||||
#define PORT_ENABLE (1 << 31)
|
||||
#define TRANSCODER_A (0)
|
||||
#define TRANSCODER_B (1 << 30)
|
||||
#define COLOR_FORMAT_8bpc (0)
|
||||
#define COLOR_FORMAT_12bpc (3 << 26)
|
||||
#define SDVOB_HOTPLUG_ENABLE (1 << 23)
|
||||
#define SDVO_ENCODING (0)
|
||||
#define TMDS_ENCODING (2 << 10)
|
||||
#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
|
||||
#define SDVOB_BORDER_ENABLE (1 << 7)
|
||||
#define AUDIO_ENABLE (1 << 6)
|
||||
#define VSYNC_ACTIVE_HIGH (1 << 4)
|
||||
#define HSYNC_ACTIVE_HIGH (1 << 3)
|
||||
#define PORT_DETECTED (1 << 2)
|
||||
|
||||
#define HDMIC 0xe1150
|
||||
#define HDMID 0xe1160
|
||||
|
||||
#define PCH_LVDS 0xe1180
|
||||
#define LVDS_DETECTED (1 << 1)
|
||||
|
||||
#define BLC_PWM_CPU_CTL2 0x48250
|
||||
#define PWM_ENABLE (1 << 31)
|
||||
#define PWM_PIPE_A (0 << 29)
|
||||
#define PWM_PIPE_B (1 << 29)
|
||||
#define BLC_PWM_CPU_CTL 0x48254
|
||||
|
||||
#define BLC_PWM_PCH_CTL1 0xc8250
|
||||
#define PWM_PCH_ENABLE (1 << 31)
|
||||
#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
|
||||
#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
|
||||
#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
|
||||
#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
|
||||
|
||||
#define BLC_PWM_PCH_CTL2 0xc8254
|
||||
|
||||
#define PCH_PP_STATUS 0xc7200
|
||||
#define PCH_PP_CONTROL 0xc7204
|
||||
#define EDP_FORCE_VDD (1 << 3)
|
||||
#define EDP_BLC_ENABLE (1 << 2)
|
||||
#define PANEL_POWER_RESET (1 << 1)
|
||||
#define PANEL_POWER_OFF (0 << 0)
|
||||
#define PANEL_POWER_ON (1 << 0)
|
||||
#define PCH_PP_ON_DELAYS 0xc7208
|
||||
#define EDP_PANEL (1 << 30)
|
||||
#define PCH_PP_OFF_DELAYS 0xc720c
|
||||
#define PCH_PP_DIVISOR 0xc7210
|
||||
|
||||
#endif /* _I915_REG_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user