forked from luck/tmp_suning_uos_patched
IIO: Ingenic JZ47xx: Add touchscreen mode.
The SADC component in JZ47xx SoCs provides support for touchscreen operations (pen position and pen down pressure) in single-ended and differential modes. The touchscreen component of SADC takes a significant time to stabilize after first receiving the clock and a delay of 50ms has been empirically proven to be a safe value before data sampling can begin. Of the known hardware to use this controller, GCW Zero and Anbernic RG-350 utilize the touchscreen mode by having their joystick(s) attached to the X/Y positive/negative input pins. JZ4770 and later SoCs introduce a low-level command feature. With it, up to 32 commands can be programmed, each one corresponding to a sampling job. It allows to change the low-voltage reference, the high-voltage reference, have them connected to VCC, GND, or one of the X-/X+ or Y-/Y+ pins. This patch introduces support for 6 stream-capable channels: - channel #0 samples X+/GND - channel #1 samples Y+/GND - channel #2 samples X-/GND - channel #3 samples Y-/GND - channel #4 samples X+/X- - channel #5 samples Y+/Y- Being able to sample X-/GND and Y-/GND is useful on some devices, where one joystick is connected to the X+/Y+ pins, and a second joystick is connected to the X-/Y- pins. All the boards which probe this driver have the interrupt provided from Device Tree, with no need to handle a case where the IRQ was not provided. Co-developed-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Artur Rojek <contact@artur-rojek.eu> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
This commit is contained in:
Artur Rojek
Jonathan Cameron
parent
842247203c
commit
b96952f498
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@ -465,6 +465,7 @@ config INA2XX_ADC
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config INGENIC_ADC
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tristate "Ingenic JZ47xx SoCs ADC driver"
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depends on MIPS || COMPILE_TEST
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select IIO_BUFFER
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help
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Say yes here to build support for the Ingenic JZ47xx SoCs ADC unit.
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@ -8,7 +8,9 @@
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#include <dt-bindings/iio/adc/ingenic,adc.h>
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#include <linux/clk.h>
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#include <linux/iio/buffer.h>
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#include <linux/iio/iio.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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@ -20,19 +22,46 @@
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#define JZ_ADC_REG_CFG 0x04
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#define JZ_ADC_REG_CTRL 0x08
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#define JZ_ADC_REG_STATUS 0x0c
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#define JZ_ADC_REG_ADSAME 0x10
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#define JZ_ADC_REG_ADWAIT 0x14
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#define JZ_ADC_REG_ADTCH 0x18
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#define JZ_ADC_REG_ADBDAT 0x1c
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#define JZ_ADC_REG_ADSDAT 0x20
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#define JZ_ADC_REG_ADCMD 0x24
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#define JZ_ADC_REG_ADCLK 0x28
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#define JZ_ADC_REG_ENABLE_PD BIT(7)
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#define JZ_ADC_REG_CFG_AUX_MD (BIT(0) | BIT(1))
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#define JZ_ADC_REG_CFG_BAT_MD BIT(4)
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#define JZ_ADC_REG_CFG_SAMPLE_NUM(n) ((n) << 10)
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#define JZ_ADC_REG_CFG_PULL_UP(n) ((n) << 16)
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#define JZ_ADC_REG_CFG_CMD_SEL BIT(22)
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#define JZ_ADC_REG_CFG_TOUCH_OPS_MASK (BIT(31) | GENMASK(23, 10))
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#define JZ_ADC_REG_ADCLK_CLKDIV_LSB 0
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#define JZ4725B_ADC_REG_ADCLK_CLKDIV10US_LSB 16
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#define JZ4770_ADC_REG_ADCLK_CLKDIV10US_LSB 8
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#define JZ4770_ADC_REG_ADCLK_CLKDIVMS_LSB 16
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#define JZ_ADC_REG_ADCMD_YNADC BIT(7)
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#define JZ_ADC_REG_ADCMD_YPADC BIT(8)
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#define JZ_ADC_REG_ADCMD_XNADC BIT(9)
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#define JZ_ADC_REG_ADCMD_XPADC BIT(10)
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#define JZ_ADC_REG_ADCMD_VREFPYP BIT(11)
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#define JZ_ADC_REG_ADCMD_VREFPXP BIT(12)
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#define JZ_ADC_REG_ADCMD_VREFPXN BIT(13)
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#define JZ_ADC_REG_ADCMD_VREFPAUX BIT(14)
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#define JZ_ADC_REG_ADCMD_VREFPVDD33 BIT(15)
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#define JZ_ADC_REG_ADCMD_VREFNYN BIT(16)
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#define JZ_ADC_REG_ADCMD_VREFNXP BIT(17)
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#define JZ_ADC_REG_ADCMD_VREFNXN BIT(18)
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#define JZ_ADC_REG_ADCMD_VREFAUX BIT(19)
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#define JZ_ADC_REG_ADCMD_YNGRU BIT(20)
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#define JZ_ADC_REG_ADCMD_XNGRU BIT(21)
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#define JZ_ADC_REG_ADCMD_XPGRU BIT(22)
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#define JZ_ADC_REG_ADCMD_YPSUP BIT(23)
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#define JZ_ADC_REG_ADCMD_XNSUP BIT(24)
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#define JZ_ADC_REG_ADCMD_XPSUP BIT(25)
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#define JZ_ADC_AUX_VREF 3300
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#define JZ_ADC_AUX_VREF_BITS 12
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#define JZ_ADC_BATTERY_LOW_VREF 2500
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@ -44,6 +73,14 @@
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#define JZ4770_ADC_BATTERY_VREF 6600
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#define JZ4770_ADC_BATTERY_VREF_BITS 12
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#define JZ_ADC_IRQ_AUX BIT(0)
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#define JZ_ADC_IRQ_BATTERY BIT(1)
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#define JZ_ADC_IRQ_TOUCH BIT(2)
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#define JZ_ADC_IRQ_PEN_DOWN BIT(3)
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#define JZ_ADC_IRQ_PEN_UP BIT(4)
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#define JZ_ADC_IRQ_PEN_DOWN_SLEEP BIT(5)
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#define JZ_ADC_IRQ_SLEEP BIT(7)
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struct ingenic_adc;
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struct ingenic_adc_soc_data {
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@ -69,6 +106,61 @@ struct ingenic_adc {
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bool low_vref_mode;
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};
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static void ingenic_adc_set_adcmd(struct iio_dev *iio_dev, unsigned long mask)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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mutex_lock(&adc->lock);
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/* Init ADCMD */
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readl(adc->base + JZ_ADC_REG_ADCMD);
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if (mask & 0x3) {
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/* Second channel (INGENIC_ADC_TOUCH_YP): sample YP vs. GND */
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writel(JZ_ADC_REG_ADCMD_XNGRU
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| JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_YPADC,
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adc->base + JZ_ADC_REG_ADCMD);
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/* First channel (INGENIC_ADC_TOUCH_XP): sample XP vs. GND */
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writel(JZ_ADC_REG_ADCMD_YNGRU
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| JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_XPADC,
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adc->base + JZ_ADC_REG_ADCMD);
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}
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if (mask & 0xc) {
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/* Fourth channel (INGENIC_ADC_TOUCH_YN): sample YN vs. GND */
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writel(JZ_ADC_REG_ADCMD_XNGRU
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| JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_YNADC,
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adc->base + JZ_ADC_REG_ADCMD);
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/* Third channel (INGENIC_ADC_TOUCH_XN): sample XN vs. GND */
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writel(JZ_ADC_REG_ADCMD_YNGRU
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| JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_XNADC,
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adc->base + JZ_ADC_REG_ADCMD);
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}
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if (mask & 0x30) {
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/* Sixth channel (INGENIC_ADC_TOUCH_YD): sample YP vs. YN */
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writel(JZ_ADC_REG_ADCMD_VREFNYN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_YPADC,
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adc->base + JZ_ADC_REG_ADCMD);
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/* Fifth channel (INGENIC_ADC_TOUCH_XD): sample XP vs. XN */
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writel(JZ_ADC_REG_ADCMD_VREFNXN | JZ_ADC_REG_ADCMD_VREFPVDD33
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| JZ_ADC_REG_ADCMD_XPADC,
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adc->base + JZ_ADC_REG_ADCMD);
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}
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/* We're done */
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writel(0, adc->base + JZ_ADC_REG_ADCMD);
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mutex_unlock(&adc->lock);
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}
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static void ingenic_adc_set_config(struct ingenic_adc *adc,
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uint32_t mask,
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uint32_t val)
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@ -288,6 +380,72 @@ static const struct iio_chan_spec jz4740_channels[] = {
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};
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static const struct iio_chan_spec jz4770_channels[] = {
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_XP,
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.scan_index = 0,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_YP,
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.scan_index = 1,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_XN,
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.scan_index = 2,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_YN,
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.scan_index = 3,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_XD,
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.scan_index = 4,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.type = IIO_VOLTAGE,
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.indexed = 1,
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.channel = INGENIC_ADC_TOUCH_YD,
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.scan_index = 5,
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.scan_type = {
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.sign = 'u',
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.realbits = 12,
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.storagebits = 16,
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},
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},
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{
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.extend_name = "aux",
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.type = IIO_VOLTAGE,
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@ -491,13 +649,89 @@ static const struct iio_info ingenic_adc_info = {
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.of_xlate = ingenic_adc_of_xlate,
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};
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static int ingenic_adc_buffer_enable(struct iio_dev *iio_dev)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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int ret;
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ret = clk_enable(adc->clk);
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if (ret) {
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dev_err(iio_dev->dev.parent, "Failed to enable clock: %d\n",
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ret);
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return ret;
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}
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/* It takes significant time for the touchscreen hw to stabilize. */
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msleep(50);
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ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK,
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JZ_ADC_REG_CFG_SAMPLE_NUM(4) |
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JZ_ADC_REG_CFG_PULL_UP(4));
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writew(80, adc->base + JZ_ADC_REG_ADWAIT);
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writew(2, adc->base + JZ_ADC_REG_ADSAME);
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writeb((u8)~JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_CTRL);
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writel(0, adc->base + JZ_ADC_REG_ADTCH);
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ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL,
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JZ_ADC_REG_CFG_CMD_SEL);
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ingenic_adc_set_adcmd(iio_dev, iio_dev->active_scan_mask[0]);
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ingenic_adc_enable(adc, 2, true);
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return 0;
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}
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static int ingenic_adc_buffer_disable(struct iio_dev *iio_dev)
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{
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struct ingenic_adc *adc = iio_priv(iio_dev);
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ingenic_adc_enable(adc, 2, false);
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ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_CMD_SEL, 0);
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writeb(0xff, adc->base + JZ_ADC_REG_CTRL);
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writeb(0xff, adc->base + JZ_ADC_REG_STATUS);
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ingenic_adc_set_config(adc, JZ_ADC_REG_CFG_TOUCH_OPS_MASK, 0);
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writew(0, adc->base + JZ_ADC_REG_ADSAME);
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writew(0, adc->base + JZ_ADC_REG_ADWAIT);
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clk_disable(adc->clk);
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return 0;
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}
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static const struct iio_buffer_setup_ops ingenic_buffer_setup_ops = {
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.postenable = &ingenic_adc_buffer_enable,
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.predisable = &ingenic_adc_buffer_disable
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};
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static irqreturn_t ingenic_adc_irq(int irq, void *data)
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{
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struct iio_dev *iio_dev = data;
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struct ingenic_adc *adc = iio_priv(iio_dev);
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unsigned long mask = iio_dev->active_scan_mask[0];
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unsigned int i;
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u32 tdat[3];
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for (i = 0; i < ARRAY_SIZE(tdat); mask >>= 2, i++) {
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if (mask & 0x3)
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tdat[i] = readl(adc->base + JZ_ADC_REG_ADTCH);
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else
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tdat[i] = 0;
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}
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iio_push_to_buffers(iio_dev, tdat);
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writeb(JZ_ADC_IRQ_TOUCH, adc->base + JZ_ADC_REG_STATUS);
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return IRQ_HANDLED;
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}
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static int ingenic_adc_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct iio_dev *iio_dev;
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struct ingenic_adc *adc;
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const struct ingenic_adc_soc_data *soc_data;
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int ret;
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int irq, ret;
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soc_data = device_get_match_data(dev);
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if (!soc_data)
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@ -512,6 +746,17 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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mutex_init(&adc->aux_lock);
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adc->soc_data = soc_data;
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(dev, irq, ingenic_adc_irq, 0,
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dev_name(dev), iio_dev);
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if (ret < 0) {
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dev_err(dev, "Failed to request irq: %d\n", ret);
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return ret;
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}
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adc->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(adc->base))
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return PTR_ERR(adc->base);
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@ -551,7 +796,8 @@ static int ingenic_adc_probe(struct platform_device *pdev)
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iio_dev->dev.parent = dev;
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iio_dev->name = "jz-adc";
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iio_dev->modes = INDIO_DIRECT_MODE;
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iio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
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iio_dev->setup_ops = &ingenic_buffer_setup_ops;
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iio_dev->channels = soc_data->channels;
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iio_dev->num_channels = soc_data->num_channels;
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iio_dev->info = &ingenic_adc_info;
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