forked from luck/tmp_suning_uos_patched
agp/intel: Experiment with a 855GM GWB bit
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27187 Tested-by: Thorsten Vollmer <thorsten@thvo.de> (DFI-ACP G5M150-N w/852GME) Tested-by: Moritz Brunner <2points@gmx.org> (Asus M2400N/i855GM) Tested-by: Indan Zupancic <indan@nul.nu> (Thinkpad X40/855GM rev 02) Tested-by: Eric Anholt <eric@anholt.net> (865G) Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -130,6 +130,7 @@
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I915_IFPADDR 0x60
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#define I830_HIC 0x70
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/* Intel 965G registers */
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#define I965_MSAC 0x62
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@ -21,6 +21,7 @@
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#include <linux/kernel.h>
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#include <linux/pagemap.h>
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#include <linux/agp_backend.h>
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#include <linux/delay.h>
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#include <asm/smp.h>
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#include "agp.h"
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#include "intel-agp.h"
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@ -70,12 +71,8 @@ static struct _intel_private {
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u32 __iomem *gtt; /* I915G */
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bool clear_fake_agp; /* on first access via agp, fill with scratch */
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int num_dcache_entries;
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union {
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void __iomem *i9xx_flush_page;
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void *i8xx_flush_page;
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};
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void __iomem *i9xx_flush_page;
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char *i81x_gtt_table;
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struct page *i8xx_page;
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struct resource ifp_resource;
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int resource_valid;
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struct page *scratch_page;
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@ -722,28 +719,6 @@ static int intel_fake_agp_fetch_size(void)
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static void i830_cleanup(void)
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{
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if (intel_private.i8xx_flush_page) {
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kunmap(intel_private.i8xx_flush_page);
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intel_private.i8xx_flush_page = NULL;
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}
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__free_page(intel_private.i8xx_page);
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intel_private.i8xx_page = NULL;
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}
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static void intel_i830_setup_flush(void)
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{
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/* return if we've already set the flush mechanism up */
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if (intel_private.i8xx_page)
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return;
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intel_private.i8xx_page = alloc_page(GFP_KERNEL);
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if (!intel_private.i8xx_page)
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return;
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intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
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if (!intel_private.i8xx_flush_page)
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i830_cleanup();
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}
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/* The chipset_flush interface needs to get data that has already been
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@ -758,14 +733,27 @@ static void intel_i830_setup_flush(void)
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*/
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static void i830_chipset_flush(void)
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{
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unsigned int *pg = intel_private.i8xx_flush_page;
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unsigned long timeout = jiffies + msecs_to_jiffies(1000);
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memset(pg, 0, 1024);
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/* Forcibly evict everything from the CPU write buffers.
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* clflush appears to be insufficient.
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*/
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wbinvd_on_all_cpus();
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if (cpu_has_clflush)
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clflush_cache_range(pg, 1024);
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else if (wbinvd_on_all_cpus() != 0)
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printk(KERN_ERR "Timed out waiting for cache flush.\n");
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/* Now we've only seen documents for this magic bit on 855GM,
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* we hope it exists for the other gen2 chipsets...
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*
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* Also works as advertised on my 845G.
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*/
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writel(readl(intel_private.registers+I830_HIC) | (1<<31),
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intel_private.registers+I830_HIC);
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while (readl(intel_private.registers+I830_HIC) & (1<<31)) {
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if (time_after(jiffies, timeout))
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break;
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udelay(50);
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}
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}
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static void i830_write_entry(dma_addr_t addr, unsigned int entry,
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@ -849,8 +837,6 @@ static int i830_setup(void)
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intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
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intel_i830_setup_flush();
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return 0;
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}
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