forked from luck/tmp_suning_uos_patched
[POWERPC] back up old school ipic.[hc] to arch/ppc
Keep from breaking 83xx arch/ppc build. Back up old school arch/powerpc/sysdev/ipic.[hc] to arch/ppc/syslib. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Kim Phillips
Paul Mackerras
parent
c85c41ad73
commit
bf4152dd7c
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@ -9,11 +9,11 @@ obj-$(CONFIG_BOOKE) += dcr.o
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obj-$(CONFIG_40x) += dcr.o
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obj-$(CONFIG_U3_DART) += dart_iommu.o
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obj-$(CONFIG_MMIO_NVRAM) += mmio_nvram.o
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obj-$(CONFIG_PPC_83xx) += ipic.o
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obj-$(CONFIG_FSL_SOC) += fsl_soc.o
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obj-$(CONFIG_PPC_TODC) += todc.o
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obj-$(CONFIG_TSI108_BRIDGE) += tsi108_pci.o tsi108_dev.o
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ifeq ($(CONFIG_PPC_MERGE),y)
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obj-$(CONFIG_PPC_I8259) += i8259.o
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endif
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obj-$(CONFIG_PPC_83xx) += ipic.o
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endif
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@ -93,7 +93,7 @@ obj-$(CONFIG_PCI) += pci_auto.o
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endif
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obj-$(CONFIG_RAPIDIO) += ppc85xx_rio.o
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obj-$(CONFIG_83xx) += ppc83xx_setup.o ppc_sys.o \
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mpc83xx_sys.o mpc83xx_devices.o
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mpc83xx_sys.o mpc83xx_devices.o ipic.o
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ifeq ($(CONFIG_83xx),y)
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obj-$(CONFIG_PCI) += pci_auto.o
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endif
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646
arch/ppc/syslib/ipic.c
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646
arch/ppc/syslib/ipic.c
Normal file
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@ -0,0 +1,646 @@
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/*
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* include/asm-ppc/ipic.c
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*
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* IPIC routines implementations.
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*
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* Copyright 2005 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/slab.h>
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#include <linux/stddef.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/sysdev.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/ipic.h>
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#include <asm/mpc83xx.h>
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#include "ipic.h"
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static struct ipic p_ipic;
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static struct ipic * primary_ipic;
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static struct ipic_info ipic_info[] = {
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[9] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 24,
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.prio_mask = 0,
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},
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[10] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 25,
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.prio_mask = 1,
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},
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[11] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 26,
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.prio_mask = 2,
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},
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[14] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 29,
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.prio_mask = 5,
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},
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[15] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 30,
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.prio_mask = 6,
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},
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[16] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_D,
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.force = IPIC_SIFCR_H,
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.bit = 31,
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.prio_mask = 7,
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},
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[17] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 1,
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.prio_mask = 5,
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},
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[18] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 2,
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.prio_mask = 6,
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},
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[19] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 3,
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.prio_mask = 7,
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},
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[20] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 4,
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.prio_mask = 4,
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},
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[21] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 5,
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.prio_mask = 5,
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},
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[22] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 6,
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.prio_mask = 6,
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},
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[23] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SEFCR,
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.bit = 7,
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.prio_mask = 7,
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},
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[32] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 0,
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.prio_mask = 0,
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},
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[33] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 1,
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.prio_mask = 1,
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},
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[34] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 2,
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.prio_mask = 2,
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},
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[35] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 3,
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.prio_mask = 3,
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},
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[36] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 4,
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.prio_mask = 4,
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},
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[37] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 5,
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.prio_mask = 5,
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},
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[38] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 6,
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.prio_mask = 6,
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},
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[39] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_H,
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.prio = IPIC_SIPRR_A,
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.force = IPIC_SIFCR_H,
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.bit = 7,
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.prio_mask = 7,
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},
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[48] = {
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.pend = IPIC_SEPNR,
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.mask = IPIC_SEMSR,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SEFCR,
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.bit = 0,
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.prio_mask = 4,
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},
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[64] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 0,
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.prio_mask = 0,
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},
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[65] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 1,
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.prio_mask = 1,
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},
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[66] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 2,
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.prio_mask = 2,
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},
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[67] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_A,
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.force = IPIC_SIFCR_L,
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.bit = 3,
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.prio_mask = 3,
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},
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[68] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 4,
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.prio_mask = 0,
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},
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[69] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 5,
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.prio_mask = 1,
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},
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[70] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 6,
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.prio_mask = 2,
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},
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[71] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = IPIC_SMPRR_B,
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.force = IPIC_SIFCR_L,
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.bit = 7,
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.prio_mask = 3,
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},
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[72] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 8,
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},
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[73] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 9,
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},
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[74] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 10,
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},
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[75] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 11,
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},
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[76] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 12,
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},
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[77] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 13,
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},
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[78] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 14,
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},
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[79] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 15,
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},
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[80] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 16,
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},
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[84] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 20,
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},
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[85] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 21,
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},
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[90] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 26,
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},
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[91] = {
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.pend = IPIC_SIPNR_H,
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.mask = IPIC_SIMSR_L,
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.prio = 0,
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.force = IPIC_SIFCR_L,
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.bit = 27,
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},
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};
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static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
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{
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out_be32(base + (reg >> 2), value);
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}
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static inline struct ipic * ipic_from_irq(unsigned int irq)
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{
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return primary_ipic;
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}
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static void ipic_enable_irq(unsigned int irq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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u32 temp;
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temp = ipic_read(ipic->regs, ipic_info[src].mask);
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temp |= (1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].mask, temp);
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}
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static void ipic_disable_irq(unsigned int irq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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u32 temp;
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temp = ipic_read(ipic->regs, ipic_info[src].mask);
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temp &= ~(1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].mask, temp);
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}
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static void ipic_disable_irq_and_ack(unsigned int irq)
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{
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struct ipic *ipic = ipic_from_irq(irq);
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unsigned int src = irq - ipic->irq_offset;
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u32 temp;
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ipic_disable_irq(irq);
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temp = ipic_read(ipic->regs, ipic_info[src].pend);
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temp |= (1 << (31 - ipic_info[src].bit));
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ipic_write(ipic->regs, ipic_info[src].pend, temp);
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}
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static void ipic_end_irq(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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ipic_enable_irq(irq);
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}
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struct hw_interrupt_type ipic = {
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.typename = " IPIC ",
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.enable = ipic_enable_irq,
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.disable = ipic_disable_irq,
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.ack = ipic_disable_irq_and_ack,
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.end = ipic_end_irq,
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};
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void __init ipic_init(phys_addr_t phys_addr,
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unsigned int flags,
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unsigned int irq_offset,
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unsigned char *senses,
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unsigned int senses_count)
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{
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||||
u32 i, temp = 0;
|
||||
|
||||
primary_ipic = &p_ipic;
|
||||
primary_ipic->regs = ioremap(phys_addr, MPC83xx_IPIC_SIZE);
|
||||
|
||||
primary_ipic->irq_offset = irq_offset;
|
||||
|
||||
ipic_write(primary_ipic->regs, IPIC_SICNR, 0x0);
|
||||
|
||||
/* default priority scheme is grouped. If spread mode is required
|
||||
* configure SICFR accordingly */
|
||||
if (flags & IPIC_SPREADMODE_GRP_A)
|
||||
temp |= SICFR_IPSA;
|
||||
if (flags & IPIC_SPREADMODE_GRP_D)
|
||||
temp |= SICFR_IPSD;
|
||||
if (flags & IPIC_SPREADMODE_MIX_A)
|
||||
temp |= SICFR_MPSA;
|
||||
if (flags & IPIC_SPREADMODE_MIX_B)
|
||||
temp |= SICFR_MPSB;
|
||||
|
||||
ipic_write(primary_ipic->regs, IPIC_SICNR, temp);
|
||||
|
||||
/* handle MCP route */
|
||||
temp = 0;
|
||||
if (flags & IPIC_DISABLE_MCP_OUT)
|
||||
temp = SERCR_MCPR;
|
||||
ipic_write(primary_ipic->regs, IPIC_SERCR, temp);
|
||||
|
||||
/* handle routing of IRQ0 to MCP */
|
||||
temp = ipic_read(primary_ipic->regs, IPIC_SEMSR);
|
||||
|
||||
if (flags & IPIC_IRQ0_MCP)
|
||||
temp |= SEMSR_SIRQ0;
|
||||
else
|
||||
temp &= ~SEMSR_SIRQ0;
|
||||
|
||||
ipic_write(primary_ipic->regs, IPIC_SEMSR, temp);
|
||||
|
||||
for (i = 0 ; i < NR_IPIC_INTS ; i++) {
|
||||
irq_desc[i+irq_offset].chip = &ipic;
|
||||
irq_desc[i+irq_offset].status = IRQ_LEVEL;
|
||||
}
|
||||
|
||||
temp = 0;
|
||||
for (i = 0 ; i < senses_count ; i++) {
|
||||
if ((senses[i] & IRQ_SENSE_MASK) == IRQ_SENSE_EDGE) {
|
||||
temp |= 1 << (15 - i);
|
||||
if (i != 0)
|
||||
irq_desc[i + irq_offset + MPC83xx_IRQ_EXT1 - 1].status = 0;
|
||||
else
|
||||
irq_desc[irq_offset + MPC83xx_IRQ_EXT0].status = 0;
|
||||
}
|
||||
}
|
||||
ipic_write(primary_ipic->regs, IPIC_SECNR, temp);
|
||||
|
||||
printk ("IPIC (%d IRQ sources, %d External IRQs) at %p\n", NR_IPIC_INTS,
|
||||
senses_count, primary_ipic->regs);
|
||||
}
|
||||
|
||||
int ipic_set_priority(unsigned int irq, unsigned int priority)
|
||||
{
|
||||
struct ipic *ipic = ipic_from_irq(irq);
|
||||
unsigned int src = irq - ipic->irq_offset;
|
||||
u32 temp;
|
||||
|
||||
if (priority > 7)
|
||||
return -EINVAL;
|
||||
if (src > 127)
|
||||
return -EINVAL;
|
||||
if (ipic_info[src].prio == 0)
|
||||
return -EINVAL;
|
||||
|
||||
temp = ipic_read(ipic->regs, ipic_info[src].prio);
|
||||
|
||||
if (priority < 4) {
|
||||
temp &= ~(0x7 << (20 + (3 - priority) * 3));
|
||||
temp |= ipic_info[src].prio_mask << (20 + (3 - priority) * 3);
|
||||
} else {
|
||||
temp &= ~(0x7 << (4 + (7 - priority) * 3));
|
||||
temp |= ipic_info[src].prio_mask << (4 + (7 - priority) * 3);
|
||||
}
|
||||
|
||||
ipic_write(ipic->regs, ipic_info[src].prio, temp);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ipic_set_highest_priority(unsigned int irq)
|
||||
{
|
||||
struct ipic *ipic = ipic_from_irq(irq);
|
||||
unsigned int src = irq - ipic->irq_offset;
|
||||
u32 temp;
|
||||
|
||||
temp = ipic_read(ipic->regs, IPIC_SICFR);
|
||||
|
||||
/* clear and set HPI */
|
||||
temp &= 0x7f000000;
|
||||
temp |= (src & 0x7f) << 24;
|
||||
|
||||
ipic_write(ipic->regs, IPIC_SICFR, temp);
|
||||
}
|
||||
|
||||
void ipic_set_default_priority(void)
|
||||
{
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC1_TX, 0);
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC1_RX, 1);
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC1_ERROR, 2);
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC2_TX, 3);
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC2_RX, 4);
|
||||
ipic_set_priority(MPC83xx_IRQ_TSEC2_ERROR, 5);
|
||||
ipic_set_priority(MPC83xx_IRQ_USB2_DR, 6);
|
||||
ipic_set_priority(MPC83xx_IRQ_USB2_MPH, 7);
|
||||
|
||||
ipic_set_priority(MPC83xx_IRQ_UART1, 0);
|
||||
ipic_set_priority(MPC83xx_IRQ_UART2, 1);
|
||||
ipic_set_priority(MPC83xx_IRQ_SEC2, 2);
|
||||
ipic_set_priority(MPC83xx_IRQ_IIC1, 5);
|
||||
ipic_set_priority(MPC83xx_IRQ_IIC2, 6);
|
||||
ipic_set_priority(MPC83xx_IRQ_SPI, 7);
|
||||
ipic_set_priority(MPC83xx_IRQ_RTC_SEC, 0);
|
||||
ipic_set_priority(MPC83xx_IRQ_PIT, 1);
|
||||
ipic_set_priority(MPC83xx_IRQ_PCI1, 2);
|
||||
ipic_set_priority(MPC83xx_IRQ_PCI2, 3);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT0, 4);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT1, 5);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT2, 6);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT3, 7);
|
||||
ipic_set_priority(MPC83xx_IRQ_RTC_ALR, 0);
|
||||
ipic_set_priority(MPC83xx_IRQ_MU, 1);
|
||||
ipic_set_priority(MPC83xx_IRQ_SBA, 2);
|
||||
ipic_set_priority(MPC83xx_IRQ_DMA, 3);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT4, 4);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT5, 5);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT6, 6);
|
||||
ipic_set_priority(MPC83xx_IRQ_EXT7, 7);
|
||||
}
|
||||
|
||||
void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq)
|
||||
{
|
||||
struct ipic *ipic = primary_ipic;
|
||||
u32 temp;
|
||||
|
||||
temp = ipic_read(ipic->regs, IPIC_SERMR);
|
||||
temp |= (1 << (31 - mcp_irq));
|
||||
ipic_write(ipic->regs, IPIC_SERMR, temp);
|
||||
}
|
||||
|
||||
void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq)
|
||||
{
|
||||
struct ipic *ipic = primary_ipic;
|
||||
u32 temp;
|
||||
|
||||
temp = ipic_read(ipic->regs, IPIC_SERMR);
|
||||
temp &= (1 << (31 - mcp_irq));
|
||||
ipic_write(ipic->regs, IPIC_SERMR, temp);
|
||||
}
|
||||
|
||||
u32 ipic_get_mcp_status(void)
|
||||
{
|
||||
return ipic_read(primary_ipic->regs, IPIC_SERMR);
|
||||
}
|
||||
|
||||
void ipic_clear_mcp_status(u32 mask)
|
||||
{
|
||||
ipic_write(primary_ipic->regs, IPIC_SERMR, mask);
|
||||
}
|
||||
|
||||
/* Return an interrupt vector or -1 if no interrupt is pending. */
|
||||
int ipic_get_irq(struct pt_regs *regs)
|
||||
{
|
||||
int irq;
|
||||
|
||||
irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & 0x7f;
|
||||
|
||||
if (irq == 0) /* 0 --> no irq is pending */
|
||||
irq = -1;
|
||||
|
||||
return irq;
|
||||
}
|
||||
|
||||
static struct sysdev_class ipic_sysclass = {
|
||||
set_kset_name("ipic"),
|
||||
};
|
||||
|
||||
static struct sys_device device_ipic = {
|
||||
.id = 0,
|
||||
.cls = &ipic_sysclass,
|
||||
};
|
||||
|
||||
static int __init init_ipic_sysfs(void)
|
||||
{
|
||||
int rc;
|
||||
|
||||
if (!primary_ipic->regs)
|
||||
return -ENODEV;
|
||||
printk(KERN_DEBUG "Registering ipic with sysfs...\n");
|
||||
|
||||
rc = sysdev_class_register(&ipic_sysclass);
|
||||
if (rc) {
|
||||
printk(KERN_ERR "Failed registering ipic sys class\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
rc = sysdev_register(&device_ipic);
|
||||
if (rc) {
|
||||
printk(KERN_ERR "Failed registering ipic sys device\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
subsys_initcall(init_ipic_sysfs);
|
||||
47
arch/ppc/syslib/ipic.h
Normal file
47
arch/ppc/syslib/ipic.h
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* IPIC private definitions and structure.
|
||||
*
|
||||
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
|
||||
*
|
||||
* Copyright 2005 Freescale Semiconductor, Inc
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
#ifndef __IPIC_H__
|
||||
#define __IPIC_H__
|
||||
|
||||
#include <asm/ipic.h>
|
||||
|
||||
#define MPC83xx_IPIC_SIZE (0x00100)
|
||||
|
||||
/* System Global Interrupt Configuration Register */
|
||||
#define SICFR_IPSA 0x00010000
|
||||
#define SICFR_IPSD 0x00080000
|
||||
#define SICFR_MPSA 0x00200000
|
||||
#define SICFR_MPSB 0x00400000
|
||||
|
||||
/* System External Interrupt Mask Register */
|
||||
#define SEMSR_SIRQ0 0x00008000
|
||||
|
||||
/* System Error Control Register */
|
||||
#define SERCR_MCPR 0x00000001
|
||||
|
||||
struct ipic {
|
||||
volatile u32 __iomem *regs;
|
||||
unsigned int irq_offset;
|
||||
};
|
||||
|
||||
struct ipic_info {
|
||||
u8 pend; /* pending register offset from base */
|
||||
u8 mask; /* mask register offset from base */
|
||||
u8 prio; /* priority register offset from base */
|
||||
u8 force; /* force register offset from base */
|
||||
u8 bit; /* register bit position (as per doc)
|
||||
bit mask = 1 << (31 - bit) */
|
||||
u8 prio_mask; /* priority mask value */
|
||||
};
|
||||
|
||||
#endif /* __IPIC_H__ */
|
||||
|
|
@ -69,9 +69,6 @@ enum ipic_mcp_irq {
|
|||
IPIC_MCP_MU = 7,
|
||||
};
|
||||
|
||||
extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
|
||||
unsigned int irq_offset,
|
||||
unsigned char *senses, unsigned int senses_count);
|
||||
extern int ipic_set_priority(unsigned int irq, unsigned int priority);
|
||||
extern void ipic_set_highest_priority(unsigned int irq);
|
||||
extern void ipic_set_default_priority(void);
|
||||
|
|
@ -79,7 +76,16 @@ extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
|
|||
extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
|
||||
extern u32 ipic_get_mcp_status(void);
|
||||
extern void ipic_clear_mcp_status(u32 mask);
|
||||
|
||||
#ifdef CONFIG_PPC_MERGE
|
||||
extern void ipic_init(struct device_node *node, unsigned int flags);
|
||||
extern unsigned int ipic_get_irq(struct pt_regs *regs);
|
||||
#else
|
||||
extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
|
||||
unsigned int irq_offset,
|
||||
unsigned char *senses, unsigned int senses_count);
|
||||
extern int ipic_get_irq(struct pt_regs *regs);
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_IPIC_H__ */
|
||||
#endif /* __KERNEL__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user