forked from luck/tmp_suning_uos_patched
Merge branch 'remotes/lorenzo/pci/mediatek'
- Use devm resource parser in mediatek (Honghui Zhang) - Remove unused mediatek "num-lanes" DT property (Honghui Zhang) * remotes/lorenzo/pci/mediatek: arm64: dts: mt7622: Remove un-used property for PCIe arm: dts: mt7623: Remove un-used property for PCIe dt-bindings: PCI: MediaTek: Remove un-used property PCI: mediatek: Remove un-used variant in struct mtk_pcie_port PCI: mediatek: Use devm_of_pci_get_host_bridge_resources() to parse DT
This commit is contained in:
Bjorn Helgaas
commit
c266b026ae
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@ -65,7 +65,6 @@ Required properties:
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explanation.
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- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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property is sufficient.
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- num-lanes: Number of lanes to use for this port.
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Examples for MT7623:
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@ -118,7 +117,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@1,0 {
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@ -129,7 +127,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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pcie@2,0 {
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@ -140,7 +137,6 @@ Examples for MT7623:
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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};
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};
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@ -172,7 +168,6 @@ Examples for MT2712:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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@ -191,7 +186,6 @@ Examples for MT2712:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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@ -245,7 +239,6 @@ Examples for MT7622:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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@ -264,7 +257,6 @@ Examples for MT7622:
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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@ -850,7 +850,6 @@ pcie@0,0 {
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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status = "disabled";
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};
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@ -862,7 +861,6 @@ pcie@1,0 {
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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status = "disabled";
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};
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@ -874,7 +872,6 @@ pcie@2,0 {
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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ranges;
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num-lanes = <1>;
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status = "disabled";
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};
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};
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@ -812,7 +812,6 @@ pcie0: pcie@0,0 {
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ranges;
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status = "disabled";
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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<0 0 0 2 &pcie_intc0 1>,
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@ -833,7 +832,6 @@ pcie1: pcie@1,0 {
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ranges;
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status = "disabled";
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num-lanes = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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<0 0 0 2 &pcie_intc1 1>,
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@ -161,7 +161,6 @@ struct mtk_pcie_soc {
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* @obff_ck: pointer to OBFF functional block operating clock
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* @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
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* @phy: pointer to PHY control block
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* @lane: lane count
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* @slot: port slot
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* @irq: GIC irq
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* @irq_domain: legacy INTx IRQ domain
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@ -182,7 +181,6 @@ struct mtk_pcie_port {
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struct clk *obff_ck;
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struct clk *pipe_ck;
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struct phy *phy;
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u32 lane;
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u32 slot;
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int irq;
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struct irq_domain *irq_domain;
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@ -197,29 +195,20 @@ struct mtk_pcie_port {
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* @dev: pointer to PCIe device
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* @base: IO mapped register base
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* @free_ck: free-run reference clock
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* @io: IO resource
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* @pio: PIO resource
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* @mem: non-prefetchable memory resource
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* @busn: bus range
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* @offset: IO / Memory offset
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* @ports: pointer to PCIe port information
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* @soc: pointer to SoC-dependent operations
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* @busnr: root bus number
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*/
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struct mtk_pcie {
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struct device *dev;
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void __iomem *base;
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struct clk *free_ck;
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struct resource io;
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struct resource pio;
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struct resource mem;
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struct resource busn;
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struct {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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struct list_head ports;
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const struct mtk_pcie_soc *soc;
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unsigned int busnr;
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};
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static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
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@ -904,12 +893,6 @@ static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
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if (!port)
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return -ENOMEM;
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err = of_property_read_u32(node, "num-lanes", &port->lane);
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if (err) {
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dev_err(dev, "missing num-lanes property\n");
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return err;
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}
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snprintf(name, sizeof(name), "port%d", slot);
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regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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port->base = devm_ioremap_resource(dev, regs);
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@ -1045,55 +1028,43 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node, *child;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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struct resource res;
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struct mtk_pcie_port *port, *tmp;
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struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct list_head *windows = &host->windows;
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struct resource_entry *win, *tmp_win;
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resource_size_t io_base;
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int err;
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if (of_pci_range_parser_init(&parser, node)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
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windows, &io_base);
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if (err)
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return err;
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for_each_of_pci_range(&parser, &range) {
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err = of_pci_range_to_resource(&range, node, &res);
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if (err < 0)
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return err;
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err = devm_request_pci_bus_resources(dev, windows);
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if (err < 0)
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return err;
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switch (res.flags & IORESOURCE_TYPE_BITS) {
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/* Get the I/O and memory ranges from DT */
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resource_list_for_each_entry_safe(win, tmp_win, windows) {
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switch (resource_type(win->res)) {
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case IORESOURCE_IO:
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pcie->offset.io = res.start - range.pci_addr;
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memcpy(&pcie->pio, &res, sizeof(res));
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pcie->pio.name = node->full_name;
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pcie->io.start = range.cpu_addr;
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pcie->io.end = range.cpu_addr + range.size - 1;
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pcie->io.flags = IORESOURCE_MEM;
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pcie->io.name = "I/O";
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memcpy(&res, &pcie->io, sizeof(res));
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err = devm_pci_remap_iospace(dev, win->res, io_base);
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if (err) {
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dev_warn(dev, "error %d: failed to map resource %pR\n",
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err, win->res);
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resource_list_destroy_entry(win);
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}
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break;
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case IORESOURCE_MEM:
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pcie->offset.mem = res.start - range.pci_addr;
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memcpy(&pcie->mem, &res, sizeof(res));
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memcpy(&pcie->mem, win->res, sizeof(*win->res));
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pcie->mem.name = "non-prefetchable";
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break;
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case IORESOURCE_BUS:
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pcie->busnr = win->res->start;
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break;
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}
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}
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err = of_pci_parse_bus_range(node, &pcie->busn);
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if (err < 0) {
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dev_err(dev, "failed to parse bus ranges property: %d\n", err);
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pcie->busn.name = node->name;
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pcie->busn.start = 0;
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pcie->busn.end = 0xff;
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pcie->busn.flags = IORESOURCE_BUS;
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}
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for_each_available_child_of_node(node, child) {
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int slot;
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@ -1125,28 +1096,6 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
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return 0;
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}
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static int mtk_pcie_request_resources(struct mtk_pcie *pcie)
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{
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struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
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struct list_head *windows = &host->windows;
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struct device *dev = pcie->dev;
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int err;
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pci_add_resource_offset(windows, &pcie->pio, pcie->offset.io);
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pci_add_resource_offset(windows, &pcie->mem, pcie->offset.mem);
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pci_add_resource(windows, &pcie->busn);
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err = devm_request_pci_bus_resources(dev, windows);
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if (err < 0)
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return err;
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err = devm_pci_remap_iospace(dev, &pcie->pio, pcie->io.start);
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if (err)
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return err;
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return 0;
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}
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static int mtk_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@ -1169,11 +1118,7 @@ static int mtk_pcie_probe(struct platform_device *pdev)
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if (err)
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return err;
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err = mtk_pcie_request_resources(pcie);
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if (err)
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goto put_resources;
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host->busnr = pcie->busn.start;
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host->busnr = pcie->busnr;
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host->dev.parent = pcie->dev;
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host->ops = pcie->soc->ops;
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host->map_irq = of_irq_parse_and_map_pci;
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