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dt-bindings: Changes for v5.5-rc1

Browse Source 
This contains various updates to device tree bindings and includes that
 are related to driver changes in other Tegra branches.
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Merge tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

dt-bindings: Changes for v5.5-rc1

This contains various updates to device tree bindings and includes that
are related to driver changes in other Tegra branches.

* tag 'tegra-for-5.5-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
  dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
  dt-bindings: memory: tegra30: Convert to Tegra124 YAML
  dt-bindings: regulator: Document regulators coupling of NVIDIA Tegra20/30 SoCs
  dt-bindings: clock: tegra: Rename SOR0_LVDS to SOR0_OUT

Link: https://lore.kernel.org/r/20191102144521.3863321-1-thierry.reding@gmail.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-03 17:19:26 -08:00
commit c267d9960c
7 changed files with 724 additions and 125 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

152
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 SoC Memory Controller
maintainers:
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
These are interleaved to provide high performance with the load shared across
two memory channels. The Tegra124 Memory Controller handles memory requests
from internal clients and arbitrates among them to allocate memory bandwidth
for DDR3L and LPDDR3 SDRAMs.
properties:
compatible:
const: nvidia,tegra124-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 1066000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"15.6.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_MISC1
- description: MC_EMEM_ARB_RING1_THROTTLE
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
additionalProperties: false
examples:
- |
memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};

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Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC External Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
The EMC interfaces with the off-chip SDRAM to service the request stream
sent from Memory Controller. The EMC also has various performance-affecting
settings beyond the obvious SDRAM configuration parameters and initialization
settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
LPDDR3, and DDR3.
properties:
compatible:
const: nvidia,tegra30-emc
reg:
maxItems: 1
clocks:
maxItems: 1
interrupts:
maxItems: 1
nvidia,memory-controller:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle of the Memory Controller node.
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emc-auto-cal-interval:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Pad calibration interval in microseconds.
minimum: 0
maximum: 2097151
nvidia,emc-mode-1:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 1.
nvidia,emc-mode-2:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 2.
nvidia,emc-mode-reset:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Mode Register 0.
nvidia,emc-zcal-cnt-long:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Number of EMC clocks to wait before issuing any commands after
sending ZCAL_MRW_CMD.
minimum: 0
maximum: 1023
nvidia,emc-cfg-dyn-self-ref:
type: boolean
description:
Dynamic self-refresh enabled.
nvidia,emc-cfg-periodic-qrst:
type: boolean
description:
FBIO "read" FIFO periodic resetting enabled.
nvidia,emc-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
EMC timing characterization data. These are the registers
(see section "18.13.2 EMC Registers" in the TRM) whose values
need to be specified, according to the board documentation.
items:
- description: EMC_RC
- description: EMC_RFC
- description: EMC_RAS
- description: EMC_RP
- description: EMC_R2W
- description: EMC_W2R
- description: EMC_R2P
- description: EMC_W2P
- description: EMC_RD_RCD
- description: EMC_WR_RCD
- description: EMC_RRD
- description: EMC_REXT
- description: EMC_WEXT
- description: EMC_WDV
- description: EMC_QUSE
- description: EMC_QRST
- description: EMC_QSAFE
- description: EMC_RDV
- description: EMC_REFRESH
- description: EMC_BURST_REFRESH_NUM
- description: EMC_PRE_REFRESH_REQ_CNT
- description: EMC_PDEX2WR
- description: EMC_PDEX2RD
- description: EMC_PCHG2PDEN
- description: EMC_ACT2PDEN
- description: EMC_AR2PDEN
- description: EMC_RW2PDEN
- description: EMC_TXSR
- description: EMC_TXSRDLL
- description: EMC_TCKE
- description: EMC_TFAW
- description: EMC_TRPAB
- description: EMC_TCLKSTABLE
- description: EMC_TCLKSTOP
- description: EMC_TREFBW
- description: EMC_QUSE_EXTRA
- description: EMC_FBIO_CFG6
- description: EMC_ODT_WRITE
- description: EMC_ODT_READ
- description: EMC_FBIO_CFG5
- description: EMC_CFG_DIG_DLL
- description: EMC_CFG_DIG_DLL_PERIOD
- description: EMC_DLL_XFORM_DQS0
- description: EMC_DLL_XFORM_DQS1
- description: EMC_DLL_XFORM_DQS2
- description: EMC_DLL_XFORM_DQS3
- description: EMC_DLL_XFORM_DQS4
- description: EMC_DLL_XFORM_DQS5
- description: EMC_DLL_XFORM_DQS6
- description: EMC_DLL_XFORM_DQS7
- description: EMC_DLL_XFORM_QUSE0
- description: EMC_DLL_XFORM_QUSE1
- description: EMC_DLL_XFORM_QUSE2
- description: EMC_DLL_XFORM_QUSE3
- description: EMC_DLL_XFORM_QUSE4
- description: EMC_DLL_XFORM_QUSE5
- description: EMC_DLL_XFORM_QUSE6
- description: EMC_DLL_XFORM_QUSE7
- description: EMC_DLI_TRIM_TXDQS0
- description: EMC_DLI_TRIM_TXDQS1
- description: EMC_DLI_TRIM_TXDQS2
- description: EMC_DLI_TRIM_TXDQS3
- description: EMC_DLI_TRIM_TXDQS4
- description: EMC_DLI_TRIM_TXDQS5
- description: EMC_DLI_TRIM_TXDQS6
- description: EMC_DLI_TRIM_TXDQS7
- description: EMC_DLL_XFORM_DQ0
- description: EMC_DLL_XFORM_DQ1
- description: EMC_DLL_XFORM_DQ2
- description: EMC_DLL_XFORM_DQ3
- description: EMC_XM2CMDPADCTRL
- description: EMC_XM2DQSPADCTRL2
- description: EMC_XM2DQPADCTRL2
- description: EMC_XM2CLKPADCTRL
- description: EMC_XM2COMPPADCTRL
- description: EMC_XM2VTTGENPADCTRL
- description: EMC_XM2VTTGENPADCTRL2
- description: EMC_XM2QUSEPADCTRL
- description: EMC_XM2DQSPADCTRL3
- description: EMC_CTT_TERM_CTRL
- description: EMC_ZCAL_INTERVAL
- description: EMC_ZCAL_WAIT_CNT
- description: EMC_MRS_WAIT_CNT
- description: EMC_AUTO_CAL_CONFIG
- description: EMC_CTT
- description: EMC_CTT_DURATION
- description: EMC_DYN_SELF_REF_CONTROL
- description: EMC_FBIO_SPARE
- description: EMC_CFG_RSV
required:
- clock-frequency
- nvidia,emc-auto-cal-interval
- nvidia,emc-mode-1
- nvidia,emc-mode-2
- nvidia,emc-mode-reset
- nvidia,emc-zcal-cnt-long
- nvidia,emc-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- nvidia,memory-controller
additionalProperties: false
examples:
- |
external-memory-controller@7000f400 {
compatible = "nvidia,tegra30-emc";
reg = <0x7000f400 0x400>;
interrupts = <0 78 4>;
clocks = <&tegra_car 57>;
nvidia,memory-controller = <&mc>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000b71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = <
0x00000020 /* EMC_RC */
0x0000006a /* EMC_RFC */
0x00000017 /* EMC_RAS */
0x00000007 /* EMC_RP */
0x00000005 /* EMC_R2W */
0x0000000c /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x00000011 /* EMC_W2P */
0x00000007 /* EMC_RD_RCD */
0x00000007 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000007 /* EMC_WDV */
0x0000000a /* EMC_QUSE */
0x00000009 /* EMC_QRST */
0x0000000b /* EMC_QSAFE */
0x00000011 /* EMC_RDV */
0x00001412 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x0000000e /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x0000000c /* EMC_AR2PDEN */
0x00000016 /* EMC_RW2PDEN */
0x00000072 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000005 /* EMC_TCKE */
0x00000015 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000006 /* EMC_TCLKSTABLE */
0x00000007 /* EMC_TCLKSTOP */
0x00001453 /* EMC_TREFBW */
0x0000000b /* EMC_QUSE_EXTRA */
0x00000006 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00005088 /* EMC_FBIO_CFG5 */
0xf00b0191 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00000008 /* EMC_DLL_XFORM_DQS0 */
0x00000008 /* EMC_DLL_XFORM_DQS1 */
0x00000008 /* EMC_DLL_XFORM_DQS2 */
0x00000008 /* EMC_DLL_XFORM_DQS3 */
0x0000000a /* EMC_DLL_XFORM_DQS4 */
0x0000000a /* EMC_DLL_XFORM_DQS5 */
0x0000000a /* EMC_DLL_XFORM_DQS6 */
0x0000000a /* EMC_DLL_XFORM_DQS7 */
0x00018000 /* EMC_DLL_XFORM_QUSE0 */
0x00018000 /* EMC_DLL_XFORM_QUSE1 */
0x00018000 /* EMC_DLL_XFORM_QUSE2 */
0x00018000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x0000000a /* EMC_DLL_XFORM_DQ0 */
0x0000000a /* EMC_DLL_XFORM_DQ1 */
0x0000000a /* EMC_DLL_XFORM_DQ2 */
0x0000000a /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x22220000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f501 /* EMC_XM2COMPPADCTRL */
0x07077404 /* EMC_XM2VTTGENPADCTRL */
0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x0c000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x0155000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff49 /* EMC_CFG_RSV */
>;
};
};
};

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Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
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@ -1,123 +0,0 @@
NVIDIA Tegra Memory Controller device tree bindings
===================================================
memory-controller node
----------------------
Required properties:
- compatible: Should be "nvidia,tegra<chip>-mc"
- reg: Physical base address and length of the controller's registers.
- clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
- clock-names: Must include the following entries:
- mc: the module's clock input
- interrupts: The interrupt outputs from the controller.
- #reset-cells : Should be 1. This cell represents memory client module ID.
The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
or in the TRM documentation.
Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
- #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
the SWGROUP of the master.
This device implements an IOMMU that complies with the generic IOMMU binding.
See ../iommu/iommu.txt for details.
emc-timings subnode
-------------------
The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
register PMC_STRAPPING_OPT_A).
Required properties for "emc-timings" nodes :
- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
timing subnode
--------------
Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
Required properties for timing nodes :
- clock-frequency : Should contain the memory clock rate in Hz.
- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
specified, according to the board documentation:
MC_EMEM_ARB_CFG
MC_EMEM_ARB_OUTSTANDING_REQ
MC_EMEM_ARB_TIMING_RCD
MC_EMEM_ARB_TIMING_RP
MC_EMEM_ARB_TIMING_RC
MC_EMEM_ARB_TIMING_RAS
MC_EMEM_ARB_TIMING_FAW
MC_EMEM_ARB_TIMING_RRD
MC_EMEM_ARB_TIMING_RAP2PRE
MC_EMEM_ARB_TIMING_WAP2PRE
MC_EMEM_ARB_TIMING_R2R
MC_EMEM_ARB_TIMING_W2W
MC_EMEM_ARB_TIMING_R2W
MC_EMEM_ARB_TIMING_W2R
MC_EMEM_ARB_DA_TURNS
MC_EMEM_ARB_DA_COVERS
MC_EMEM_ARB_MISC0
MC_EMEM_ARB_MISC1
MC_EMEM_ARB_RING1_THROTTLE
Example SoC include file:
/ {
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
clock-names = "mc";
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
#reset-cells = <1>;
};
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
};
};
Example board file:
/ {
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;
timing-12750000 {
clock-frequency = <12750000>;
nvidia,emem-configuration = <
0x40040001 /* MC_EMEM_ARB_CFG */
0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
0x00000001 /* MC_EMEM_ARB_TIMING_RP */
0x00000002 /* MC_EMEM_ARB_TIMING_RC */
0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
0x06030203 /* MC_EMEM_ARB_DA_TURNS */
0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
0x77e30303 /* MC_EMEM_ARB_MISC0 */
0x70000f03 /* MC_EMEM_ARB_MISC1 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};
};

167
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra30 SoC Memory Controller
maintainers:
- Dmitry Osipenko <digetx@gmail.com>
- Jon Hunter <jonathanh@nvidia.com>
- Thierry Reding <thierry.reding@gmail.com>
description: |
Tegra30 Memory Controller architecturally consists of the following parts:
Arbitration Domains, which can handle a single request or response per
clock from a group of clients. Typically, a system has a single Arbitration
Domain, but an implementation may divide the client space into multiple
Arbitration Domains to increase the effective system bandwidth.
Protocol Arbiter, which manage a related pool of memory devices. A system
may have a single Protocol Arbiter or multiple Protocol Arbiters.
Memory Crossbar, which routes request and responses between Arbitration
Domains and Protocol Arbiters. In the simplest version of the system, the
Memory Crossbar is just a pass through between a single Arbitration Domain
and a single Protocol Arbiter.
Global Resources, which include things like configuration registers which
are shared across the Memory Subsystem.
The Tegra30 Memory Controller handles memory requests from internal clients
and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
SDRAMs.
properties:
compatible:
const: nvidia,tegra30-mc
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: mc
interrupts:
maxItems: 1
"#reset-cells":
const: 1
"#iommu-cells":
const: 1
patternProperties:
"^emc-timings-[0-9]+$":
type: object
properties:
nvidia,ram-code:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Value of RAM_CODE this timing set is used for.
patternProperties:
"^timing-[0-9]+$":
type: object
properties:
clock-frequency:
description:
Memory clock rate in Hz.
minimum: 1000000
maximum: 900000000
nvidia,emem-configuration:
$ref: /schemas/types.yaml#/definitions/uint32-array
description: |
Values to be written to the EMEM register block. See section
"18.13.1 MC Registers" in the TRM.
items:
- description: MC_EMEM_ARB_CFG
- description: MC_EMEM_ARB_OUTSTANDING_REQ
- description: MC_EMEM_ARB_TIMING_RCD
- description: MC_EMEM_ARB_TIMING_RP
- description: MC_EMEM_ARB_TIMING_RC
- description: MC_EMEM_ARB_TIMING_RAS
- description: MC_EMEM_ARB_TIMING_FAW
- description: MC_EMEM_ARB_TIMING_RRD
- description: MC_EMEM_ARB_TIMING_RAP2PRE
- description: MC_EMEM_ARB_TIMING_WAP2PRE
- description: MC_EMEM_ARB_TIMING_R2R
- description: MC_EMEM_ARB_TIMING_W2W
- description: MC_EMEM_ARB_TIMING_R2W
- description: MC_EMEM_ARB_TIMING_W2R
- description: MC_EMEM_ARB_DA_TURNS
- description: MC_EMEM_ARB_DA_COVERS
- description: MC_EMEM_ARB_MISC0
- description: MC_EMEM_ARB_RING1_THROTTLE
required:
- clock-frequency
- nvidia,emem-configuration
additionalProperties: false
required:
- nvidia,ram-code
additionalProperties: false
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- "#reset-cells"
- "#iommu-cells"
additionalProperties: false
examples:
- |
memory-controller@7000f000 {
compatible = "nvidia,tegra30-mc";
reg = <0x7000f000 0x400>;
clocks = <&tegra_car 32>;
clock-names = "mc";
interrupts = <0 77 4>;
#iommu-cells = <1>;
#reset-cells = <1>;
emc-timings-1 {
nvidia,ram-code = <1>;
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emem-configuration = <
0x0000000a /* MC_EMEM_ARB_CFG */
0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
0x00000004 /* MC_EMEM_ARB_TIMING_RP */
0x00000010 /* MC_EMEM_ARB_TIMING_RC */
0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
0x08040202 /* MC_EMEM_ARB_DA_TURNS */
0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
>;
};
};
};

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Documentation/devicetree/bindings/regulator/nvidia,tegra-regulators-coupling.txt Normal file
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NVIDIA Tegra Regulators Coupling
================================
NVIDIA Tegra SoC's have a mandatory voltage-coupling between regulators.
Thus on Tegra20 there are 3 coupled regulators and on NVIDIA Tegra30
there are 2.
Tegra20 voltage coupling
------------------------
On Tegra20 SoC's there are 3 coupled regulators: CORE, RTC and CPU.
The CORE and RTC voltages shall be in a range of 170mV from each other
and they both shall be higher than the CPU voltage by at least 120mV.
Tegra30 voltage coupling
------------------------
On Tegra30 SoC's there are 2 coupled regulators: CORE and CPU. The CORE
and CPU voltages shall be in a range of 300mV from each other and CORE
voltage shall be higher than the CPU by N mV, where N depends on the CPU
voltage.
Required properties:
- nvidia,tegra-core-regulator: Boolean property that designates regulator
as the "Core domain" voltage regulator.
- nvidia,tegra-rtc-regulator: Boolean property that designates regulator
as the "RTC domain" voltage regulator.
- nvidia,tegra-cpu-regulator: Boolean property that designates regulator
as the "CPU domain" voltage regulator.
Example:
pmic {
regulators {
core_vdd_reg: core {
regulator-name = "vdd_core";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 550000>;
nvidia,tegra-core-regulator;
};
rtc_vdd_reg: rtc {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1300000>;
regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>;
regulator-coupled-max-spread = <170000 550000>;
nvidia,tegra-rtc-regulator;
};
cpu_vdd_reg: cpu {
regulator-name = "vdd_cpu";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1125000>;
regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>;
regulator-coupled-max-spread = <550000 550000>;
nvidia,tegra-cpu-regulator;
};
};
};

3
include/dt-bindings/clock/tegra124-car-common.h
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@ -337,7 +337,8 @@
#define TEGRA124_CLK_CLK_OUT_3_MUX 308
/* 309 */
/* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
#define TEGRA124_CLK_SOR0_OUT 311
#define TEGRA124_CLK_XUSB_SS_DIV2 312
#define TEGRA124_CLK_PLL_M_UD 313

3
include/dt-bindings/clock/tegra210-car.h
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@ -391,7 +391,8 @@
#define TEGRA210_CLK_CLK_OUT_3_MUX 358
#define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360
#define TEGRA210_CLK_SOR0_LVDS 361
#define TEGRA210_CLK_SOR0_LVDS 361 /* deprecated */
#define TEGRA210_CLK_SOR0_OUT 361
#define TEGRA210_CLK_XUSB_SS_DIV2 362
#define TEGRA210_CLK_PLL_M_UD 363