forked from luck/tmp_suning_uos_patched
microblaze/PCI: Remove stale pcibios_align_resource() comment
commit01cf9d524f
("microblaze/PCI: Support generic Xilinx AXI PCIe Host Bridge IP driver") and commitecf677c8dc
("PCI: Add a generic weak pcibios_align_resource()") first patched then removed pcibios_align_resource() from the microblaze architecture code but failed to remove the comment that was added to it. Remove it since it has now become stale and it is quite confusing. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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@ -597,19 +597,6 @@ static void pcibios_fixup_resources(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*
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* Why? Because some silly external IO cards only decode
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* the low 10 bits of the IO address. The 0x00-0xff region
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* is reserved for motherboard devices that decode all 16
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* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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int pcibios_add_device(struct pci_dev *dev)
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{
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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