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[PATCH] ppc32/8xx: Fix r3 trashing due to 8MB TLB page instantiation

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Instantiation of 8MB pages on the TLB cache for the kernel static
mapping trashes r3 register on !CONFIG_8xx_CPU6 configurations.
This ensures r3 gets saved and restored.

Signed-off-by: Marcelo Tosatti <marcelo@kvack.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Marcelo Tosatti 2006-05-05 17:09:29 -03:00 committed by Paul Mackerras
parent e4de00215c
commit c51e078f82
1 changed files with 0 additions and 4 deletions
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4
arch/ppc/kernel/head_8xx.S
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@ -355,9 +355,7 @@ InstructionTLBMiss:
. = 0x1200
DataStoreTLBMiss:
#ifdef CONFIG_8xx_CPU6
stw r3, 8(r0)
#endif
DO_8xx_CPU6(0x3f80, r3)
mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
mfcr r10
@ -417,9 +415,7 @@ DataStoreTLBMiss:
lwz r11, 0(r0)
mtcr r11
lwz r11, 4(r0)
#ifdef CONFIG_8xx_CPU6
lwz r3, 8(r0)
#endif
rfi
/* This is an instruction TLB error on the MPC8xx. This could be due