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perf jevents: Add some test events

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Add some test PMU events. The events are randomly chosen from x86 and
arm64 JSONs. The events include CPU and uncore events.

Signed-off-by: John Garry <john.garry@huawei.com>
Acked-by: Jiri Olsa <jolsa@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: James Clark <james.clark@arm.com>
Cc: Joakim Zhang <qiangqing.zhang@nxp.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linuxarm@huawei.com
Link: http://lore.kernel.org/lkml/1584442939-8911-2-git-send-email-john.garry@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
John Garry 2020-03-17 19:02:13 +08:00 committed by Arnaldo Carvalho de Melo
parent 7cd053d4cf
commit c52db67a74
3 changed files with 59 additions and 0 deletions
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12
tools/perf/pmu-events/arch/test/test_cpu/branch.json Normal file
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[
{
"EventName": "bp_l1_btb_correct",
"EventCode": "0x8a",
"BriefDescription": "L1 BTB Correction."
},
{
"EventName": "bp_l2_btb_correct",
"EventCode": "0x8b",
"BriefDescription": "L2 BTB Correction."
}
]

26
tools/perf/pmu-events/arch/test/test_cpu/other.json Normal file
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[
{
"EventCode": "0x6",
"Counter": "0,1",
"UMask": "0x80",
"EventName": "SEGMENT_REG_LOADS.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Number of segment register loads."
},
{
"EventCode": "0x9",
"Counter": "0,1",
"UMask": "0x20",
"EventName": "DISPATCH_BLOCKED.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
},
{
"EventCode": "0x3A",
"Counter": "0,1",
"UMask": "0x0",
"EventName": "EIST_TRANS",
"SampleAfterValue": "200000",
"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
}
]

21
tools/perf/pmu-events/arch/test/test_cpu/uncore.json Normal file
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[
{
"EventCode": "0x02",
"EventName": "uncore_hisi_ddrc.flux_wcmd",
"BriefDescription": "DDRC write commands",
"PublicDescription": "DDRC write commands",
"Unit": "hisi_sccl,ddrc"
},
{
"Unit": "CBO",
"EventCode": "0x22",
"UMask": "0x81",
"EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION",
"BriefDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"PublicDescription": "A cross-core snoop resulted from L3 Eviction which misses in some processor core.",
"Counter": "0,1",
"CounterMask": "0",
"Invert": "0",
"EdgeDetect": "0"
}
]