forked from luck/tmp_suning_uos_patched
crypto: inside-secure - irq balance
Balance the irqs of the inside secure driver over all available cpus. Currently all interrupts are handled by the first CPU. From my testing with IPSec AES-GCM 256 on my MCbin with 4 Cores I get a 50% speed increase: Before the patch: 99.73 Kpps With the patch: 151.25 Kpps Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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6914dd53eb
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c672041590
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@ -1135,11 +1135,12 @@ static irqreturn_t safexcel_irq_ring_thread(int irq, void *data)
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static int safexcel_request_ring_irq(void *pdev, int irqid,
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int is_pci_dev,
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int ring_id,
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irq_handler_t handler,
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irq_handler_t threaded_handler,
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struct safexcel_ring_irq_data *ring_irq_priv)
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{
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int ret, irq;
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int ret, irq, cpu;
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struct device *dev;
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if (IS_ENABLED(CONFIG_PCI) && is_pci_dev) {
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@ -1177,6 +1178,10 @@ static int safexcel_request_ring_irq(void *pdev, int irqid,
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return ret;
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}
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/* Set affinity */
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cpu = cpumask_local_spread(ring_id, NUMA_NO_NODE);
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irq_set_affinity_hint(irq, get_cpu_mask(cpu));
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return irq;
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}
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@ -1611,6 +1616,7 @@ static int safexcel_probe_generic(void *pdev,
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irq = safexcel_request_ring_irq(pdev,
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EIP197_IRQ_NUMBER(i, is_pci_dev),
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is_pci_dev,
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i,
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safexcel_irq_ring,
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safexcel_irq_ring_thread,
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ring_irq);
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@ -1619,6 +1625,7 @@ static int safexcel_probe_generic(void *pdev,
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return irq;
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}
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priv->ring[i].irq = irq;
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priv->ring[i].work_data.priv = priv;
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priv->ring[i].work_data.ring = i;
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INIT_WORK(&priv->ring[i].work_data.work,
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@ -1756,8 +1763,10 @@ static int safexcel_remove(struct platform_device *pdev)
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clk_disable_unprepare(priv->reg_clk);
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clk_disable_unprepare(priv->clk);
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for (i = 0; i < priv->config.rings; i++)
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for (i = 0; i < priv->config.rings; i++) {
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irq_set_affinity_hint(priv->ring[i].irq, NULL);
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destroy_workqueue(priv->ring[i].workqueue);
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}
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return 0;
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}
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@ -707,6 +707,9 @@ struct safexcel_ring {
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*/
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struct crypto_async_request *req;
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struct crypto_async_request *backlog;
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/* irq of this ring */
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int irq;
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};
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/* EIP integration context flags */
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