AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

[PATCH] ppc64: Updated Olof iommu updates 1/3

Browse Source 
Split out the implementation-specific parts of include/asm-ppc64/iommu.h
to separate include files (tce.h and dart.h respectively).

The generic iommu code really doesn't care about the underlying
implementation, and the TCE and DART stuff is completely different.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Olof Johansson 2005-09-20 13:45:41 +10:00 committed by Paul Mackerras
parent a21ead3239
commit c707ffcf3a
8 changed files with 118 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/ppc64/kernel/iSeries_iommu.c
View File

@ -30,6 +30,7 @@
#include <linux/list.h>
#include <asm/iommu.h>
#include <asm/tce.h>
#include <asm/machdep.h>
#include <asm/iSeries/HvCallXm.h>
#include <asm/iSeries/iSeries_pci.h>

1
arch/ppc64/kernel/iSeries_vio.c
View File

@ -14,6 +14,7 @@
#include <asm/vio.h>
#include <asm/iommu.h>
#include <asm/tce.h>
#include <asm/abs_addr.h>
#include <asm/page.h>
#include <asm/iSeries/vio.h>

1
arch/ppc64/kernel/pSeries_iommu.c
View File

@ -46,6 +46,7 @@
#include <asm/pSeries_reconfig.h>
#include <asm/systemcfg.h>
#include <asm/firmware.h>
#include <asm/tce.h>
#include "pci.h"
#define DBG(fmt...)

1
arch/ppc64/kernel/pSeries_vio.c
View File

@ -22,6 +22,7 @@
#include <asm/prom.h>
#include <asm/vio.h>
#include <asm/hvcall.h>
#include <asm/tce.h>
extern struct subsystem devices_subsys; /* needed for vio_find_name() */

29
arch/ppc64/kernel/u3_iommu.c
View File

@ -44,39 +44,12 @@
#include <asm/abs_addr.h>
#include <asm/cacheflush.h>
#include <asm/lmb.h>
#include <asm/dart.h>
#include "pci.h"
extern int iommu_force_on;
/* physical base of DART registers */
#define DART_BASE 0xf8033000UL
/* Offset from base to control register */
#define DARTCNTL 0
/* Offset from base to exception register */
#define DARTEXCP 0x10
/* Offset from base to TLB tag registers */
#define DARTTAG 0x1000
/* Control Register fields */
/* base address of table (pfn) */
#define DARTCNTL_BASE_MASK 0xfffff
#define DARTCNTL_BASE_SHIFT 12
#define DARTCNTL_FLUSHTLB 0x400
#define DARTCNTL_ENABLE 0x200
/* size of table in pages */
#define DARTCNTL_SIZE_MASK 0x1ff
#define DARTCNTL_SIZE_SHIFT 0
/* DART table fields */
#define DARTMAP_VALID 0x80000000
#define DARTMAP_RPNMASK 0x00ffffff
/* Physical base address and size of the DART table */
unsigned long dart_tablebase; /* exported to htab_initialize */
static unsigned long dart_tablesize;

55
include/asm-ppc64/dart.h Normal file
View File

@ -0,0 +1,55 @@
/*
* Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_DART_H
#define _ASM_DART_H
/* physical base of DART registers */
#define DART_BASE 0xf8033000UL
/* Offset from base to control register */
#define DARTCNTL 0
/* Offset from base to exception register */
#define DARTEXCP 0x10
/* Offset from base to TLB tag registers */
#define DARTTAG 0x1000
/* Control Register fields */
/* base address of table (pfn) */
#define DARTCNTL_BASE_MASK 0xfffff
#define DARTCNTL_BASE_SHIFT 12
#define DARTCNTL_FLUSHTLB 0x400
#define DARTCNTL_ENABLE 0x200
/* size of table in pages */
#define DARTCNTL_SIZE_MASK 0x1ff
#define DARTCNTL_SIZE_SHIFT 0
/* DART table fields */
#define DARTMAP_VALID 0x80000000
#define DARTMAP_RPNMASK 0x00ffffff
#endif

36
include/asm-ppc64/iommu.h
View File

@ -1,5 +1,4 @@
/*
* iommu.h
* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
* Rewrite, cleanup:
* Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
@ -29,44 +28,11 @@
/*
* IOMAP_MAX_ORDER defines the largest contiguous block
* of dma (tce) space we can get. IOMAP_MAX_ORDER = 13
* of dma space we can get. IOMAP_MAX_ORDER = 13
* allows up to 2**12 pages (4096 * 4096) = 16 MB
*/
#define IOMAP_MAX_ORDER 13
/*
* Tces come in two formats, one for the virtual bus and a different
* format for PCI
*/
#define TCE_VB 0
#define TCE_PCI 1
/* tce_entry
* Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
* abstracted so layout is irrelevant.
*/
union tce_entry {
unsigned long te_word;
struct {
unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
unsigned int tb_rsvd :6;
unsigned long tb_rpn :40; /* Real page number */
unsigned int tb_valid :1; /* Tce is valid (vb only) */
unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
unsigned int tb_pciwr :1; /* Write allowed (pci only) */
unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
} te_bits;
#define te_cacheBits te_bits.tb_cacheBits
#define te_rpn te_bits.tb_rpn
#define te_valid te_bits.tb_valid
#define te_allio te_bits.tb_allio
#define te_lpindex te_bits.tb_lpindex
#define te_pciwr te_bits.tb_pciwr
#define te_rdwr te_bits.tb_rdwr
};
struct iommu_table {
unsigned long it_busno; /* Bus number this table belongs to */
unsigned long it_size; /* Size of iommu table in entries */

57
include/asm-ppc64/tce.h Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
* Rewrite, cleanup:
* Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef _ASM_TCE_H
#define _ASM_TCE_H
/*
* Tces come in two formats, one for the virtual bus and a different
* format for PCI
*/
#define TCE_VB 0
#define TCE_PCI 1
/* tce_entry
* Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
* abstracted so layout is irrelevant.
*/
union tce_entry {
unsigned long te_word;
struct {
unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
unsigned int tb_rsvd :6;
unsigned long tb_rpn :40; /* Real page number */
unsigned int tb_valid :1; /* Tce is valid (vb only) */
unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
unsigned int tb_pciwr :1; /* Write allowed (pci only) */
unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
} te_bits;
#define te_cacheBits te_bits.tb_cacheBits
#define te_rpn te_bits.tb_rpn
#define te_valid te_bits.tb_valid
#define te_allio te_bits.tb_allio
#define te_lpindex te_bits.tb_lpindex
#define te_pciwr te_bits.tb_pciwr
#define te_rdwr te_bits.tb_rdwr
};
#endif