forked from luck/tmp_suning_uos_patched
drivers/rtc/rtc-pm8xxx.c: rework to support pm8941 rtc
Adds support for RTC device inside PM8941 PMIC. The RTC in this PMIC have two register spaces. Thus the rtc-pm8xxx is slightly reworked to reflect these differences. The register set for different PMIC chips are selected on DT compatible string base. [akpm@linux-foundation.org: coding-style fixes] [akpm@linux-foundation.org: simplify and fix locking in pm8xxx_rtc_set_time()] Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Josh Cartwright <joshc@codeaurora.org> Cc: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Stanimir Varbanov
Linus Torvalds
parent
6d50e60cd2
commit
c8d523a4b0
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@ -1320,7 +1320,7 @@ config RTC_DRV_LPC32XX
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config RTC_DRV_PM8XXX
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tristate "Qualcomm PMIC8XXX RTC"
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depends on MFD_PM8XXX
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depends on MFD_PM8XXX || MFD_SPMI_PMIC
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help
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If you say yes here you get support for the
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Qualcomm PMIC8XXX RTC.
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@ -27,21 +27,36 @@
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/* RTC_CTRL register bit fields */
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#define PM8xxx_RTC_ENABLE BIT(7)
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#define PM8xxx_RTC_ALARM_ENABLE BIT(1)
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#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
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#define NUM_8_BIT_RTC_REGS 0x4
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/**
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* struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
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* @ctrl: base address of control register
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* @write: base address of write register
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* @read: base address of read register
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* @alarm_ctrl: base address of alarm control register
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* @alarm_ctrl2: base address of alarm control2 register
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* @alarm_rw: base address of alarm read-write register
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* @alarm_en: alarm enable mask
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*/
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struct pm8xxx_rtc_regs {
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unsigned int ctrl;
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unsigned int write;
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unsigned int read;
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unsigned int alarm_ctrl;
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unsigned int alarm_ctrl2;
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unsigned int alarm_rw;
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unsigned int alarm_en;
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};
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/**
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* struct pm8xxx_rtc - rtc driver internal structure
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* @rtc: rtc device for this driver.
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* @regmap: regmap used to access RTC registers
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* @allow_set_time: indicates whether writing to the RTC is allowed
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* @rtc_alarm_irq: rtc alarm irq number.
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* @rtc_base: address of rtc control register.
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* @rtc_read_base: base address of read registers.
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* @rtc_write_base: base address of write registers.
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* @alarm_rw_base: base address of alarm registers.
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* @ctrl_reg: rtc control register.
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* @rtc_dev: device structure.
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* @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
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@ -51,11 +66,7 @@ struct pm8xxx_rtc {
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struct regmap *regmap;
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bool allow_set_time;
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int rtc_alarm_irq;
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int rtc_base;
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int rtc_read_base;
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int rtc_write_base;
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int alarm_rw_base;
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u8 ctrl_reg;
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const struct pm8xxx_rtc_regs *regs;
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struct device *rtc_dev;
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spinlock_t ctrl_reg_lock;
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};
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@ -71,8 +82,10 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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{
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int rc, i;
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unsigned long secs, irq_flags;
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u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
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u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
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unsigned int ctrl_reg;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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if (!rtc_dd->allow_set_time)
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return -EACCES;
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@ -87,30 +100,30 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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ctrl_reg = rtc_dd->ctrl_reg;
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if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
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rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
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if (rc)
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goto rtc_rw_fail;
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if (ctrl_reg & regs->alarm_en) {
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alarm_enabled = 1;
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
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ctrl_reg &= ~regs->alarm_en;
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
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if (rc) {
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dev_err(dev, "Write to RTC control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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} else {
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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}
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/* Write 0 to Byte[0] */
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0);
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rc = regmap_write(rtc_dd->regmap, regs->write, 0);
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if (rc) {
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dev_err(dev, "Write to RTC write data register failed\n");
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goto rtc_rw_fail;
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}
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/* Write Byte[1], Byte[2], Byte[3] */
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rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1,
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rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
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&value[1], sizeof(value) - 1);
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if (rc) {
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dev_err(dev, "Write to RTC write data register failed\n");
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@ -118,25 +131,23 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct rtc_time *tm)
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}
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/* Write Byte[0] */
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, value[0]);
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rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
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if (rc) {
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dev_err(dev, "Write to RTC write data register failed\n");
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goto rtc_rw_fail;
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}
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if (alarm_enabled) {
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ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
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ctrl_reg |= regs->alarm_en;
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
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if (rc) {
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dev_err(dev, "Write to RTC control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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}
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rtc_rw_fail:
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if (alarm_enabled)
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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return rc;
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}
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@ -148,9 +159,9 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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unsigned long secs;
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unsigned int reg;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
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value, sizeof(value));
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rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
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if (rc) {
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dev_err(dev, "RTC read data register failed\n");
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return rc;
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@ -160,14 +171,14 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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* Read the LSB again and check if there has been a carry over.
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* If there is, redo the read operation.
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*/
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rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_read_base, ®);
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rc = regmap_read(rtc_dd->regmap, regs->read, ®);
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if (rc < 0) {
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dev_err(dev, "RTC read data register failed\n");
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return rc;
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}
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if (unlikely(reg < value[0])) {
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rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->rtc_read_base,
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rc = regmap_bulk_read(rtc_dd->regmap, regs->read,
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value, sizeof(value));
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if (rc) {
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dev_err(dev, "RTC read data register failed\n");
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@ -195,9 +206,11 @@ static int pm8xxx_rtc_read_time(struct device *dev, struct rtc_time *tm)
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static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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int rc, i;
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u8 value[NUM_8_BIT_RTC_REGS], ctrl_reg;
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u8 value[NUM_8_BIT_RTC_REGS];
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unsigned int ctrl_reg;
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unsigned long secs, irq_flags;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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rtc_tm_to_time(&alarm->time, &secs);
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@ -208,28 +221,28 @@ static int pm8xxx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
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rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
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sizeof(value));
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if (rc) {
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dev_err(dev, "Write to RTC ALARM register failed\n");
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goto rtc_rw_fail;
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}
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ctrl_reg = rtc_dd->ctrl_reg;
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
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if (rc)
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goto rtc_rw_fail;
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if (alarm->enabled)
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ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
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ctrl_reg |= regs->alarm_en;
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else
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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ctrl_reg &= ~regs->alarm_en;
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
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if (rc) {
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dev_err(dev, "Write to RTC control register failed\n");
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dev_err(dev, "Write to RTC alarm control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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dev_dbg(dev, "Alarm Set for h:r:s=%d:%d:%d, d/m/y=%d/%d/%d\n",
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alarm->time.tm_hour, alarm->time.tm_min,
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alarm->time.tm_sec, alarm->time.tm_mday,
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@ -245,8 +258,9 @@ static int pm8xxx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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u8 value[NUM_8_BIT_RTC_REGS];
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unsigned long secs;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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rc = regmap_bulk_read(rtc_dd->regmap, rtc_dd->alarm_rw_base, value,
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rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
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sizeof(value));
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if (rc) {
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dev_err(dev, "RTC alarm time read failed\n");
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@ -276,25 +290,26 @@ static int pm8xxx_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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int rc;
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unsigned long irq_flags;
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struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
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u8 ctrl_reg;
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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unsigned int ctrl_reg;
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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ctrl_reg = rtc_dd->ctrl_reg;
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
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if (rc)
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goto rtc_rw_fail;
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if (enable)
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ctrl_reg |= PM8xxx_RTC_ALARM_ENABLE;
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ctrl_reg |= regs->alarm_en;
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else
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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ctrl_reg &= ~regs->alarm_en;
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
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if (rc) {
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dev_err(dev, "Write to RTC control register failed\n");
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goto rtc_rw_fail;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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rtc_rw_fail:
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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return rc;
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@ -311,6 +326,7 @@ static const struct rtc_class_ops pm8xxx_rtc_ops = {
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static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
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{
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struct pm8xxx_rtc *rtc_dd = dev_id;
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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unsigned int ctrl_reg;
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int rc;
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unsigned long irq_flags;
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@ -320,48 +336,100 @@ static irqreturn_t pm8xxx_alarm_trigger(int irq, void *dev_id)
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spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
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/* Clear the alarm enable bit */
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ctrl_reg = rtc_dd->ctrl_reg;
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ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
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if (rc) {
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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goto rtc_alarm_handled;
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}
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rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
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ctrl_reg &= ~regs->alarm_en;
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl, ctrl_reg);
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if (rc) {
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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dev_err(rtc_dd->rtc_dev,
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"Write to RTC control register failed\n");
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"Write to alarm control register failed\n");
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goto rtc_alarm_handled;
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}
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rtc_dd->ctrl_reg = ctrl_reg;
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spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
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/* Clear RTC alarm register */
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rc = regmap_read(rtc_dd->regmap,
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rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
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&ctrl_reg);
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rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl2, &ctrl_reg);
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if (rc) {
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dev_err(rtc_dd->rtc_dev,
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"RTC Alarm control register read failed\n");
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"RTC Alarm control2 register read failed\n");
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goto rtc_alarm_handled;
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}
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ctrl_reg &= ~PM8xxx_RTC_ALARM_CLEAR;
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rc = regmap_write(rtc_dd->regmap,
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rtc_dd->rtc_base + PM8XXX_ALARM_CTRL_OFFSET,
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ctrl_reg);
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ctrl_reg |= PM8xxx_RTC_ALARM_CLEAR;
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rc = regmap_write(rtc_dd->regmap, regs->alarm_ctrl2, ctrl_reg);
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if (rc)
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dev_err(rtc_dd->rtc_dev,
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"Write to RTC Alarm control register failed\n");
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"Write to RTC Alarm control2 register failed\n");
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rtc_alarm_handled:
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return IRQ_HANDLED;
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}
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static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
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{
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const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
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unsigned int ctrl_reg;
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int rc;
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/* Check if the RTC is on, else turn it on */
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rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
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if (rc)
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return rc;
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if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
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ctrl_reg |= PM8xxx_RTC_ENABLE;
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rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
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if (rc)
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return rc;
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}
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return 0;
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}
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static const struct pm8xxx_rtc_regs pm8921_regs = {
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.ctrl = 0x11d,
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.write = 0x11f,
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.read = 0x123,
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.alarm_rw = 0x127,
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.alarm_ctrl = 0x11d,
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.alarm_ctrl2 = 0x11e,
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.alarm_en = BIT(1),
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};
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static const struct pm8xxx_rtc_regs pm8058_regs = {
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.ctrl = 0x1e8,
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.write = 0x1ea,
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.read = 0x1ee,
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.alarm_rw = 0x1f2,
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.alarm_ctrl = 0x1e8,
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.alarm_ctrl2 = 0x1e9,
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.alarm_en = BIT(1),
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};
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static const struct pm8xxx_rtc_regs pm8941_regs = {
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.ctrl = 0x6046,
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.write = 0x6040,
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.read = 0x6048,
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.alarm_rw = 0x6140,
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.alarm_ctrl = 0x6146,
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.alarm_ctrl2 = 0x6148,
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.alarm_en = BIT(7),
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};
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/*
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* Hardcoded RTC bases until IORESOURCE_REG mapping is figured out
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*/
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static const struct of_device_id pm8xxx_id_table[] = {
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{ .compatible = "qcom,pm8921-rtc", .data = (void *) 0x11D },
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{ .compatible = "qcom,pm8058-rtc", .data = (void *) 0x1E8 },
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{ .compatible = "qcom,pm8921-rtc", .data = &pm8921_regs },
|
||||
{ .compatible = "qcom,pm8058-rtc", .data = &pm8058_regs },
|
||||
{ .compatible = "qcom,pm8941-rtc", .data = &pm8941_regs },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
|
||||
|
|
@ -369,7 +437,6 @@ MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
|
|||
static int pm8xxx_rtc_probe(struct platform_device *pdev)
|
||||
{
|
||||
int rc;
|
||||
unsigned int ctrl_reg;
|
||||
struct pm8xxx_rtc *rtc_dd;
|
||||
const struct of_device_id *match;
|
||||
|
||||
|
|
@ -399,33 +466,12 @@ static int pm8xxx_rtc_probe(struct platform_device *pdev)
|
|||
rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
|
||||
"allow-set-time");
|
||||
|
||||
rtc_dd->rtc_base = (long) match->data;
|
||||
|
||||
/* Setup RTC register addresses */
|
||||
rtc_dd->rtc_write_base = rtc_dd->rtc_base + PM8XXX_RTC_WRITE_OFFSET;
|
||||
rtc_dd->rtc_read_base = rtc_dd->rtc_base + PM8XXX_RTC_READ_OFFSET;
|
||||
rtc_dd->alarm_rw_base = rtc_dd->rtc_base + PM8XXX_ALARM_RW_OFFSET;
|
||||
|
||||
rtc_dd->regs = match->data;
|
||||
rtc_dd->rtc_dev = &pdev->dev;
|
||||
|
||||
/* Check if the RTC is on, else turn it on */
|
||||
rc = regmap_read(rtc_dd->regmap, rtc_dd->rtc_base, &ctrl_reg);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev, "RTC control register read failed!\n");
|
||||
rc = pm8xxx_rtc_enable(rtc_dd);
|
||||
if (rc)
|
||||
return rc;
|
||||
}
|
||||
|
||||
if (!(ctrl_reg & PM8xxx_RTC_ENABLE)) {
|
||||
ctrl_reg |= PM8xxx_RTC_ENABLE;
|
||||
rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
|
||||
if (rc) {
|
||||
dev_err(&pdev->dev,
|
||||
"Write to RTC control register failed\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
rtc_dd->ctrl_reg = ctrl_reg;
|
||||
|
||||
platform_set_drvdata(pdev, rtc_dd);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user