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dt-bindings: clock: tegra: Remove PMC clock IDs

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clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.

This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.

Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Sowjanya Komatineni 2020-01-13 23:24:26 -08:00 committed by Thierry Reding
parent 796705bcb1
commit c958540525
5 changed files with 29 additions and 29 deletions
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14
include/dt-bindings/clock/tegra114-car.h
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@ -272,10 +272,10 @@
#define TEGRA114_CLK_AUDIO3 242 #define TEGRA114_CLK_AUDIO3 242
#define TEGRA114_CLK_AUDIO4 243 #define TEGRA114_CLK_AUDIO4 243
#define TEGRA114_CLK_SPDIF 244 #define TEGRA114_CLK_SPDIF 244
#define TEGRA114_CLK_CLK_OUT_1 245 /* 245 */
#define TEGRA114_CLK_CLK_OUT_2 246 /* 246 */
#define TEGRA114_CLK_CLK_OUT_3 247 /* 247 */
#define TEGRA114_CLK_BLINK 248 /* 248 */
#define TEGRA114_CLK_OSC 249 #define TEGRA114_CLK_OSC 249
/* 250 */ /* 250 */
/* 251 */ /* 251 */
@ -335,9 +335,9 @@
#define TEGRA114_CLK_AUDIO3_MUX 303 #define TEGRA114_CLK_AUDIO3_MUX 303
#define TEGRA114_CLK_AUDIO4_MUX 304 #define TEGRA114_CLK_AUDIO4_MUX 304
#define TEGRA114_CLK_SPDIF_MUX 305 #define TEGRA114_CLK_SPDIF_MUX 305
#define TEGRA114_CLK_CLK_OUT_1_MUX 306 /* 306 */
#define TEGRA114_CLK_CLK_OUT_2_MUX 307 /* 307 */
#define TEGRA114_CLK_CLK_OUT_3_MUX 308 /* 308 */
#define TEGRA114_CLK_DSIA_MUX 309 #define TEGRA114_CLK_DSIA_MUX 309
#define TEGRA114_CLK_DSIB_MUX 310 #define TEGRA114_CLK_DSIB_MUX 310
#define TEGRA114_CLK_XUSB_SS_DIV2 311 #define TEGRA114_CLK_XUSB_SS_DIV2 311

14
include/dt-bindings/clock/tegra124-car-common.h
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@ -271,10 +271,10 @@
#define TEGRA124_CLK_AUDIO3 242 #define TEGRA124_CLK_AUDIO3 242
#define TEGRA124_CLK_AUDIO4 243 #define TEGRA124_CLK_AUDIO4 243
#define TEGRA124_CLK_SPDIF 244 #define TEGRA124_CLK_SPDIF 244
#define TEGRA124_CLK_CLK_OUT_1 245 /* 245 */
#define TEGRA124_CLK_CLK_OUT_2 246 /* 246 */
#define TEGRA124_CLK_CLK_OUT_3 247 /* 247 */
#define TEGRA124_CLK_BLINK 248 /* 248 */
#define TEGRA124_CLK_OSC 249 #define TEGRA124_CLK_OSC 249
/* 250 */ /* 250 */
/* 251 */ /* 251 */
@ -334,9 +334,9 @@
#define TEGRA124_CLK_AUDIO3_MUX 303 #define TEGRA124_CLK_AUDIO3_MUX 303
#define TEGRA124_CLK_AUDIO4_MUX 304 #define TEGRA124_CLK_AUDIO4_MUX 304
#define TEGRA124_CLK_SPDIF_MUX 305 #define TEGRA124_CLK_SPDIF_MUX 305
#define TEGRA124_CLK_CLK_OUT_1_MUX 306 /* 306 */
#define TEGRA124_CLK_CLK_OUT_2_MUX 307 /* 307 */
#define TEGRA124_CLK_CLK_OUT_3_MUX 308 /* 308 */
/* 309 */ /* 309 */
/* 310 */ /* 310 */
#define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */

2
include/dt-bindings/clock/tegra20-car.h
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@ -131,7 +131,7 @@
#define TEGRA20_CLK_CCLK 108 #define TEGRA20_CLK_CCLK 108
#define TEGRA20_CLK_HCLK 109 #define TEGRA20_CLK_HCLK 109
#define TEGRA20_CLK_PCLK 110 #define TEGRA20_CLK_PCLK 110
#define TEGRA20_CLK_BLINK 111 /* 111 */
#define TEGRA20_CLK_PLL_A 112 #define TEGRA20_CLK_PLL_A 112
#define TEGRA20_CLK_PLL_A_OUT0 113 #define TEGRA20_CLK_PLL_A_OUT0 113
#define TEGRA20_CLK_PLL_C 114 #define TEGRA20_CLK_PLL_C 114

14
include/dt-bindings/clock/tegra210-car.h
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@ -306,10 +306,10 @@
#define TEGRA210_CLK_AUDIO3 274 #define TEGRA210_CLK_AUDIO3 274
#define TEGRA210_CLK_AUDIO4 275 #define TEGRA210_CLK_AUDIO4 275
#define TEGRA210_CLK_SPDIF 276 #define TEGRA210_CLK_SPDIF 276
#define TEGRA210_CLK_CLK_OUT_1 277 /* 277 */
#define TEGRA210_CLK_CLK_OUT_2 278 /* 278 */
#define TEGRA210_CLK_CLK_OUT_3 279 /* 279 */
#define TEGRA210_CLK_BLINK 280 /* 280 */
#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
#define TEGRA210_CLK_SOR0_OUT 281 #define TEGRA210_CLK_SOR0_OUT 281
#define TEGRA210_CLK_SOR1_OUT 282 #define TEGRA210_CLK_SOR1_OUT 282
@ -388,9 +388,9 @@
#define TEGRA210_CLK_AUDIO3_MUX 353 #define TEGRA210_CLK_AUDIO3_MUX 353
#define TEGRA210_CLK_AUDIO4_MUX 354 #define TEGRA210_CLK_AUDIO4_MUX 354
#define TEGRA210_CLK_SPDIF_MUX 355 #define TEGRA210_CLK_SPDIF_MUX 355
#define TEGRA210_CLK_CLK_OUT_1_MUX 356 /* 356 */
#define TEGRA210_CLK_CLK_OUT_2_MUX 357 /* 357 */
#define TEGRA210_CLK_CLK_OUT_3_MUX 358 /* 358 */
#define TEGRA210_CLK_DSIA_MUX 359 #define TEGRA210_CLK_DSIA_MUX 359
#define TEGRA210_CLK_DSIB_MUX 360 #define TEGRA210_CLK_DSIB_MUX 360
/* 361 */ /* 361 */

14
include/dt-bindings/clock/tegra30-car.h
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@ -232,11 +232,11 @@
#define TEGRA30_CLK_AUDIO3 204 #define TEGRA30_CLK_AUDIO3 204
#define TEGRA30_CLK_AUDIO4 205 #define TEGRA30_CLK_AUDIO4 205
#define TEGRA30_CLK_SPDIF 206 #define TEGRA30_CLK_SPDIF 206
#define TEGRA30_CLK_CLK_OUT_1 207 /* (extern1) */ /* 207 */
#define TEGRA30_CLK_CLK_OUT_2 208 /* (extern2) */ /* 208 */
#define TEGRA30_CLK_CLK_OUT_3 209 /* (extern3) */ /* 209 */
#define TEGRA30_CLK_SCLK 210 #define TEGRA30_CLK_SCLK 210
#define TEGRA30_CLK_BLINK 211 /* 211 */
#define TEGRA30_CLK_CCLK_G 212 #define TEGRA30_CLK_CCLK_G 212
#define TEGRA30_CLK_CCLK_LP 213 #define TEGRA30_CLK_CCLK_LP 213
#define TEGRA30_CLK_TWD 214 #define TEGRA30_CLK_TWD 214
@ -262,9 +262,9 @@
/* 297 */ /* 297 */
/* 298 */ /* 298 */
/* 299 */ /* 299 */
#define TEGRA30_CLK_CLK_OUT_1_MUX 300 /* 300 */
#define TEGRA30_CLK_CLK_OUT_2_MUX 301 /* 301 */
#define TEGRA30_CLK_CLK_OUT_3_MUX 302 /* 302 */
#define TEGRA30_CLK_AUDIO0_MUX 303 #define TEGRA30_CLK_AUDIO0_MUX 303
#define TEGRA30_CLK_AUDIO1_MUX 304 #define TEGRA30_CLK_AUDIO1_MUX 304
#define TEGRA30_CLK_AUDIO2_MUX 305 #define TEGRA30_CLK_AUDIO2_MUX 305