forked from luck/tmp_suning_uos_patched
parport: parport_serial: Add WCH CH382L PCIe single parallel port support
The WCH CH382L PCIe adapter has 1 parallel port but unlike the similar WCH CH328 adapter there are no serial ports connected to it. Enable this adapter with the addition of the appropriate PCIe IDs and board support config. PCIe device ID 1c00:3050: 02:00.0 Serial controller: Device 1c00:3050 (rev 10) (prog-if 05 [16850]) Subsystem: Device 1c00:3050 Flags: fast devsel, IRQ 16 I/O ports at 2000 [size=256] Memory at d0000000 (32-bit, prefetchable) [size=32K] I/O ports at 2100 [size=4] Expansion ROM at b0200000 [disabled] [size=32K] Capabilities: [60] Power Management version 3 Capabilities: [68] MSI: Enable- Count=1/32 Maskable+ 64bit+ Capabilities: [80] Express Legacy Endpoint, MSI 00 Capabilities: [100] Advanced Error Reporting Kernel driver in use: parport_pc Kernel modules: parport_pc, parport_serial Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3ff10703c7
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c9a104e23c
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@ -58,6 +58,7 @@ enum parport_pc_pci_cards {
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timedia_9079c,
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wch_ch353_1s1p,
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wch_ch353_2s1p,
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wch_ch382_0s1p,
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wch_ch382_2s1p,
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brainboxes_5s1p,
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sunix_2s1p,
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@ -147,6 +148,7 @@ static struct parport_pc_pci cards[] = {
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/* timedia_9079c */ { 1, { { 2, 3 }, } },
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/* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
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/* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
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/* wch_ch382_0s1p*/ { 1, { { 2, -1}, } },
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/* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
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/* brainboxes_5s1p */ { 1, { { 3, -1 }, } },
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/* sunix_2s1p */ { 1, { { 3, -1 }, } },
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@ -252,6 +254,7 @@ static struct pci_device_id parport_serial_pci_tbl[] = {
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/* WCH CARDS */
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{ 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
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{ 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
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{ 0x1c00, 0x3050, 0x1c00, 0x3050, 0, 0, wch_ch382_0s1p},
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{ 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
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/* BrainBoxes PX272/PX306 MIO card */
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@ -494,6 +497,12 @@ static struct pciserial_board pci_parport_serial_boards[] = {
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.base_baud = 115200,
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.uart_offset = 8,
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},
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[wch_ch382_0s1p] = {
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.flags = FL_BASE0,
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.num_ports = 0,
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.base_baud = 115200,
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.uart_offset = 8,
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},
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[wch_ch382_2s1p] = {
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.flags = FL_BASE0,
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.num_ports = 2,
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