forked from luck/tmp_suning_uos_patched
ARM: SAMSUNG: Fix on s5p_gpio_[get,set]_drvstr
This patch fixes bug on gpio drive strength helper function. The offset should be like follwoing. - off = chip->chip.base - pin; + off = pin - chip->chip.base; In the s5p_gpio_get_drvstr(), the second line is unnecessary, because overwrite drvstr. drvstr = __raw_readl(reg); - drvstr = 0xffff & (0x3 << shift); And need 2bit masking before return the drvstr value. drvstr = drvstr >> shift; + drvstr &= 0x3; In the s5p_gpio_set_drvstr(), need relevant bit clear. tmp = __raw_readl(reg); + tmp &= ~(0x3 << shift); tmp |= drvstr << shift; Reported-by: Jaecheol Lee <jc.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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0770e5280e
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cbd2780fce
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@ -273,13 +273,13 @@ s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
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if (!chip)
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return -EINVAL;
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off = chip->chip.base - pin;
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off = pin - chip->chip.base;
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shift = off * 2;
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reg = chip->base + 0x0C;
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drvstr = __raw_readl(reg);
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drvstr = 0xffff & (0x3 << shift);
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drvstr = drvstr >> shift;
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drvstr &= 0x3;
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return (__force s5p_gpio_drvstr_t)drvstr;
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}
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@ -296,11 +296,12 @@ int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr)
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if (!chip)
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return -EINVAL;
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off = chip->chip.base - pin;
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off = pin - chip->chip.base;
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shift = off * 2;
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reg = chip->base + 0x0C;
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tmp = __raw_readl(reg);
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tmp &= ~(0x3 << shift);
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tmp |= drvstr << shift;
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__raw_writel(tmp, reg);
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