forked from luck/tmp_suning_uos_patched
bnx2x: Supporting new BCM8726 FW
Microcode download requires write of another register and read from "Limiting/LRM mode" register before setting Signed-off-by: Yaniv Rosner <yanivr@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -2258,6 +2258,11 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
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MDIO_PMA_REG_GEN_CTRL,
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MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
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bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_GEN_CTRL2,
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0x73A0);
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/* Clear soft reset.
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Will automatically reset micro-controller re-boot */
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bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
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@ -2265,8 +2270,8 @@ static void bnx2x_bcm8726_external_rom_boot(struct link_params *params)
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MDIO_PMA_REG_GEN_CTRL,
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MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
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/* wait for 100ms for microcode load */
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msleep(100);
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/* wait for 150ms for microcode load */
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msleep(150);
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/* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
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bnx2x_cl45_write(bp, port, ext_phy_type, ext_phy_addr,
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@ -2524,7 +2529,7 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
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u8 ext_phy_addr = ((params->ext_phy_config &
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >>
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PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT);
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u16 cur_limiting_mode;
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if (bnx2x_read_sfp_module_eeprom(params,
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SFP_EEPROM_OPTIONS_ADDR,
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SFP_EEPROM_OPTIONS_SIZE,
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@ -2535,6 +2540,16 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
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}
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limiting_mode = !(options[0] &
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SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK);
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bnx2x_cl45_read(bp, port,
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_ROM_VER2,
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&cur_limiting_mode);
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DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n",
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cur_limiting_mode);
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if (limiting_mode &&
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(module_type != SFP_MODULE_TYPE_PASSIVE_COPPER_CABLE)) {
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DP(NETIF_MSG_LINK,
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@ -2547,17 +2562,10 @@ static u8 bnx2x_bcm8726_set_limiting_mode(struct link_params *params,
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MDIO_PMA_REG_ROM_VER2,
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SFP_LIMITING_MODE_VALUE);
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} else { /* LRM mode ( default )*/
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u16 cur_limiting_mode;
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DP(NETIF_MSG_LINK, "Module options = 0x%x.Setting LRM MODE\n",
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options[0]);
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bnx2x_cl45_read(bp, port,
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PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
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ext_phy_addr,
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MDIO_PMA_DEVAD,
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MDIO_PMA_REG_ROM_VER2,
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&cur_limiting_mode);
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/* Changing to LRM mode takes quite few seconds.
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So do it only if current mode is limiting
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( default is LRM )*/
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@ -5843,6 +5843,7 @@ Theotherbitsarereservedandshouldbezero*/
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#define MDIO_PMA_REG_ROM_VER2 0xca1a
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#define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
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#define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
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#define MDIO_PMA_REG_GEN_CTRL2 0xca1e
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#define MDIO_PMA_REG_MISC_CTRL0 0xca23
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#define MDIO_PMA_REG_LRM_MODE 0xca3f
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#define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
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