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DMA: Freescale: unify register access methods

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Methods of accessing DMA controller registers are inconsistent, some registers
are accessed by DMA_IN/OUT directly, while others are accessed by functions
get/set_* which are wrappers of DMA_IN/OUT, and even for the BCR register, it
is read by get_bcr but written by DMA_OUT.
This patch unifies the inconsistent methods, all registers are accessed by
get/set_* now.

Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Hongbo Zhang 2014-04-18 16:17:45 +08:00 committed by Vinod Koul
parent cf7f7a2b4b
commit ccdce9a041
1 changed files with 33 additions and 19 deletions
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52
drivers/dma/fsldma.c
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@ -61,6 +61,16 @@ static u32 get_sr(struct fsldma_chan *chan)
return DMA_IN(chan, &chan->regs->sr, 32); return DMA_IN(chan, &chan->regs->sr, 32);
} }
static void set_mr(struct fsldma_chan *chan, u32 val)
{
DMA_OUT(chan, &chan->regs->mr, val, 32);
}
static u32 get_mr(struct fsldma_chan *chan)
{
return DMA_IN(chan, &chan->regs->mr, 32);
}
static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
{ {
DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
@ -71,6 +81,11 @@ static dma_addr_t get_cdar(struct fsldma_chan *chan)
return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
} }
static void set_bcr(struct fsldma_chan *chan, u32 val)
{
DMA_OUT(chan, &chan->regs->bcr, val, 32);
}
static u32 get_bcr(struct fsldma_chan *chan) static u32 get_bcr(struct fsldma_chan *chan)
{ {
return DMA_IN(chan, &chan->regs->bcr, 32); return DMA_IN(chan, &chan->regs->bcr, 32);
@ -135,7 +150,7 @@ static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
static void dma_init(struct fsldma_chan *chan) static void dma_init(struct fsldma_chan *chan)
{ {
/* Reset the channel */ /* Reset the channel */
DMA_OUT(chan, &chan->regs->mr, 0, 32); set_mr(chan, 0);
switch (chan->feature & FSL_DMA_IP_MASK) { switch (chan->feature & FSL_DMA_IP_MASK) {
case FSL_DMA_IP_85XX: case FSL_DMA_IP_85XX:
@ -144,16 +159,15 @@ static void dma_init(struct fsldma_chan *chan)
* EOLNIE - End of links interrupt enable * EOLNIE - End of links interrupt enable
* BWC - Bandwidth sharing among channels * BWC - Bandwidth sharing among channels
*/ */
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
| FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); | FSL_DMA_MR_EOLNIE);
break; break;
case FSL_DMA_IP_83XX: case FSL_DMA_IP_83XX:
/* Set the channel to below modes: /* Set the channel to below modes:
* EOTIE - End-of-transfer interrupt enable * EOTIE - End-of-transfer interrupt enable
* PRC_RM - PCI read multiple * PRC_RM - PCI read multiple
*/ */
DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
| FSL_DMA_MR_PRC_RM, 32);
break; break;
} }
} }
@ -175,10 +189,10 @@ static void dma_start(struct fsldma_chan *chan)
{ {
u32 mode; u32 mode;
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
DMA_OUT(chan, &chan->regs->bcr, 0, 32); set_bcr(chan, 0);
mode |= FSL_DMA_MR_EMP_EN; mode |= FSL_DMA_MR_EMP_EN;
} else { } else {
mode &= ~FSL_DMA_MR_EMP_EN; mode &= ~FSL_DMA_MR_EMP_EN;
@ -191,7 +205,7 @@ static void dma_start(struct fsldma_chan *chan)
mode |= FSL_DMA_MR_CS; mode |= FSL_DMA_MR_CS;
} }
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
} }
static void dma_halt(struct fsldma_chan *chan) static void dma_halt(struct fsldma_chan *chan)
@ -200,7 +214,7 @@ static void dma_halt(struct fsldma_chan *chan)
int i; int i;
/* read the mode register */ /* read the mode register */
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
/* /*
* The 85xx controller supports channel abort, which will stop * The 85xx controller supports channel abort, which will stop
@ -209,14 +223,14 @@ static void dma_halt(struct fsldma_chan *chan)
*/ */
if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
mode |= FSL_DMA_MR_CA; mode |= FSL_DMA_MR_CA;
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
mode &= ~FSL_DMA_MR_CA; mode &= ~FSL_DMA_MR_CA;
} }
/* stop the DMA controller */ /* stop the DMA controller */
mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
/* wait for the DMA controller to become idle */ /* wait for the DMA controller to become idle */
for (i = 0; i < 100; i++) { for (i = 0; i < 100; i++) {
@ -245,7 +259,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
{ {
u32 mode; u32 mode;
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
switch (size) { switch (size) {
case 0: case 0:
@ -259,7 +273,7 @@ static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
break; break;
} }
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
} }
/** /**
@ -277,7 +291,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
{ {
u32 mode; u32 mode;
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
switch (size) { switch (size) {
case 0: case 0:
@ -291,7 +305,7 @@ static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
break; break;
} }
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
} }
/** /**
@ -312,10 +326,10 @@ static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
BUG_ON(size > 1024); BUG_ON(size > 1024);
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
mode |= (__ilog2(size) << 24) & 0x0f000000; mode |= (__ilog2(size) << 24) & 0x0f000000;
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
} }
/** /**
@ -889,9 +903,9 @@ static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
u32 mode; u32 mode;
mode = DMA_IN(chan, &chan->regs->mr, 32); mode = get_mr(chan);
mode &= ~FSL_DMA_MR_CS; mode &= ~FSL_DMA_MR_CS;
DMA_OUT(chan, &chan->regs->mr, mode, 32); set_mr(chan, mode);
} }
/* /*