forked from luck/tmp_suning_uos_patched
ARM: tegra: add low level code for Tegra114 cluster power down
When the CPU cluster power down, the vGIC is powered down too. The flow controller needs to monitor the legacy interrupt controller to wake up CPU. So setting up the appropriate wake up event in flow controller. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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@ -28,6 +28,8 @@
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#define FLOW_CTRL_SCLK_RESUME (1 << 27)
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#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
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#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
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#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
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#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
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#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
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#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
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#define FLOW_CTRL_CPU0_CSR 0x8
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@ -175,8 +175,12 @@ tegra30_enter_sleep:
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orr r0, r0, #FLOW_CTRL_CSR_ENABLE
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str r0, [r6, r2]
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
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cmp r10, #TEGRA30
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mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
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orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
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orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
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orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
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cpu_to_halt_reg r2, r1
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str r0, [r6, r2]
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dsb
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