forked from luck/tmp_suning_uos_patched
Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
This commit is contained in:
Linus Torvalds
commit
cdf2c465f0
@ -91,16 +91,17 @@ ENTRY(vhpt_miss)
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* (the "original") TLB miss, which may either be caused by an instruction
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* fetch or a data access (or non-access).
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*
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* What we do here is normal TLB miss handing for the _original_ miss, followed
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* by inserting the TLB entry for the virtual page table page that the VHPT
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* walker was attempting to access. The latter gets inserted as long
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* as both L1 and L2 have valid mappings for the faulting address.
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* The TLB entry for the original miss gets inserted only if
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* the L3 entry indicates that the page is present.
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* What we do here is normal TLB miss handing for the _original_ miss,
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* followed by inserting the TLB entry for the virtual page table page
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* that the VHPT walker was attempting to access. The latter gets
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* inserted as long as page table entry above pte level have valid
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* mappings for the faulting address. The TLB entry for the original
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* miss gets inserted only if the pte entry indicates that the page is
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* present.
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*
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* do_page_fault gets invoked in the following cases:
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* - the faulting virtual address uses unimplemented address bits
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* - the faulting virtual address has no L1, L2, or L3 mapping
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* - the faulting virtual address has no valid page table mapping
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*/
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mov r16=cr.ifa // get address that caused the TLB miss
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#ifdef CONFIG_HUGETLB_PAGE
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@ -126,7 +127,7 @@ ENTRY(vhpt_miss)
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#endif
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;;
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cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
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shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
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shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
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;;
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(p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
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@ -137,38 +138,38 @@ ENTRY(vhpt_miss)
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(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
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(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
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;;
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
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cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
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#ifdef CONFIG_PGTABLE_4
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shr.u r28=r22,PUD_SHIFT // shift L2 index into position
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shr.u r28=r22,PUD_SHIFT // shift pud index into position
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#else
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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shr.u r18=r22,PMD_SHIFT // shift pmd index into position
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#endif
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;;
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ld8 r17=[r17] // fetch the L1 entry (may be 0)
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ld8 r17=[r17] // get *pgd (may be 0)
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;;
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(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
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(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
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#ifdef CONFIG_PGTABLE_4
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dep r28=r28,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
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;;
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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(p7) ld8 r29=[r28] // fetch the L2 entry (may be 0)
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shr.u r18=r22,PMD_SHIFT // shift pmd index into position
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(p7) ld8 r29=[r28] // get *pud (may be 0)
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;;
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(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was L2 entry NULL?
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dep r17=r18,r29,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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(p7) cmp.eq.or.andcm p6,p7=r29,r0 // was pud_present(*pud) == NULL?
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dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
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#else
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
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#endif
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;;
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(p7) ld8 r20=[r17] // fetch the L3 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
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(p7) ld8 r20=[r17] // get *pmd (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift pte index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L3 entry NULL?
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dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
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(p7) cmp.eq.or.andcm p6,p7=r20,r0 // was pmd_present(*pmd) == NULL?
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dep r21=r19,r20,3,(PAGE_SHIFT-3) // r21=pte_offset(pmd,addr)
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;;
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(p7) ld8 r18=[r21] // read the L4 PTE
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mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
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(p7) ld8 r18=[r21] // read *pte
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mov r19=cr.isr // cr.isr bit 32 tells us if this is an insn miss
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;;
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(p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
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mov r22=cr.iha // get the VHPT address that caused the TLB miss
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@ -202,25 +203,33 @@ ENTRY(vhpt_miss)
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dv_serialize_data
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/*
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* Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
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* Re-check pagetable entry. If they changed, we may have received a ptc.g
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* between reading the pagetable and the "itc". If so, flush the entry we
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* inserted and retry.
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* inserted and retry. At this point, we have:
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*
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* r28 = equivalent of pud_offset(pgd, ifa)
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* r17 = equivalent of pmd_offset(pud, ifa)
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* r21 = equivalent of pte_offset(pmd, ifa)
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*
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* r29 = *pud
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* r20 = *pmd
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* r18 = *pte
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*/
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ld8 r25=[r21] // read L4 entry again
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ld8 r26=[r17] // read L3 PTE again
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ld8 r25=[r21] // read *pte again
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ld8 r26=[r17] // read *pmd again
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#ifdef CONFIG_PGTABLE_4
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ld8 r18=[r28] // read L2 entry again
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ld8 r19=[r28] // read *pud again
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#endif
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cmp.ne p6,p7=r0,r0
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;;
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cmp.ne.or.andcm p6,p7=r26,r20 // did L3 entry change
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cmp.ne.or.andcm p6,p7=r26,r20 // did *pmd change
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#ifdef CONFIG_PGTABLE_4
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cmp.ne.or.andcm p6,p7=r29,r18 // did L4 PTE change
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cmp.ne.or.andcm p6,p7=r19,r29 // did *pud change
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#endif
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mov r27=PAGE_SHIFT<<2
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;;
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(p6) ptc.l r22,r27 // purge PTE page translation
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(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L4 PTE change
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(p7) cmp.ne.or.andcm p6,p7=r25,r18 // did *pte change
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;;
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(p6) ptc.l r16,r27 // purge translation
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#endif
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@ -235,19 +244,19 @@ END(vhpt_miss)
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ENTRY(itlb_miss)
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DBG_FAULT(1)
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/*
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* The ITLB handler accesses the L3 PTE via the virtually mapped linear
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* The ITLB handler accesses the PTE via the virtually mapped linear
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* page table. If a nested TLB miss occurs, we switch into physical
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* mode, walk the page table, and then re-execute the L3 PTE read
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* and go on normally after that.
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* mode, walk the page table, and then re-execute the PTE read and
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* go on normally after that.
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*/
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mov r16=cr.ifa // get virtual address
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mov r29=b0 // save b0
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mov r31=pr // save predicates
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.itlb_fault:
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mov r17=cr.iha // get virtual address of L3 PTE
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mov r17=cr.iha // get virtual address of PTE
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movl r30=1f // load nested fault continuation point
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;;
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1: ld8 r18=[r17] // read L3 PTE
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1: ld8 r18=[r17] // read *pte
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;;
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mov b0=r29
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tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
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@ -262,7 +271,7 @@ ENTRY(itlb_miss)
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*/
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dv_serialize_data
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ld8 r19=[r17] // read L3 PTE again and see if same
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ld8 r19=[r17] // read *pte again and see if same
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mov r20=PAGE_SHIFT<<2 // setup page size for purge
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;;
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cmp.ne p7,p0=r18,r19
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@ -279,19 +288,19 @@ END(itlb_miss)
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ENTRY(dtlb_miss)
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DBG_FAULT(2)
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/*
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* The DTLB handler accesses the L3 PTE via the virtually mapped linear
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* The DTLB handler accesses the PTE via the virtually mapped linear
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* page table. If a nested TLB miss occurs, we switch into physical
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* mode, walk the page table, and then re-execute the L3 PTE read
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* and go on normally after that.
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* mode, walk the page table, and then re-execute the PTE read and
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* go on normally after that.
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*/
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mov r16=cr.ifa // get virtual address
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mov r29=b0 // save b0
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mov r31=pr // save predicates
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dtlb_fault:
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mov r17=cr.iha // get virtual address of L3 PTE
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mov r17=cr.iha // get virtual address of PTE
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movl r30=1f // load nested fault continuation point
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;;
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1: ld8 r18=[r17] // read L3 PTE
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1: ld8 r18=[r17] // read *pte
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;;
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mov b0=r29
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tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
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@ -306,7 +315,7 @@ dtlb_fault:
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*/
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dv_serialize_data
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ld8 r19=[r17] // read L3 PTE again and see if same
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ld8 r19=[r17] // read *pte again and see if same
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mov r20=PAGE_SHIFT<<2 // setup page size for purge
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;;
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cmp.ne p7,p0=r18,r19
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@ -420,7 +429,7 @@ ENTRY(nested_dtlb_miss)
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* r30: continuation address
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* r31: saved pr
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*
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* Output: r17: physical address of L3 PTE of faulting address
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* Output: r17: physical address of PTE of faulting address
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* r29: saved b0
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* r30: continuation address
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* r31: saved pr
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@ -450,33 +459,33 @@ ENTRY(nested_dtlb_miss)
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(p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
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(p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
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;;
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
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(p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
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(p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
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cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
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#ifdef CONFIG_PGTABLE_4
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shr.u r18=r22,PUD_SHIFT // shift L2 index into position
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shr.u r18=r22,PUD_SHIFT // shift pud index into position
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#else
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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shr.u r18=r22,PMD_SHIFT // shift pmd index into position
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#endif
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;;
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ld8 r17=[r17] // fetch the L1 entry (may be 0)
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ld8 r17=[r17] // get *pgd (may be 0)
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;;
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(p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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(p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
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;;
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#ifdef CONFIG_PGTABLE_4
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(p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
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shr.u r18=r22,PMD_SHIFT // shift L3 index into position
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(p7) ld8 r17=[r17] // get *pud (may be 0)
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shr.u r18=r22,PMD_SHIFT // shift pmd index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
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dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
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;;
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#endif
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(p7) ld8 r17=[r17] // fetch the L3 entry (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift L4 index into position
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(p7) ld8 r17=[r17] // get *pmd (may be 0)
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shr.u r19=r22,PAGE_SHIFT // shift pte index into position
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;;
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L3 entry NULL?
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dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L4 page table entry
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(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
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dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
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(p6) br.cond.spnt page_fault
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mov b0=r30
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br.sptk.many b0 // return to continuation point
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