forked from luck/tmp_suning_uos_patched
hwmon-vid: Fix AMD K8 VID decoding
Not all AMD K8 have 6 VID pins, contrary to what was assumed in
commit 116d0486bd
. This commit broke
support of older CPU models which have only 5 VID pins:
http://bugzilla.kernel.org/show_bug.cgi?id=11329
We need two entries in the hwmon-vid table, one for 5-bit VID models
(K8 revision <= E) and one for 6-bit VID models (K8 revision >= F).
This fixes bug #11329.
Signed-off-by: Jean Delvare <khali@linux-fr.org>
Acked-by: Frank Myhr <fmyhr@fhmtech.com>
Tested-by: Jean-Luc Coulon <jean.luc.coulon@gmail.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
parent
cd98a04a59
commit
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@ -37,13 +37,21 @@
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* For VRD 10.0 and up, "VRD x.y Design Guide",
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* available at http://developer.intel.com/.
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*
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* AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559,
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* AMD Athlon 64 and AMD Opteron Processors, AMD Publication 26094,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/26094.PDF
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* Table 74. VID Code Voltages
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* This corresponds to an arbitrary VRM code of 24 in the functions below.
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* These CPU models (K8 revision <= E) have 5 VID pins. See also:
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* Revision Guide for AMD Athlon 64 and AMD Opteron Processors, AMD Publication 25759,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25759.pdf
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*
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* AMD NPT Family 0Fh Processors, AMD Publication 32559,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf
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* Table 71. VID Code Voltages
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* AMD Opteron processors don't follow the Intel specifications.
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* I'm going to "make up" 2.4 as the spec number for the Opterons.
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* No good reason just a mnemonic for the 24x Opteron processor
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* series.
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* This corresponds to an arbitrary VRM code of 25 in the functions below.
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* These CPU models (K8 revision >= F) have 6 VID pins. See also:
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* Revision Guide for AMD NPT Family 0Fh Processors, AMD Publication 33610,
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* http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
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*
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* The 17 specification is in fact Intel Mobile Voltage Positioning -
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* (IMVP-II). You can find more information in the datasheet of Max1718
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@ -95,7 +103,12 @@ int vid_from_reg(int val, u8 vrm)
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return 0;
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return((1600000 - (val - 2) * 6250 + 500) / 1000);
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case 24: /* AMD NPT 0Fh (Athlon64 & Opteron) */
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case 24: /* Athlon64 & Opteron */
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val &= 0x1f;
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if (val == 0x1f)
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return 0;
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/* fall through */
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case 25: /* AMD NPT 0Fh */
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val &= 0x3f;
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return (val < 32) ? 1550 - 25 * val
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: 775 - (25 * (val - 31)) / 2;
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@ -157,11 +170,16 @@ struct vrm_model {
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#ifdef CONFIG_X86
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/* the stepping parameter is highest acceptable stepping for current line */
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/*
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* The stepping parameter is highest acceptable stepping for current line.
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* The model match must be exact for 4-bit values. For model values 0x10
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* and above (extended model), all models below the parameter will match.
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*/
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static struct vrm_model vrm_models[] = {
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{X86_VENDOR_AMD, 0x6, ANY, ANY, 90}, /* Athlon Duron etc */
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{X86_VENDOR_AMD, 0xF, ANY, ANY, 24}, /* Athlon 64, Opteron and above VRM 24 */
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{X86_VENDOR_AMD, 0xF, 0x3F, ANY, 24}, /* Athlon 64, Opteron */
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{X86_VENDOR_AMD, 0xF, ANY, ANY, 25}, /* NPT family 0Fh */
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{X86_VENDOR_INTEL, 0x6, 0x9, ANY, 13}, /* Pentium M (130 nm) */
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{X86_VENDOR_INTEL, 0x6, 0xB, ANY, 85}, /* Tualatin */
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{X86_VENDOR_INTEL, 0x6, 0xD, ANY, 13}, /* Pentium M (90 nm) */
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@ -189,6 +207,8 @@ static u8 find_vrm(u8 eff_family, u8 eff_model, u8 eff_stepping, u8 vendor)
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if (vrm_models[i].vendor==vendor)
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if ((vrm_models[i].eff_family==eff_family)
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&& ((vrm_models[i].eff_model==eff_model) ||
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(vrm_models[i].eff_model >= 0x10 &&
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eff_model <= vrm_models[i].eff_model) ||
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(vrm_models[i].eff_model==ANY)) &&
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(eff_stepping <= vrm_models[i].eff_stepping))
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return vrm_models[i].vrm_type;
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