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imx-dt-3.7

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- All imx53 board files are removed by the equal device tree support
 - The efikamx board files are removed to ease device tree migration
 - Remove dummy pinctrl state by setting up pinctrl in device tree
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Merge tag 'imx-dt-3.7' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

- All imx53 board files are removed by the equal device tree support
- The efikamx board files are removed to ease device tree migration
- Remove dummy pinctrl state by setting up pinctrl in device tree

* tag 'imx-dt-3.7' of git://git.linaro.org/people/shawnguo/linux-2.6: (28 commits)
  ARM: imx6q-sabrelite: Rename 'pinctrl_gpio_hog'
  ARM: imx51: decouple device tree boot from board files
  ARM: imx51: build in pinctrl support
  ARM: dts: imx51-babbage: add pinctrl settings
  ARM: imx53: remove unneeded files and functions
  ARM: imx53: support device tree boot only
  ARM: imx53: decouple device tree boot from board files
  ARM: imx53: build in pinctrl support
  ARM: dts: imx53-smd: add pinctrl settings
  ARM: dts: imx53-evk: add pinctrl settings
  ARM: dts: imx53-ard: add pinctrl settings
  ARM: dts: imx53-qsb: add pinctrl settings
  ARM: imx6q: remove dummy pinctrl state
  ARM: dts: imx6q-sabresd: add pinctrl settings
  ARM: dts: imx6q-arm2: add pinctrl for uart and enet
  ARM: dts: imx6q-sabrelite: add pinctrl for usdhc and enet
  ARM: dts: imx6q: sort iomuxc sub-nodes in name
  ARM: dts: imx6q: name iomuxc sub-nodes following pin function
  ARM: dts: imx6q: improve indentation for fsl,pins
  ARM: efikamx: remove Genesi Efika MX platform files from the tree
  ...

Resolved trivial context conflict in arch/arm/boot/dts/imx51-babbage.dts
This commit is contained in:
Olof Johansson 2012-09-12 23:17:11 -07:00
commit cecb9a1e4d
32 changed files with 794 additions and 3809 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/imx27-phytec-phycore.dts
View File

@ -23,10 +23,6 @@ memory {
soc {
aipi@10000000 { /* aipi */
wdog@10002000 {
status = "okay";
};
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";

1
arch/arm/boot/dts/imx27.dtsi
View File

@ -62,7 +62,6 @@ wdog@10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x4000>;
interrupts = <27>;
status = "disabled";
};
uart1: serial@1000a000 {

44
arch/arm/boot/dts/imx51-babbage.dts
View File

@ -25,23 +25,31 @@ soc {
aips@70000000 { /* aips-1 */
spba@70000000 {
esdhc@70004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
fsl,cd-controller;
fsl,wp-controller;
status = "okay";
};
esdhc@70008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
cd-gpios = <&gpio1 6 0>;
wp-gpios = <&gpio1 5 0>;
status = "okay";
};
uart3: serial@7000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@70010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 0>, <&gpio4 25 0>;
status = "okay";
@ -169,31 +177,43 @@ ssi2: ssi@70014000 {
};
};
wdog@73f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc-babbage";
reg = <0x73fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
694 0x20d5 /* MX51_PAD_GPIO1_0__SD1_CD */
697 0x20d5 /* MX51_PAD_GPIO1_1__SD1_WP */
737 0x100 /* MX51_PAD_GPIO1_5__GPIO1_5 */
740 0x100 /* MX51_PAD_GPIO1_6__GPIO1_6 */
121 0x5 /* MX51_PAD_EIM_A27__GPIO2_21 */
402 0x85 /* MX51_PAD_CSPI1_SS0__GPIO4_24 */
405 0x85 /* MX51_PAD_CSPI1_SS1__GPIO4_25 */
>;
};
};
};
uart1: serial@73fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
fsl,uart-has-rtscts;
status = "okay";
};
uart2: serial@73fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@80000000 { /* aips-2 */
sdma@83fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
i2c@83fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
@ -206,10 +226,14 @@ sgtl5000: codec@0a {
};
audmux@83fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@83fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "mii";
status = "okay";
};

146
arch/arm/boot/dts/imx51.dtsi
View File

@ -130,6 +130,34 @@ esdhc@70024000 { /* ESDHC4 */
};
};
usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
usb@73f80200 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
usb@73f80400 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
usb@73f80600 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
status = "disabled";
};
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;
@ -174,7 +202,6 @@ wdog@73f98000 { /* WDOG1 */
compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
reg = <0x73f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@73f9c000 { /* WDOG2 */
@ -184,6 +211,122 @@ wdog@73f9c000 { /* WDOG2 */
status = "disabled";
};
iomuxc@73fa8000 {
compatible = "fsl,imx51-iomuxc";
reg = <0x73fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */
386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */
389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */
391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */
134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */
146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */
152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */
158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */
165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */
206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */
213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */
293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */
298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */
225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */
231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */
237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */
243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */
250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */
255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */
260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */
394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */
409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */
669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */
672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */
678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */
684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */
691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */
707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */
710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */
712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */
715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */
719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */
454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */
416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */
418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */
420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */
426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */
59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */
65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */
49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */
>;
};
};
};
uart1: serial@73fbc000 {
compatible = "fsl,imx51-uart", "fsl,imx21-uart";
reg = <0x73fbc000 0x4000>;
@ -219,6 +362,7 @@ sdma@83fb0000 {
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
reg = <0x83fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
};
cspi@83fc0000 {

59
arch/arm/boot/dts/imx53-ard.dts
View File

@ -25,31 +25,66 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-ard";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1077 0x80000000 /* MX53_PAD_GPIO_1__GPIO1_1 */
1085 0x80000000 /* MX53_PAD_GPIO_9__GPIO1_9 */
486 0x80000000 /* MX53_PAD_EIM_EB3__GPIO2_31 */
739 0x80000000 /* MX53_PAD_GPIO_10__GPIO4_0 */
218 0x80000000 /* MX53_PAD_DISP0_DAT16__GPIO5_10 */
226 0x80000000 /* MX53_PAD_DISP0_DAT17__GPIO5_11 */
233 0x80000000 /* MX53_PAD_DISP0_DAT18__GPIO5_12 */
241 0x80000000 /* MX53_PAD_DISP0_DAT19__GPIO5_13 */
429 0x80000000 /* MX53_PAD_EIM_D16__EMI_WEIM_D_16 */
435 0x80000000 /* MX53_PAD_EIM_D17__EMI_WEIM_D_17 */
441 0x80000000 /* MX53_PAD_EIM_D18__EMI_WEIM_D_18 */
448 0x80000000 /* MX53_PAD_EIM_D19__EMI_WEIM_D_19 */
456 0x80000000 /* MX53_PAD_EIM_D20__EMI_WEIM_D_20 */
464 0x80000000 /* MX53_PAD_EIM_D21__EMI_WEIM_D_21 */
471 0x80000000 /* MX53_PAD_EIM_D22__EMI_WEIM_D_22 */
477 0x80000000 /* MX53_PAD_EIM_D23__EMI_WEIM_D_23 */
492 0x80000000 /* MX53_PAD_EIM_D24__EMI_WEIM_D_24 */
500 0x80000000 /* MX53_PAD_EIM_D25__EMI_WEIM_D_25 */
508 0x80000000 /* MX53_PAD_EIM_D26__EMI_WEIM_D_26 */
516 0x80000000 /* MX53_PAD_EIM_D27__EMI_WEIM_D_27 */
524 0x80000000 /* MX53_PAD_EIM_D28__EMI_WEIM_D_28 */
532 0x80000000 /* MX53_PAD_EIM_D29__EMI_WEIM_D_29 */
540 0x80000000 /* MX53_PAD_EIM_D30__EMI_WEIM_D_30 */
548 0x80000000 /* MX53_PAD_EIM_D31__EMI_WEIM_D_31 */
637 0x80000000 /* MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 */
642 0x80000000 /* MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 */
647 0x80000000 /* MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 */
652 0x80000000 /* MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 */
657 0x80000000 /* MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 */
662 0x80000000 /* MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 */
667 0x80000000 /* MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 */
611 0x80000000 /* MX53_PAD_EIM_OE__EMI_WEIM_OE */
616 0x80000000 /* MX53_PAD_EIM_RW__EMI_WEIM_RW */
607 0x80000000 /* MX53_PAD_EIM_CS1__EMI_WEIM_CS_1 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
};
};
eim-cs1@f4000000 {

39
arch/arm/boot/dts/imx53-evk.dts
View File

@ -25,12 +25,16 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio3 14 0>;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
@ -56,32 +60,45 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-evk";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
705 0x80000000 /* MX53_PAD_EIM_DA14__GPIO3_14 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
pmic: mc13892@08 {
@ -96,6 +113,8 @@ codec: sgtl5000@0a {
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";

42
arch/arm/boot/dts/imx53-qsb.dts
View File

@ -25,6 +25,8 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
status = "okay";
};
@ -35,32 +37,46 @@ ssi2: ssi@50014000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
cd-gpios = <&gpio3 11 0>;
wp-gpios = <&gpio3 12 0>;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-qsb";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1071 0x80000000 /* MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK */
1141 0x80000000 /* MX53_PAD_GPIO_8__GPIO1_8 */
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
693 0x80000000 /* MX53_PAD_EIM_DA11__GPIO3_11 */
697 0x80000000 /* MX53_PAD_EIM_DA12__GPIO3_12 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
873 0x80000000 /* MX53_PAD_PATA_DA_1__GPIO7_7 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
sgtl5000: codec@0a {
@ -72,6 +88,8 @@ sgtl5000: codec@0a {
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
@ -158,10 +176,14 @@ ldo13 {
};
audmux@63fd0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "okay";
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";

46
arch/arm/boot/dts/imx53-smd.dts
View File

@ -25,22 +25,30 @@ soc {
aips@50000000 { /* AIPS1 */
spba@50000000 {
esdhc@50004000 { /* ESDHC1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio3 13 0>;
wp-gpios = <&gpio4 11 0>;
status = "okay";
};
esdhc@50008000 { /* ESDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
non-removable;
status = "okay";
};
uart3: serial@5000c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "okay";
};
ecspi@50010000 { /* ECSPI1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1>;
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
@ -72,35 +80,49 @@ partition@40000 {
};
esdhc@50020000 { /* ESDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3_1>;
non-removable;
status = "okay";
};
};
wdog@53f98000 { /* WDOG1 */
status = "okay";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc-smd";
reg = <0x53fa8000 0x4000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
982 0x80000000 /* MX53_PAD_PATA_DATA14__GPIO2_14 */
989 0x80000000 /* MX53_PAD_PATA_DATA15__GPIO2_15 */
424 0x80000000 /* MX53_PAD_EIM_EB2__GPIO2_30 */
701 0x80000000 /* MX53_PAD_EIM_DA13__GPIO3_13 */
449 0x80000000 /* MX53_PAD_EIM_D19__GPIO3_19 */
43 0x80000000 /* MX53_PAD_KEY_ROW2__GPIO4_11 */
868 0x80000000 /* MX53_PAD_PATA_DA_0__GPIO7_6 */
>;
};
};
};
uart1: serial@53fbc000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
uart2: serial@53fc0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
};
aips@60000000 { /* AIPS2 */
sdma@63fb0000 {
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
i2c@63fc4000 { /* I2C2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_1>;
status = "okay";
codec: sgtl5000@0a {
@ -120,6 +142,8 @@ touchkey: mpr121@5a {
};
i2c@63fc8000 { /* I2C1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_1>;
status = "okay";
accelerometer: mma8450@1c {
@ -139,6 +163,8 @@ pmic: dialog@48 {
};
ethernet@63fec000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";

199
arch/arm/boot/dts/imx53.dtsi
View File

@ -135,6 +135,34 @@ esdhc@50024000 { /* ESDHC4 */
};
};
usb@53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
status = "disabled";
};
usb@53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
status = "disabled";
};
usb@53f80400 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
status = "disabled";
};
usb@53f80600 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
status = "disabled";
};
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
@ -179,7 +207,6 @@ wdog@53f98000 { /* WDOG1 */
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
reg = <0x53f98000 0x4000>;
interrupts = <58>;
status = "disabled";
};
wdog@53f9c000 { /* WDOG2 */
@ -189,6 +216,161 @@ wdog@53f9c000 { /* WDOG2 */
status = "disabled";
};
iomuxc@53fa8000 {
compatible = "fsl,imx53-iomuxc";
reg = <0x53fa8000 0x4000>;
audmux {
pinctrl_audmux_1: audmuxgrp-1 {
fsl,pins = <
10 0x80000000 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */
17 0x80000000 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */
23 0x80000000 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */
30 0x80000000 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */
>;
};
};
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
820 0x80000000 /* MX53_PAD_FEC_MDC__FEC_MDC */
779 0x80000000 /* MX53_PAD_FEC_MDIO__FEC_MDIO */
786 0x80000000 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */
791 0x80000000 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */
796 0x80000000 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */
799 0x80000000 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */
804 0x80000000 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */
808 0x80000000 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */
811 0x80000000 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */
816 0x80000000 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
433 0x80000000 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */
439 0x80000000 /* MX53_PAD_EIM_D17__ECSPI1_MISO */
445 0x80000000 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp-1 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
pinctrl_esdhc1_2: esdhc1grp-2 {
fsl,pins = <
995 0x1d5 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */
1000 0x1d5 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */
1010 0x1d5 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */
1024 0x1d5 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */
941 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */
948 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */
955 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */
962 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */
1005 0x1d5 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */
1018 0x1d5 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */
>;
};
};
esdhc2 {
pinctrl_esdhc2_1: esdhc2grp-1 {
fsl,pins = <
1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */
1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */
1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */
1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */
1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */
1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */
>;
};
};
esdhc3 {
pinctrl_esdhc3_1: esdhc3grp-1 {
fsl,pins = <
943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */
950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */
957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */
964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */
893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */
900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */
906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */
912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */
857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */
863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
333 0xc0000000 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */
341 0xc0000000 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */
>;
};
};
i2c2 {
pinctrl_i2c2_1: i2c2grp-1 {
fsl,pins = <
61 0xc0000000 /* MX53_PAD_KEY_ROW3__I2C2_SDA */
53 0xc0000000 /* MX53_PAD_KEY_COL3__I2C2_SCL */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */
354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */
>;
};
pinctrl_uart1_2: uart1grp-2 {
fsl,pins = <
828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */
832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */
836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */
>;
};
};
uart3 {
pinctrl_uart3_1: uart3grp-1 {
fsl,pins = <
884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */
888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */
875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */
880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */
>;
};
};
};
uart1: serial@53fbc000 {
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
reg = <0x53fbc000 0x4000>;
@ -203,6 +385,20 @@ uart2: serial@53fc0000 {
status = "disabled";
};
can1: can@53fc8000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fc8000 0x4000>;
interrupts = <82>;
status = "disabled";
};
can2: can@53fcc000 {
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
reg = <0x53fcc000 0x4000>;
interrupts = <83>;
status = "disabled";
};
gpio5: gpio@53fdc000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53fdc000 0x4000>;
@ -277,6 +473,7 @@ sdma@63fb0000 {
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
reg = <0x63fb0000 0x4000>;
interrupts = <6>;
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
};
cspi@63fc0000 {

21
arch/arm/boot/dts/imx6q-arm2.dts
View File

@ -28,8 +28,27 @@ gpmi-nand@00112000 {
status = "disabled"; /* gpmi nand conflicts with SD */
};
aips-bus@02000000 { /* AIPS1 */
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
176 0x80000000 /* MX6Q_PAD_EIM_D25__GPIO_3_25 */
1363 0x80000000 /* MX6Q_PAD_NANDF_CS0__GPIO_6_11 */
1369 0x80000000 /* MX6Q_PAD_NANDF_CS1__GPIO_6_14 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
phy-mode = "rgmii";
status = "okay";
};
@ -52,6 +71,8 @@ usdhc@0219c000 { /* uSDHC4 */
};
uart4: serial@021f0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "okay";
};
};

27
arch/arm/boot/dts/imx6q-sabrelite.dts
View File

@ -46,15 +46,20 @@ ssi1: ssi@02028000 {
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_hog>;
pinctrl-0 = <&pinctrl_hog>;
gpios {
pinctrl_gpio_hog: gpiohog {
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
1450 0x80000000 /* MX6Q_PAD_NANDF_D6__GPIO_2_6 */
1458 0x80000000 /* MX6Q_PAD_NANDF_D7__GPIO_2_7 */
121 0x80000000 /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
144 0x80000000 /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
152 0x80000000 /* MX6Q_PAD_EIM_D23__GPIO_3_23 */
1262 0x80000000 /* MX6Q_PAD_SD3_DAT5__GPIO_7_0 */
1270 0x1f0b0 /* MX6Q_PAD_SD3_DAT4__GPIO_7_1 */
953 0x80000000 /* MX6Q_PAD_GPIO_0__CCM_CLKO */
>;
};
};
};
@ -71,12 +76,16 @@ usb@02184200 { /* USB1 */
};
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2>;
cd-gpios = <&gpio7 0 0>;
wp-gpios = <&gpio7 1 0>;
vmmc-supply = <&reg_3p3v>;
@ -84,6 +93,8 @@ usdhc@02198000 { /* uSDHC3 */
};
usdhc@0219c000 { /* uSDHC4 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4_2>;
cd-gpios = <&gpio2 6 0>;
wp-gpios = <&gpio2 7 0>;
vmmc-supply = <&reg_3p3v>;
@ -99,7 +110,7 @@ audmux@021d8000 {
uart2: serial@021e8000 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_serial2_1>;
pinctrl-0 = <&pinctrl_uart2_1>;
};
i2c@021a0000 { /* I2C1 */

25
arch/arm/boot/dts/imx6q-sabresd.dts
View File

@ -22,28 +22,51 @@ memory {
};
soc {
aips-bus@02000000 { /* AIPS1 */
spba-bus@02000000 {
uart1: serial@02020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
};
iomuxc@020e0000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
1402 0x80000000 /* MX6Q_PAD_NANDF_D0__GPIO_2_0 */
1410 0x80000000 /* MX6Q_PAD_NANDF_D1__GPIO_2_1 */
1418 0x80000000 /* MX6Q_PAD_NANDF_D2__GPIO_2_2 */
1426 0x80000000 /* MX6Q_PAD_NANDF_D3__GPIO_2_3 */
>;
};
};
};
};
aips-bus@02100000 { /* AIPS2 */
ethernet@02188000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_1>;
phy-mode = "rgmii";
status = "okay";
};
usdhc@02194000 { /* uSDHC2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio2 2 0>;
wp-gpios = <&gpio2 3 0>;
status = "okay";
};
usdhc@02198000 { /* uSDHC3 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio2 0 0>;
wp-gpios = <&gpio2 1 0>;
status = "okay";

264
arch/arm/boot/dts/imx6q.dtsi
View File

@ -362,7 +362,6 @@ wdog@020bc000 { /* WDOG1 */
compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
status = "disabled";
};
wdog@020c0000 { /* WDOG2 */
@ -514,86 +513,199 @@ iomuxc@020e0000 {
/* shared pinctrl settings */
audmux {
pinctrl_audmux_1: audmux-1 {
fsl,pins = <18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
3 0x80000000>; /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1463 0x00b1>; /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
196 0x4001b8b1>; /* MX6Q_PAD_EIM_D28__I2C1_SDA */
};
};
serial2 {
pinctrl_serial2_1: serial2grp-1 {
fsl,pins = <183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
191 0x1b0b1>; /* MX6Q_PAD_EIM_D27__UART2_RXD */
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1241 0x17059>; /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059>; /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
fsl,pins = <
18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1>; /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
fsl,pins = <
101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
>;
};
pinctrl_enet_2: enetgrp-2 {
fsl,pins = <
890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
>;
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
>;
};
};
i2c1 {
pinctrl_i2c1_1: i2c1grp-1 {
fsl,pins = <
137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
>;
};
};
uart2 {
pinctrl_uart2_1: uart2grp-1 {
fsl,pins = <
183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
>;
};
};
uart4 {
pinctrl_uart4_1: uart4grp-1 {
fsl,pins = <
877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
>;
};
pinctrl_usdhc3_2: usdhc3grp-2 {
fsl,pins = <
1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
>;
};
};
usdhc4 {
pinctrl_usdhc4_1: usdhc4grp-1 {
fsl,pins = <
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
>;
};
pinctrl_usdhc4_2: usdhc4grp-2 {
fsl,pins = <
1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
>;
};
};
};

4
arch/arm/configs/imx_v6_v7_defconfig
View File

@ -32,9 +32,7 @@ CONFIG_MACH_VPR200=y
CONFIG_MACH_IMX51_DT=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_MACH_MX51_EFIKAMX=y
CONFIG_MACH_MX51_EFIKASB=y
CONFIG_MACH_IMX53_DT=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_MXC_PWM=y
CONFIG_SMP=y

108
arch/arm/mach-imx/Kconfig
View File

@ -101,13 +101,8 @@ config SOC_IMX51
select SOC_IMX5
select ARCH_MX5
select ARCH_MX51
config SOC_IMX53
bool
select SOC_IMX5
select ARCH_MX5
select ARCH_MX53
select HAVE_CAN_FLEXCAN if CAN
select PINCTRL
select PINCTRL_IMX51
if ARCH_IMX_V4_V5
@ -561,7 +556,6 @@ config MACH_BUG
config MACH_IMX31_DT
bool "Support i.MX31 platforms from device tree"
select SOC_IMX31
select USE_OF
help
Include support for Freescale i.MX31 based platforms
using the device tree for discovery.
@ -737,95 +731,19 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
endchoice
config MX51_EFIKA_COMMON
bool
select SOC_IMX51
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_PATA_IMX
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select MXC_ULPI if USB_ULPI
comment "Device tree only"
config SOC_IMX53
bool "i.MX53 support"
select SOC_IMX5
select ARCH_MX5
select ARCH_MX53
select HAVE_CAN_FLEXCAN if CAN
select PINCTRL
select PINCTRL_IMX53
config MACH_MX51_EFIKAMX
bool "Support MX51 Genesi Efika MX nettop"
select LEDS_GPIO_REGISTER
select MX51_EFIKA_COMMON
help
Include support for Genesi Efika MX nettop. This includes specific
configurations for the board and its peripherals.
config MACH_MX51_EFIKASB
bool "Support MX51 Genesi Efika Smartbook"
select LEDS_GPIO_REGISTER
select MX51_EFIKA_COMMON
help
Include support for Genesi Efika Smartbook. This includes specific
configurations for the board and its peripherals.
comment "i.MX53 machines:"
config MACH_IMX53_DT
bool "Support i.MX53 platforms from device tree"
select SOC_IMX53
select MACH_MX53_ARD
select MACH_MX53_EVK
select MACH_MX53_LOCO
select MACH_MX53_SMD
help
Include support for Freescale i.MX53 based platforms
using the device tree for discovery
config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
select LEDS_GPIO_REGISTER
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_SMD
bool "Support MX53 SMD platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 SMD platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_LOCO
bool "Support MX53 LOCO platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
select LEDS_GPIO_REGISTER
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX53_ARD
bool "Support MX53 ARD platforms"
select SOC_IMX53
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
help
Include support for MX53 ARD platform. This includes specific
configurations for the board and its peripherals.
comment "i.MX6 family:"
This enables support for Freescale i.MX53 processor.
config SOC_IMX6Q
bool "i.MX6 Quad support"

9
arch/arm/mach-imx/Makefile
View File

@ -83,16 +83,9 @@ endif
# i.MX5 based machines
obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o

8
arch/arm/mach-imx/Makefile.boot
View File

@ -39,8 +39,12 @@ params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
dtb-$(CONFIG_MACH_IMX51_DT) += imx51-babbage.dtb
dtb-$(CONFIG_MACH_IMX53_DT) += imx53-ard.dtb imx53-evk.dtb \
imx53-qsb.dtb imx53-smd.dtb
dtb-$(CONFIG_SOC_IMX53) += imx53-ard.dtb \
imx53-evk.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \

48
arch/arm/mach-imx/devices-imx53.h
View File

@ -1,48 +0,0 @@
/*
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#include <mach/mx53.h>
#include <mach/devices-common.h>
extern const struct imx_fec_data imx53_fec_data;
#define imx53_add_fec(pdata) \
imx_add_fec(&imx53_fec_data, pdata)
extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
#define imx53_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
#define imx53_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
extern const struct imx_spi_imx_data imx53_ecspi_data[];
#define imx53_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
#define imx53_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
#define imx53_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
extern const struct imx_pata_imx_data imx53_pata_imx_data;
#define imx53_add_pata_imx() \
imx_add_pata_imx(&imx53_pata_imx_data)
extern struct platform_device *__init imx53_add_ahci_imx(void);

10
arch/arm/mach-imx/efika.h
View File

@ -1,10 +0,0 @@
#ifndef _EFIKA_H
#define _EFIKA_H
#define EFIKA_WLAN_EN IMX_GPIO_NR(2, 16)
#define EFIKA_WLAN_RESET IMX_GPIO_NR(2, 10)
#define EFIKA_USB_PHY_RESET IMX_GPIO_NR(2, 9)
void __init efika_board_common_init(void);
#endif

21
arch/arm/mach-imx/imx51-dt.c
View File

@ -13,7 +13,6 @@
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
@ -44,27 +43,8 @@ static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
{ /* sentinel */ }
};
static void __init imx51_dt_init(void)
{
struct device_node *node;
const struct of_device_id *of_id;
void (*func)(void);
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
if (node) {
of_id = of_match_node(imx51_iomuxc_of_match, node);
func = of_id->data;
func();
of_node_put(node);
}
of_platform_populate(NULL, of_default_bus_match_table,
imx51_auxdata_lookup, NULL);
}
@ -79,7 +59,6 @@ static struct sys_timer imx51_timer = {
};
static const char *imx51_dt_board_compat[] __initdata = {
"fsl,imx51-babbage",
"fsl,imx51",
NULL
};

27
arch/arm/mach-imx/imx53-dt.c → arch/arm/mach-imx/mach-imx53.c
View File

@ -17,7 +17,6 @@
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
@ -51,14 +50,6 @@ static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
{ /* sentinel */ }
};
static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
{ .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
{ .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
{ .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
{ .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
{ /* sentinel */ }
};
static void __init imx53_qsb_init(void)
{
struct clk *clk;
@ -74,20 +65,6 @@ static void __init imx53_qsb_init(void)
static void __init imx53_dt_init(void)
{
struct device_node *node;
const struct of_device_id *of_id;
void (*func)(void);
pinctrl_provide_dummies();
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
if (node) {
of_id = of_match_node(imx53_iomuxc_of_match, node);
func = of_id->data;
func();
of_node_put(node);
}
if (of_machine_is_compatible("fsl,imx53-qsb"))
imx53_qsb_init();
@ -105,10 +82,6 @@ static struct sys_timer imx53_timer = {
};
static const char *imx53_dt_board_compat[] __initdata = {
"fsl,imx53-ard",
"fsl,imx53-evk",
"fsl,imx53-qsb",
"fsl,imx53-smd",
"fsl,imx53",
NULL
};

10
arch/arm/mach-imx/mach-imx6q.c
View File

@ -22,7 +22,6 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <linux/mfd/anatop.h>
@ -159,12 +158,6 @@ static void __init imx6q_usb_init(void)
static void __init imx6q_init_machine(void)
{
/*
* This should be removed when all imx6q boards have pinctrl
* states for devices defined in device tree.
*/
pinctrl_provide_dummies();
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
imx6q_sabrelite_init();
@ -218,9 +211,6 @@ static struct sys_timer imx6q_timer = {
};
static const char *imx6q_dt_compat[] __initdata = {
"fsl,imx6q-arm2",
"fsl,imx6q-sabrelite",
"fsl,imx6q-sabresd",
"fsl,imx6q",
NULL,
};

300
arch/arm/mach-imx/mach-mx51_efikamx.c
View File

@ -1,300 +0,0 @@
/*
* Copyright (C) 2010 Linaro Limited
*
* based on code from the following
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/setup.h>
#include <asm/system_info.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "efika.h"
#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
/* board 1.1 doesn't have same reset gpio */
#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
#define EFIKAMX_POWEROFF IMX_GPIO_NR(4, 13)
#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
/* the pci ids pin have pull up. they're driven low according to board id */
#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
static iomux_v3_cfg_t mx51efikamx_pads[] = {
/* board id */
MX51_PAD_PCBID0,
MX51_PAD_PCBID1,
MX51_PAD_PCBID2,
/* leds */
MX51_PAD_CSI1_D9__GPIO3_13,
MX51_PAD_CSI1_VSYNC__GPIO3_14,
MX51_PAD_CSI1_HSYNC__GPIO3_15,
/* power key */
MX51_PAD_PWRKEY,
/* reset */
MX51_PAD_DI1_PIN13__GPIO3_2,
MX51_PAD_GPIO1_4__GPIO1_4,
/* power off */
MX51_PAD_CSI2_VSYNC__GPIO4_13,
};
/* PCBID2 PCBID1 PCBID0 STATE
1 1 1 ER1:rev1.1
1 1 0 ER2:rev1.2
1 0 1 ER3:rev1.3
1 0 0 ER4:rev1.4
*/
static void __init mx51_efikamx_board_id(void)
{
int id;
/* things are taking time to settle */
msleep(150);
gpio_request(EFIKAMX_PCBID0, "pcbid0");
gpio_direction_input(EFIKAMX_PCBID0);
gpio_request(EFIKAMX_PCBID1, "pcbid1");
gpio_direction_input(EFIKAMX_PCBID1);
gpio_request(EFIKAMX_PCBID2, "pcbid2");
gpio_direction_input(EFIKAMX_PCBID2);
id = gpio_get_value(EFIKAMX_PCBID0) ? 1 : 0;
id |= (gpio_get_value(EFIKAMX_PCBID1) ? 1 : 0) << 1;
id |= (gpio_get_value(EFIKAMX_PCBID2) ? 1 : 0) << 2;
switch (id) {
case 7:
system_rev = 0x11;
break;
case 6:
system_rev = 0x12;
break;
case 5:
system_rev = 0x13;
break;
case 4:
system_rev = 0x14;
break;
default:
system_rev = 0x10;
break;
}
if ((system_rev == 0x10)
|| (system_rev == 0x12)
|| (system_rev == 0x14)) {
printk(KERN_WARNING
"EfikaMX: Unsupported board revision 1.%u!\n",
system_rev & 0xf);
}
}
static struct gpio_led mx51_efikamx_leds[] __initdata = {
{
.name = "efikamx:green",
.default_trigger = "default-on",
.gpio = EFIKAMX_GREEN_LED,
},
{
.name = "efikamx:red",
.default_trigger = "ide-disk",
.gpio = EFIKAMX_RED_LED,
},
{
.name = "efikamx:blue",
.default_trigger = "mmc0",
.gpio = EFIKAMX_BLUE_LED,
},
};
static const struct gpio_led_platform_data
mx51_efikamx_leds_data __initconst = {
.leds = mx51_efikamx_leds,
.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
};
static struct esdhc_platform_data sd_pdata = {
.cd_type = ESDHC_CD_CONTROLLER,
.wp_type = ESDHC_WP_CONTROLLER,
};
static struct gpio_keys_button mx51_efikamx_powerkey[] = {
{
.code = KEY_POWER,
.gpio = EFIKAMX_POWER_KEY,
.type = EV_PWR,
.desc = "Power Button (CM)",
.wakeup = 1,
.debounce_interval = 10, /* ms */
},
};
static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
.buttons = mx51_efikamx_powerkey,
.nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
};
static void mx51_efikamx_restart(char mode, const char *cmd)
{
if (system_rev == 0x11)
gpio_direction_output(EFIKAMX_RESET1_1, 0);
else
gpio_direction_output(EFIKAMX_RESET, 0);
}
static struct regulator *pwgt1, *pwgt2, *coincell;
static void mx51_efikamx_power_off(void)
{
if (!IS_ERR(coincell))
regulator_disable(coincell);
if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
regulator_disable(pwgt2);
regulator_disable(pwgt1);
}
gpio_direction_output(EFIKAMX_POWEROFF, 1);
}
static int __init mx51_efikamx_power_init(void)
{
pwgt1 = regulator_get(NULL, "pwgt1");
pwgt2 = regulator_get(NULL, "pwgt2");
if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
regulator_enable(pwgt1);
regulator_enable(pwgt2);
}
gpio_request(EFIKAMX_POWEROFF, "poweroff");
pm_power_off = mx51_efikamx_power_off;
/* enable coincell charger. maybe need a small power driver ? */
coincell = regulator_get(NULL, "coincell");
if (!IS_ERR(coincell)) {
regulator_set_voltage(coincell, 3000000, 3000000);
regulator_enable(coincell);
}
regulator_has_full_constraints();
return 0;
}
static void __init mx51_efikamx_init_late(void)
{
imx51_init_late();
mx51_efikamx_power_init();
}
static void __init mx51_efikamx_init(void)
{
imx51_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
ARRAY_SIZE(mx51efikamx_pads));
efika_board_common_init();
mx51_efikamx_board_id();
/* on < 1.2 boards both SD controllers are used */
if (system_rev < 0x12) {
imx51_add_sdhci_esdhc_imx(0, NULL);
imx51_add_sdhci_esdhc_imx(1, &sd_pdata);
mx51_efikamx_leds[2].default_trigger = "mmc1";
} else
imx51_add_sdhci_esdhc_imx(0, &sd_pdata);
gpio_led_register_device(-1, &mx51_efikamx_leds_data);
imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
if (system_rev == 0x11) {
gpio_request(EFIKAMX_RESET1_1, "reset");
gpio_direction_output(EFIKAMX_RESET1_1, 1);
} else {
gpio_request(EFIKAMX_RESET, "reset");
gpio_direction_output(EFIKAMX_RESET, 1);
}
/*
* enable wifi by default only on mx
* sb and mx have same wlan pin but the value to enable it are
* different :/
*/
gpio_request(EFIKA_WLAN_EN, "wlan_en");
gpio_direction_output(EFIKA_WLAN_EN, 0);
msleep(10);
gpio_request(EFIKA_WLAN_RESET, "wlan_rst");
gpio_direction_output(EFIKA_WLAN_RESET, 0);
msleep(10);
gpio_set_value(EFIKA_WLAN_RESET, 1);
}
static void __init mx51_efikamx_timer_init(void)
{
mx51_clocks_init(32768, 24000000, 22579200, 24576000);
}
static struct sys_timer mx51_efikamx_timer = {
.init = mx51_efikamx_timer_init,
};
MACHINE_START(MX51_EFIKAMX, "Genesi Efika MX (Smarttop)")
.atag_offset = 0x100,
.map_io = mx51_map_io,
.init_early = imx51_init_early,
.init_irq = mx51_init_irq,
.handle_irq = imx51_handle_irq,
.timer = &mx51_efikamx_timer,
.init_machine = mx51_efikamx_init,
.init_late = mx51_efikamx_init_late,
.restart = mx51_efikamx_restart,
MACHINE_END

296
arch/arm/mach-imx/mach-mx51_efikasb.c
View File

@ -1,296 +0,0 @@
/*
* Copyright (C) Arnaud Patard <arnaud.patard@rtp-net.org>
*
* based on code from the following
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <mach/ulpi.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <asm/setup.h>
#include <asm/system_info.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "efika.h"
#define EFIKASB_USBH2_STP IMX_GPIO_NR(2, 20)
#define EFIKASB_GREEN_LED IMX_GPIO_NR(1, 3)
#define EFIKASB_WHITE_LED IMX_GPIO_NR(2, 25)
#define EFIKASB_PCBID0 IMX_GPIO_NR(2, 28)
#define EFIKASB_PCBID1 IMX_GPIO_NR(2, 29)
#define EFIKASB_PWRKEY IMX_GPIO_NR(2, 31)
#define EFIKASB_LID IMX_GPIO_NR(3, 14)
#define EFIKASB_POWEROFF IMX_GPIO_NR(4, 13)
#define EFIKASB_RFKILL IMX_GPIO_NR(3, 1)
#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
#define MX51_PAD_SD1_CD IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL)
static iomux_v3_cfg_t mx51efikasb_pads[] = {
/* USB HOST2 */
MX51_PAD_EIM_D16__USBH2_DATA0,
MX51_PAD_EIM_D17__USBH2_DATA1,
MX51_PAD_EIM_D18__USBH2_DATA2,
MX51_PAD_EIM_D19__USBH2_DATA3,
MX51_PAD_EIM_D20__USBH2_DATA4,
MX51_PAD_EIM_D21__USBH2_DATA5,
MX51_PAD_EIM_D22__USBH2_DATA6,
MX51_PAD_EIM_D23__USBH2_DATA7,
MX51_PAD_EIM_A24__USBH2_CLK,
MX51_PAD_EIM_A25__USBH2_DIR,
MX51_PAD_EIM_A26__USBH2_STP,
MX51_PAD_EIM_A27__USBH2_NXT,
/* leds */
MX51_PAD_EIM_CS0__GPIO2_25,
MX51_PAD_GPIO1_3__GPIO1_3,
/* pcb id */
MX51_PAD_EIM_CS3__GPIO2_28,
MX51_PAD_EIM_CS4__GPIO2_29,
/* lid */
MX51_PAD_CSI1_VSYNC__GPIO3_14,
/* power key*/
MX51_PAD_PWRKEY,
/* wifi/bt button */
MX51_PAD_DI1_PIN12__GPIO3_1,
/* power off */
MX51_PAD_CSI2_VSYNC__GPIO4_13,
/* wdog reset */
MX51_PAD_GPIO1_4__WDOG1_WDOG_B,
/* BT */
MX51_PAD_EIM_A17__GPIO2_11,
MX51_PAD_SD1_CD,
};
static int initialize_usbh2_port(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP;
iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20;
mxc_iomux_v3_setup_pad(usbh2gpio);
gpio_request(EFIKASB_USBH2_STP, "usbh2_stp");
gpio_direction_output(EFIKASB_USBH2_STP, 0);
msleep(1);
gpio_set_value(EFIKASB_USBH2_STP, 1);
msleep(1);
gpio_free(EFIKASB_USBH2_STP);
mxc_iomux_v3_setup_pad(usbh2stp);
mdelay(10);
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data usbh2_config __initdata = {
.init = initialize_usbh2_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
static void __init mx51_efikasb_usb(void)
{
usbh2_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
if (usbh2_config.otg)
imx51_add_mxc_ehci_hs(2, &usbh2_config);
}
static const struct gpio_led mx51_efikasb_leds[] __initconst = {
{
.name = "efikasb:green",
.default_trigger = "default-on",
.gpio = EFIKASB_GREEN_LED,
.active_low = 1,
},
{
.name = "efikasb:white",
.default_trigger = "caps",
.gpio = EFIKASB_WHITE_LED,
},
};
static const struct gpio_led_platform_data
mx51_efikasb_leds_data __initconst = {
.leds = mx51_efikasb_leds,
.num_leds = ARRAY_SIZE(mx51_efikasb_leds),
};
static struct gpio_keys_button mx51_efikasb_keys[] = {
{
.code = KEY_POWER,
.gpio = EFIKASB_PWRKEY,
.type = EV_KEY,
.desc = "Power Button",
.wakeup = 1,
.active_low = 1,
},
{
.code = SW_LID,
.gpio = EFIKASB_LID,
.type = EV_SW,
.desc = "Lid Switch",
.active_low = 1,
},
{
.code = KEY_RFKILL,
.gpio = EFIKASB_RFKILL,
.type = EV_KEY,
.desc = "rfkill",
.active_low = 1,
},
};
static const struct gpio_keys_platform_data mx51_efikasb_keys_data __initconst = {
.buttons = mx51_efikasb_keys,
.nbuttons = ARRAY_SIZE(mx51_efikasb_keys),
};
static struct esdhc_platform_data sd0_pdata = {
#define EFIKASB_SD1_CD IMX_GPIO_NR(2, 27)
.cd_gpio = EFIKASB_SD1_CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_CONTROLLER,
};
static struct esdhc_platform_data sd1_pdata = {
.cd_type = ESDHC_CD_CONTROLLER,
.wp_type = ESDHC_WP_CONTROLLER,
};
static struct regulator *pwgt1, *pwgt2;
static void mx51_efikasb_power_off(void)
{
gpio_set_value(EFIKA_USB_PHY_RESET, 0);
if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
regulator_disable(pwgt2);
regulator_disable(pwgt1);
}
gpio_direction_output(EFIKASB_POWEROFF, 1);
}
static int __init mx51_efikasb_power_init(void)
{
pwgt1 = regulator_get(NULL, "pwgt1");
pwgt2 = regulator_get(NULL, "pwgt2");
if (!IS_ERR(pwgt1) && !IS_ERR(pwgt2)) {
regulator_enable(pwgt1);
regulator_enable(pwgt2);
}
gpio_request(EFIKASB_POWEROFF, "poweroff");
pm_power_off = mx51_efikasb_power_off;
regulator_has_full_constraints();
return 0;
}
static void __init mx51_efikasb_init_late(void)
{
imx51_init_late();
mx51_efikasb_power_init();
}
/* 01 R1.3 board
10 R2.0 board */
static void __init mx51_efikasb_board_id(void)
{
int id;
gpio_request(EFIKASB_PCBID0, "pcb id0");
gpio_direction_input(EFIKASB_PCBID0);
gpio_request(EFIKASB_PCBID1, "pcb id1");
gpio_direction_input(EFIKASB_PCBID1);
id = gpio_get_value(EFIKASB_PCBID0) ? 1 : 0;
id |= (gpio_get_value(EFIKASB_PCBID1) ? 1 : 0) << 1;
switch (id) {
default:
break;
case 1:
system_rev = 0x13;
break;
case 2:
system_rev = 0x20;
break;
}
}
static void __init efikasb_board_init(void)
{
imx51_soc_init();
mxc_iomux_v3_setup_multiple_pads(mx51efikasb_pads,
ARRAY_SIZE(mx51efikasb_pads));
efika_board_common_init();
mx51_efikasb_board_id();
mx51_efikasb_usb();
imx51_add_sdhci_esdhc_imx(0, &sd0_pdata);
imx51_add_sdhci_esdhc_imx(1, &sd1_pdata);
gpio_led_register_device(-1, &mx51_efikasb_leds_data);
imx_add_gpio_keys(&mx51_efikasb_keys_data);
}
static void __init mx51_efikasb_timer_init(void)
{
mx51_clocks_init(32768, 24000000, 22579200, 24576000);
}
static struct sys_timer mx51_efikasb_timer = {
.init = mx51_efikasb_timer_init,
};
MACHINE_START(MX51_EFIKASB, "Genesi Efika MX (Smartbook)")
.atag_offset = 0x100,
.map_io = mx51_map_io,
.init_early = imx51_init_early,
.init_irq = mx51_init_irq,
.handle_irq = imx51_handle_irq,
.init_machine = efikasb_board_init,
.init_late = mx51_efikasb_init_late,
.timer = &mx51_efikasb_timer,
.restart = mxc_restart,
MACHINE_END

272
arch/arm/mach-imx/mach-mx53_ard.c
View File

@ -1,272 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx53.h"
#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
#define ARD_HOME IMX_GPIO_NR(5, 10)
#define ARD_BACK IMX_GPIO_NR(5, 11)
#define ARD_PROG IMX_GPIO_NR(5, 12)
#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
static iomux_v3_cfg_t mx53_ard_pads[] = {
/* UART1 */
MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
/* WEIM for CS1 */
MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
MX53_PAD_EIM_D16__EMI_WEIM_D_16,
MX53_PAD_EIM_D17__EMI_WEIM_D_17,
MX53_PAD_EIM_D18__EMI_WEIM_D_18,
MX53_PAD_EIM_D19__EMI_WEIM_D_19,
MX53_PAD_EIM_D20__EMI_WEIM_D_20,
MX53_PAD_EIM_D21__EMI_WEIM_D_21,
MX53_PAD_EIM_D22__EMI_WEIM_D_22,
MX53_PAD_EIM_D23__EMI_WEIM_D_23,
MX53_PAD_EIM_D24__EMI_WEIM_D_24,
MX53_PAD_EIM_D25__EMI_WEIM_D_25,
MX53_PAD_EIM_D26__EMI_WEIM_D_26,
MX53_PAD_EIM_D27__EMI_WEIM_D_27,
MX53_PAD_EIM_D28__EMI_WEIM_D_28,
MX53_PAD_EIM_D29__EMI_WEIM_D_29,
MX53_PAD_EIM_D30__EMI_WEIM_D_30,
MX53_PAD_EIM_D31__EMI_WEIM_D_31,
MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
MX53_PAD_EIM_OE__EMI_WEIM_OE,
MX53_PAD_EIM_RW__EMI_WEIM_RW,
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
/* SDHC1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
MX53_PAD_GPIO_1__GPIO1_1,
MX53_PAD_GPIO_9__GPIO1_9,
/* I2C2 */
MX53_PAD_EIM_EB2__I2C2_SCL,
MX53_PAD_KEY_ROW3__I2C2_SDA,
/* I2C3 */
MX53_PAD_GPIO_3__I2C3_SCL,
MX53_PAD_GPIO_16__I2C3_SDA,
/* GPIO */
MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
};
#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
{ \
.gpio = gpio_num, \
.type = EV_KEY, \
.code = ev_code, \
.active_low = act_low, \
.desc = "btn " descr, \
.wakeup = wake, \
}
static struct gpio_keys_button ard_buttons[] = {
GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
};
static const struct gpio_keys_platform_data ard_button_data __initconst = {
.buttons = ard_buttons,
.nbuttons = ARRAY_SIZE(ard_buttons),
};
static struct resource ard_smsc911x_resources[] = {
{
.start = MX53_CS1_64MB_BASE_ADDR,
.end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
.flags = IORESOURCE_MEM,
},
{
/* irq number is run-time assigned */
.flags = IORESOURCE_IRQ,
},
};
struct smsc911x_platform_config ard_smsc911x_config = {
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
.flags = SMSC911X_USE_32BIT,
};
static struct platform_device ard_smsc_lan9220_device = {
.name = "smsc911x",
.id = -1,
.num_resources = ARRAY_SIZE(ard_smsc911x_resources),
.resource = ard_smsc911x_resources,
.dev = {
.platform_data = &ard_smsc911x_config,
},
};
static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
.cd_gpio = ARD_SD1_CD,
.wp_gpio = ARD_SD1_WP,
};
static struct imxi2c_platform_data mx53_ard_i2c2_data = {
.bitrate = 50000,
};
static struct imxi2c_platform_data mx53_ard_i2c3_data = {
.bitrate = 400000,
};
static void __init mx53_ard_io_init(void)
{
gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
gpio_direction_input(ARD_ETHERNET_INT_B);
gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
gpio_direction_output(ARD_I2CPORTEXP_B, 1);
}
/* Config CS1 settings for ethernet controller */
static int weim_cs_config(void)
{
u32 reg;
void __iomem *weim_base, *iomuxc_base;
weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
if (!weim_base)
return -ENOMEM;
iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
if (!iomuxc_base) {
iounmap(weim_base);
return -ENOMEM;
}
/* CS1 timings for LAN9220 */
writel(0x20001, (weim_base + 0x18));
writel(0x0, (weim_base + 0x1C));
writel(0x16000202, (weim_base + 0x20));
writel(0x00000002, (weim_base + 0x24));
writel(0x16002082, (weim_base + 0x28));
writel(0x00000000, (weim_base + 0x2C));
writel(0x00000000, (weim_base + 0x90));
/* specify 64 MB on CS1 and CS0 on GPR1 */
reg = readl(iomuxc_base + 0x4);
reg &= ~0x3F;
reg |= 0x1B;
writel(reg, (iomuxc_base + 0x4));
iounmap(iomuxc_base);
iounmap(weim_base);
return 0;
}
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
REGULATOR_SUPPLY("vddvario", "smsc911x"),
};
void __init imx53_ard_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
ARRAY_SIZE(mx53_ard_pads));
weim_cs_config();
}
static struct platform_device *devices[] __initdata = {
&ard_smsc_lan9220_device,
};
static void __init mx53_ard_board_init(void)
{
imx53_soc_init();
imx53_add_imx_uart(0, NULL);
imx53_ard_common_init();
mx53_ard_io_init();
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
ard_smsc911x_resources[1].start = gpio_to_irq(ARD_ETHERNET_INT_B);
ard_smsc911x_resources[1].end = gpio_to_irq(ARD_ETHERNET_INT_B);
platform_add_devices(devices, ARRAY_SIZE(devices));
imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
imx53_add_imx2_wdt(0);
imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
imx_add_gpio_keys(&ard_button_data);
imx53_add_ahci_imx();
}
static void __init mx53_ard_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_ard_timer = {
.init = mx53_ard_timer_init,
};
MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.timer = &mx53_ard_timer,
.init_machine = mx53_ard_board_init,
.init_late = imx53_init_late,
.restart = mxc_restart,
MACHINE_END

179
arch/arm/mach-imx/mach-mx53_evk.c
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@ -1,179 +0,0 @@
/*
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/iomux-mx53.h>
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#define MX53EVK_LED IMX_GPIO_NR(7, 7)
#include "devices-imx53.h"
static iomux_v3_cfg_t mx53_evk_pads[] = {
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
MX53_PAD_PATA_DIOR__UART2_RTS,
MX53_PAD_PATA_INTRQ__UART2_CTS,
MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
MX53_PAD_EIM_D16__ECSPI1_SCLK,
MX53_PAD_EIM_D17__ECSPI1_MISO,
MX53_PAD_EIM_D18__ECSPI1_MOSI,
/* ecspi chip select lines */
MX53_PAD_EIM_EB2__GPIO2_30,
MX53_PAD_EIM_D19__GPIO3_19,
/* LED */
MX53_PAD_PATA_DA_1__GPIO7_7,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static const struct gpio_led mx53evk_leds[] __initconst = {
{
.name = "green",
.default_trigger = "heartbeat",
.gpio = MX53EVK_LED,
},
};
static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
.leds = mx53evk_leds,
.num_leds = ARRAY_SIZE(mx53evk_leds),
};
static inline void mx53_evk_init_uart(void)
{
imx53_add_imx_uart(0, NULL);
imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
imx53_add_imx_uart(2, NULL);
}
static const struct imxi2c_platform_data mx53_evk_i2c_data __initconst = {
.bitrate = 100000,
};
static inline void mx53_evk_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request_one(MX53_EVK_FEC_PHY_RST, GPIOF_OUT_INIT_LOW,
"fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
msleep(1);
gpio_set_value(MX53_EVK_FEC_PHY_RST, 1);
}
static const struct fec_platform_data mx53_evk_fec_pdata __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static struct spi_board_info mx53_evk_spi_board_info[] __initdata = {
{
.modalias = "mtd_dataflash",
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 1,
.mode = SPI_MODE_0,
.platform_data = NULL,
},
};
static int mx53_evk_spi_cs[] = {
EVK_ECSPI1_CS0,
EVK_ECSPI1_CS1,
};
static const struct spi_imx_master mx53_evk_spi_data __initconst = {
.chipselect = mx53_evk_spi_cs,
.num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
};
void __init imx53_evk_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
ARRAY_SIZE(mx53_evk_pads));
}
static void __init mx53_evk_board_init(void)
{
imx53_soc_init();
imx53_evk_common_init();
mx53_evk_init_uart();
mx53_evk_fec_reset();
imx53_add_fec(&mx53_evk_fec_pdata);
imx53_add_imx_i2c(0, &mx53_evk_i2c_data);
imx53_add_imx_i2c(1, &mx53_evk_i2c_data);
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
spi_register_board_info(mx53_evk_spi_board_info,
ARRAY_SIZE(mx53_evk_spi_board_info));
imx53_add_ecspi(0, &mx53_evk_spi_data);
imx53_add_imx2_wdt(0);
gpio_led_register_device(-1, &mx53evk_leds_data);
}
static void __init mx53_evk_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_evk_timer = {
.init = mx53_evk_timer_init,
};
MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.timer = &mx53_evk_timer,
.init_machine = mx53_evk_board_init,
.init_late = imx53_init_late,
.restart = mxc_restart,
MACHINE_END

321
arch/arm/mach-imx/mach-mx53_loco.c
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@ -1,321 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx53.h"
#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define LOCO_LED IMX_GPIO_NR(7, 7)
#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
#define LOCO_ACCEL_EN IMX_GPIO_NR(6, 14)
static iomux_v3_cfg_t mx53_loco_pads[] = {
/* FEC */
MX53_PAD_FEC_MDC__FEC_MDC,
MX53_PAD_FEC_MDIO__FEC_MDIO,
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
MX53_PAD_FEC_RX_ER__FEC_RX_ER,
MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
MX53_PAD_FEC_RXD1__FEC_RDATA_1,
MX53_PAD_FEC_RXD0__FEC_RDATA_0,
MX53_PAD_FEC_TX_EN__FEC_TX_EN,
MX53_PAD_FEC_TXD1__FEC_TDATA_1,
MX53_PAD_FEC_TXD0__FEC_TDATA_0,
/* FEC_nRST */
MX53_PAD_PATA_DA_0__GPIO7_6,
/* FEC_nINT */
MX53_PAD_PATA_DATA4__GPIO2_4,
/* AUDMUX5 */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC,
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD,
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS,
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD,
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
MX53_PAD_NANDF_CS1__GPIO6_14, /* Accelerometer Enable */
/* I2C2 */
MX53_PAD_KEY_COL3__I2C2_SCL,
MX53_PAD_KEY_ROW3__I2C2_SDA,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD1_CD */
MX53_PAD_EIM_DA13__GPIO3_13,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
/* SD3_CD */
MX53_PAD_EIM_DA11__GPIO3_11,
/* SD3_WP */
MX53_PAD_EIM_DA12__GPIO3_12,
/* VGA */
MX53_PAD_EIM_OE__IPU_DI1_PIN7,
MX53_PAD_EIM_RW__IPU_DI1_PIN8,
/* DISPLB */
MX53_PAD_EIM_D20__IPU_SER_DISP0_CS,
MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK,
MX53_PAD_EIM_D22__IPU_DISPB0_SER_DIN,
MX53_PAD_EIM_D23__IPU_DI0_D0_CS,
/* DISP0_POWER_EN */
MX53_PAD_EIM_D24__GPIO3_24,
/* DISP0 DET INT */
MX53_PAD_EIM_D31__GPIO3_31,
/* LVDS */
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3,
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2,
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK,
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1,
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0,
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
/* UART1 */
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
/* CSI0 */
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12,
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13,
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14,
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15,
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16,
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17,
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18,
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19,
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC,
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC,
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK,
/* DISPLAY */
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK,
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15,
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2,
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3,
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0,
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1,
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2,
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3,
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4,
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5,
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6,
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7,
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8,
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9,
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10,
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11,
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12,
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13,
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14,
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15,
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16,
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17,
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18,
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19,
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20,
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21,
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22,
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23,
/* Audio CLK*/
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK,
/* PWM */
MX53_PAD_GPIO_1__PWM2_PWMO,
/* SPDIF */
MX53_PAD_GPIO_7__SPDIF_PLOCK,
MX53_PAD_GPIO_17__SPDIF_OUT1,
/* GPIO */
MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
MX53_PAD_PATA_DA_2__GPIO7_8,
MX53_PAD_PATA_DATA5__GPIO2_5,
MX53_PAD_PATA_DATA6__GPIO2_6,
MX53_PAD_PATA_DATA14__GPIO2_14,
MX53_PAD_PATA_DATA15__GPIO2_15,
MX53_PAD_PATA_INTRQ__GPIO7_2,
MX53_PAD_EIM_WAIT__GPIO5_0,
MX53_PAD_NANDF_WP_B__GPIO6_9,
MX53_PAD_NANDF_RB0__GPIO6_10,
MX53_PAD_NANDF_CS1__GPIO6_14,
MX53_PAD_NANDF_CS2__GPIO6_15,
MX53_PAD_NANDF_CS3__GPIO6_16,
MX53_PAD_GPIO_5__GPIO1_5,
MX53_PAD_GPIO_16__GPIO7_11,
MX53_PAD_GPIO_8__GPIO1_8,
};
#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
{ \
.gpio = gpio_num, \
.type = EV_KEY, \
.code = ev_code, \
.active_low = act_low, \
.desc = "btn " descr, \
.wakeup = wake, \
}
static struct gpio_keys_button loco_buttons[] = {
GPIO_BUTTON(MX53_LOCO_POWER, KEY_POWER, 1, "power", 0),
GPIO_BUTTON(MX53_LOCO_UI1, KEY_VOLUMEUP, 1, "volume-up", 0),
GPIO_BUTTON(MX53_LOCO_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0),
};
static const struct gpio_keys_platform_data loco_button_data __initconst = {
.buttons = loco_buttons,
.nbuttons = ARRAY_SIZE(loco_buttons),
};
static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
.cd_gpio = LOCO_SD1_CD,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_NONE,
};
static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
.cd_gpio = LOCO_SD3_CD,
.wp_gpio = LOCO_SD3_WP,
.cd_type = ESDHC_CD_GPIO,
.wp_type = ESDHC_WP_GPIO,
};
static inline void mx53_loco_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(LOCO_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(LOCO_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(LOCO_FEC_PHY_RST, 1);
}
static const struct fec_platform_data mx53_loco_fec_data __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
.bitrate = 100000,
};
static const struct gpio_led mx53loco_leds[] __initconst = {
{
.name = "green",
.default_trigger = "heartbeat",
.gpio = LOCO_LED,
},
};
static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
.leds = mx53loco_leds,
.num_leds = ARRAY_SIZE(mx53loco_leds),
};
void __init imx53_qsb_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
ARRAY_SIZE(mx53_loco_pads));
}
static struct i2c_board_info mx53loco_i2c_devices[] = {
{
I2C_BOARD_INFO("mma8450", 0x1C),
},
};
static void __init mx53_loco_board_init(void)
{
int ret;
imx53_soc_init();
imx53_qsb_common_init();
imx53_add_imx_uart(0, NULL);
mx53_loco_fec_reset();
imx53_add_fec(&mx53_loco_fec_data);
imx53_add_imx2_wdt(0);
ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
if (ret)
pr_err("Cannot request ACCEL_EN pin: %d\n", ret);
i2c_register_board_info(0, mx53loco_i2c_devices,
ARRAY_SIZE(mx53loco_i2c_devices));
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
imx_add_gpio_keys(&loco_button_data);
gpio_led_register_device(-1, &mx53loco_leds_data);
imx53_add_ahci_imx();
}
static void __init mx53_loco_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 0, 0);
}
static struct sys_timer mx53_loco_timer = {
.init = mx53_loco_timer_init,
};
MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.timer = &mx53_loco_timer,
.init_machine = mx53_loco_board_init,
.init_late = imx53_init_late,
.restart = mxc_restart,
MACHINE_END

168
arch/arm/mach-imx/mach-mx53_smd.c
View File

@ -1,168 +0,0 @@
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*/
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx53.h"
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3)
static iomux_v3_cfg_t mx53_smd_pads[] = {
MX53_PAD_CSI0_DAT10__UART1_TXD_MUX,
MX53_PAD_CSI0_DAT11__UART1_RXD_MUX,
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX,
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX,
MX53_PAD_PATA_CS_0__UART3_TXD_MUX,
MX53_PAD_PATA_CS_1__UART3_RXD_MUX,
MX53_PAD_PATA_DA_1__UART3_CTS,
MX53_PAD_PATA_DA_2__UART3_RTS,
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
/* SD1 */
MX53_PAD_SD1_CMD__ESDHC1_CMD,
MX53_PAD_SD1_CLK__ESDHC1_CLK,
MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
/* SD2 */
MX53_PAD_SD2_CMD__ESDHC2_CMD,
MX53_PAD_SD2_CLK__ESDHC2_CLK,
MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
MX53_PAD_PATA_IORDY__ESDHC3_CLK,
MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
};
static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mx53_smd_init_uart(void)
{
imx53_add_imx_uart(0, NULL);
imx53_add_imx_uart(1, NULL);
imx53_add_imx_uart(2, &mx53_smd_uart_data);
}
static inline void mx53_smd_fec_reset(void)
{
int ret;
/* reset FEC PHY */
ret = gpio_request(SMD_FEC_PHY_RST, "fec-phy-reset");
if (ret) {
printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
return;
}
gpio_direction_output(SMD_FEC_PHY_RST, 0);
msleep(1);
gpio_set_value(SMD_FEC_PHY_RST, 1);
}
static const struct fec_platform_data mx53_smd_fec_data __initconst = {
.phy = PHY_INTERFACE_MODE_RMII,
};
static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = {
.bitrate = 100000,
};
static inline void mx53_smd_ahci_pwr_on(void)
{
int ret;
/* Enable SATA PWR */
ret = gpio_request_one(MX53_SMD_SATA_PWR_EN,
GPIOF_DIR_OUT | GPIOF_INIT_HIGH, "ahci-sata-pwr");
if (ret) {
pr_err("failed to enable SATA_PWR_EN: %d\n", ret);
return;
}
}
void __init imx53_smd_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
ARRAY_SIZE(mx53_smd_pads));
}
static void __init mx53_smd_board_init(void)
{
imx53_soc_init();
imx53_smd_common_init();
mx53_smd_init_uart();
mx53_smd_fec_reset();
imx53_add_fec(&mx53_smd_fec_data);
imx53_add_imx2_wdt(0);
imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
imx53_add_sdhci_esdhc_imx(0, NULL);
imx53_add_sdhci_esdhc_imx(1, NULL);
imx53_add_sdhci_esdhc_imx(2, NULL);
mx53_smd_ahci_pwr_on();
imx53_add_ahci_imx();
}
static void __init mx53_smd_timer_init(void)
{
mx53_clocks_init(32768, 24000000, 22579200, 0);
}
static struct sys_timer mx53_smd_timer = {
.init = mx53_smd_timer_init,
};
MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
.map_io = mx53_map_io,
.init_early = imx53_init_early,
.init_irq = mx53_init_irq,
.handle_irq = imx53_handle_irq,
.timer = &mx53_smd_timer,
.init_machine = mx53_smd_board_init,
.init_late = imx53_init_late,
.restart = mxc_restart,
MACHINE_END

47
arch/arm/mach-imx/mm-imx5.c
View File

@ -128,25 +128,6 @@ static struct sdma_platform_data imx51_sdma_pdata __initdata = {
.script_addrs = &imx51_sdma_script,
};
static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
.ap_2_ap_addr = 642,
.app_2_mcu_addr = 683,
.mcu_2_app_addr = 747,
.uart_2_mcu_addr = 817,
.shp_2_mcu_addr = 891,
.mcu_2_shp_addr = 960,
.uartsh_2_mcu_addr = 1032,
.spdif_2_mcu_addr = 1100,
.mcu_2_spdif_addr = 1134,
.firi_2_mcu_addr = 1193,
.mcu_2_firi_addr = 1290,
};
static struct sdma_platform_data imx53_sdma_pdata __initdata = {
.fw_name = "sdma-imx53.bin",
.script_addrs = &imx53_sdma_script,
};
static const struct resource imx50_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX50_AUDMUX_BASE_ADDR, SZ_16K),
};
@ -155,10 +136,6 @@ static const struct resource imx51_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
};
static const struct resource imx53_audmux_res[] __initconst = {
DEFINE_RES_MEM(MX53_AUDMUX_BASE_ADDR, SZ_16K),
};
void __init imx50_soc_init(void)
{
/* i.mx50 has the i.mx35 type gpio */
@ -196,30 +173,6 @@ void __init imx51_soc_init(void)
ARRAY_SIZE(imx51_audmux_res));
}
void __init imx53_soc_init(void)
{
/* i.mx53 has the i.mx35 type gpio */
mxc_register_gpio("imx35-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
mxc_register_gpio("imx35-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
mxc_register_gpio("imx35-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
mxc_register_gpio("imx35-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
mxc_register_gpio("imx35-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
mxc_register_gpio("imx35-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
mxc_register_gpio("imx35-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
pinctrl_provide_dummies();
/* i.mx53 has the i.mx35 type sdma */
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
/* Setup AIPS registers */
imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR));
imx_set_aips(MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR));
/* i.mx53 has the i.mx31 type audmux */
platform_device_register_simple("imx31-audmux", 0, imx53_audmux_res,
ARRAY_SIZE(imx53_audmux_res));
}
void __init imx51_init_late(void)
{
mx51_neon_fixup();

633
arch/arm/mach-imx/mx51_efika.c
View File

@ -1,633 +0,0 @@
/*
* based on code from the following
* Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2009-2010 Pegatron Corporation. All Rights Reserved.
* Copyright 2009-2010 Genesi USA, Inc. All Rights Reserved.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/consumer.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <mach/ulpi.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "devices-imx51.h"
#include "efika.h"
#include "cpu_op-mx51.h"
#define MX51_USB_CTRL_1_OFFSET 0x10
#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
#define EFIKAMX_USB_HUB_RESET IMX_GPIO_NR(1, 5)
#define EFIKAMX_USBH1_STP IMX_GPIO_NR(1, 27)
#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
#define EFIKAMX_PMIC IMX_GPIO_NR(1, 6)
static iomux_v3_cfg_t mx51efika_pads[] = {
/* UART1 */
MX51_PAD_UART1_RXD__UART1_RXD,
MX51_PAD_UART1_TXD__UART1_TXD,
MX51_PAD_UART1_RTS__UART1_RTS,
MX51_PAD_UART1_CTS__UART1_CTS,
/* SD 1 */
MX51_PAD_SD1_CMD__SD1_CMD,
MX51_PAD_SD1_CLK__SD1_CLK,
MX51_PAD_SD1_DATA0__SD1_DATA0,
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
MX51_PAD_SD2_CLK__SD2_CLK,
MX51_PAD_SD2_DATA0__SD2_DATA0,
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
/* SD/MMC WP/CD */
MX51_PAD_GPIO1_0__SD1_CD,
MX51_PAD_GPIO1_1__SD1_WP,
MX51_PAD_GPIO1_7__SD2_WP,
MX51_PAD_GPIO1_8__SD2_CD,
/* spi */
MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
MX51_PAD_CSPI1_SS0__GPIO4_24,
MX51_PAD_CSPI1_SS1__GPIO4_25,
MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
MX51_PAD_GPIO1_6__GPIO1_6,
/* USB HOST1 */
MX51_PAD_USBH1_CLK__USBH1_CLK,
MX51_PAD_USBH1_DIR__USBH1_DIR,
MX51_PAD_USBH1_NXT__USBH1_NXT,
MX51_PAD_USBH1_DATA0__USBH1_DATA0,
MX51_PAD_USBH1_DATA1__USBH1_DATA1,
MX51_PAD_USBH1_DATA2__USBH1_DATA2,
MX51_PAD_USBH1_DATA3__USBH1_DATA3,
MX51_PAD_USBH1_DATA4__USBH1_DATA4,
MX51_PAD_USBH1_DATA5__USBH1_DATA5,
MX51_PAD_USBH1_DATA6__USBH1_DATA6,
MX51_PAD_USBH1_DATA7__USBH1_DATA7,
/* USB HUB RESET */
MX51_PAD_GPIO1_5__GPIO1_5,
/* WLAN */
MX51_PAD_EIM_A22__GPIO2_16,
MX51_PAD_EIM_A16__GPIO2_10,
/* USB PHY RESET */
MX51_PAD_EIM_D27__GPIO2_9,
};
/* Serial ports */
static const struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
/* This function is board specific as the bit mask for the plldiv will also
* be different for other Freescale SoCs, thus a common bitmask is not
* possible and cannot get place in /plat-mxc/ehci.c.
*/
static int initialize_otg_port(struct platform_device *pdev)
{
u32 v;
void __iomem *usb_base;
void __iomem *usbother_base;
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
if (!usb_base)
return -ENOMEM;
usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
/* Set the PHY clock to 19.2MHz */
v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
v |= MX51_USB_PLL_DIV_19_2_MHZ;
__raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
iounmap(usb_base);
mdelay(10);
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
}
static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
.init = initialize_otg_port,
.portsc = MXC_EHCI_UTMI_16BIT,
};
static int initialize_usbh1_port(struct platform_device *pdev)
{
iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27;
u32 v;
void __iomem *usb_base;
void __iomem *socregs_base;
mxc_iomux_v3_setup_pad(usbh1gpio);
gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp");
gpio_direction_output(EFIKAMX_USBH1_STP, 0);
msleep(1);
gpio_set_value(EFIKAMX_USBH1_STP, 1);
msleep(1);
usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
/* The clock for the USBH1 ULPI port will come externally */
/* from the PHY. */
v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET);
__raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
socregs_base + MX51_USB_CTRL_1_OFFSET);
iounmap(usb_base);
gpio_free(EFIKAMX_USBH1_STP);
mxc_iomux_v3_setup_pad(usbh1stp);
mdelay(10);
return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD);
}
static struct mxc_usbh_platform_data usbh1_config __initdata = {
.init = initialize_usbh1_port,
.portsc = MXC_EHCI_MODE_ULPI,
};
static void mx51_efika_hubreset(void)
{
gpio_request(EFIKAMX_USB_HUB_RESET, "usb_hub_rst");
gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1);
msleep(1);
gpio_set_value(EFIKAMX_USB_HUB_RESET, 0);
msleep(1);
gpio_set_value(EFIKAMX_USB_HUB_RESET, 1);
}
static void __init mx51_efika_usb(void)
{
mx51_efika_hubreset();
/* pulling it low, means no USB at all... */
gpio_request(EFIKA_USB_PHY_RESET, "usb_phy_reset");
gpio_direction_output(EFIKA_USB_PHY_RESET, 0);
msleep(1);
gpio_set_value(EFIKA_USB_PHY_RESET, 1);
usbh1_config.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT | ULPI_OTG_EXTVBUSIND);
imx51_add_mxc_ehci_otg(&dr_utmi_config);
if (usbh1_config.otg)
imx51_add_mxc_ehci_hs(1, &usbh1_config);
}
static struct mtd_partition mx51_efika_spi_nor_partitions[] = {
{
.name = "u-boot",
.offset = 0,
.size = SZ_256K,
},
{
.name = "config",
.offset = MTDPART_OFS_APPEND,
.size = SZ_64K,
},
};
static struct flash_platform_data mx51_efika_spi_flash_data = {
.name = "spi_flash",
.parts = mx51_efika_spi_nor_partitions,
.nr_parts = ARRAY_SIZE(mx51_efika_spi_nor_partitions),
.type = "sst25vf032b",
};
static struct regulator_consumer_supply sw1_consumers[] = {
{
.supply = "cpu_vcc",
}
};
static struct regulator_consumer_supply vdig_consumers[] = {
/* sgtl5000 */
REGULATOR_SUPPLY("VDDA", "1-000a"),
REGULATOR_SUPPLY("VDDD", "1-000a"),
};
static struct regulator_consumer_supply vvideo_consumers[] = {
/* sgtl5000 */
REGULATOR_SUPPLY("VDDIO", "1-000a"),
};
static struct regulator_consumer_supply vsd_consumers[] = {
REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
};
static struct regulator_consumer_supply pwgt1_consumer[] = {
{
.supply = "pwgt1",
}
};
static struct regulator_consumer_supply pwgt2_consumer[] = {
{
.supply = "pwgt2",
}
};
static struct regulator_consumer_supply coincell_consumer[] = {
{
.supply = "coincell",
}
};
static struct regulator_init_data sw1_init = {
.constraints = {
.name = "SW1",
.min_uV = 600000,
.max_uV = 1375000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.valid_modes_mask = 0,
.always_on = 1,
.boot_on = 1,
.state_mem = {
.uV = 850000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
},
.num_consumer_supplies = ARRAY_SIZE(sw1_consumers),
.consumer_supplies = sw1_consumers,
};
static struct regulator_init_data sw2_init = {
.constraints = {
.name = "SW2",
.min_uV = 900000,
.max_uV = 1850000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
.state_mem = {
.uV = 950000,
.mode = REGULATOR_MODE_NORMAL,
.enabled = 1,
},
}
};
static struct regulator_init_data sw3_init = {
.constraints = {
.name = "SW3",
.min_uV = 1100000,
.max_uV = 1850000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
}
};
static struct regulator_init_data sw4_init = {
.constraints = {
.name = "SW4",
.min_uV = 1100000,
.max_uV = 1850000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.always_on = 1,
.boot_on = 1,
}
};
static struct regulator_init_data viohi_init = {
.constraints = {
.name = "VIOHI",
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data vusb_init = {
.constraints = {
.name = "VUSB",
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data swbst_init = {
.constraints = {
.name = "SWBST",
}
};
static struct regulator_init_data vdig_init = {
.constraints = {
.name = "VDIG",
.min_uV = 1050000,
.max_uV = 1800000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(vdig_consumers),
.consumer_supplies = vdig_consumers,
};
static struct regulator_init_data vpll_init = {
.constraints = {
.name = "VPLL",
.min_uV = 1050000,
.max_uV = 1800000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data vusb2_init = {
.constraints = {
.name = "VUSB2",
.min_uV = 2400000,
.max_uV = 2775000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data vvideo_init = {
.constraints = {
.name = "VVIDEO",
.min_uV = 2775000,
.max_uV = 2775000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.apply_uV = 1,
},
.num_consumer_supplies = ARRAY_SIZE(vvideo_consumers),
.consumer_supplies = vvideo_consumers,
};
static struct regulator_init_data vaudio_init = {
.constraints = {
.name = "VAUDIO",
.min_uV = 2300000,
.max_uV = 3000000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
}
};
static struct regulator_init_data vsd_init = {
.constraints = {
.name = "VSD",
.min_uV = 1800000,
.max_uV = 3150000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(vsd_consumers),
.consumer_supplies = vsd_consumers,
};
static struct regulator_init_data vcam_init = {
.constraints = {
.name = "VCAM",
.min_uV = 2500000,
.max_uV = 3000000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
.valid_modes_mask = REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL,
.boot_on = 1,
}
};
static struct regulator_init_data vgen1_init = {
.constraints = {
.name = "VGEN1",
.min_uV = 1200000,
.max_uV = 3150000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data vgen2_init = {
.constraints = {
.name = "VGEN2",
.min_uV = 1200000,
.max_uV = 3150000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data vgen3_init = {
.constraints = {
.name = "VGEN3",
.min_uV = 1800000,
.max_uV = 2900000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_init_data gpo1_init = {
.constraints = {
.name = "GPO1",
}
};
static struct regulator_init_data gpo2_init = {
.constraints = {
.name = "GPO2",
}
};
static struct regulator_init_data gpo3_init = {
.constraints = {
.name = "GPO3",
}
};
static struct regulator_init_data gpo4_init = {
.constraints = {
.name = "GPO4",
}
};
static struct regulator_init_data pwgt1_init = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(pwgt1_consumer),
.consumer_supplies = pwgt1_consumer,
};
static struct regulator_init_data pwgt2_init = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
.boot_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(pwgt2_consumer),
.consumer_supplies = pwgt2_consumer,
};
static struct regulator_init_data vcoincell_init = {
.constraints = {
.name = "COINCELL",
.min_uV = 3000000,
.max_uV = 3000000,
.valid_ops_mask =
REGULATOR_CHANGE_VOLTAGE | REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(coincell_consumer),
.consumer_supplies = coincell_consumer,
};
static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
{ .id = MC13892_SW1, .init_data = &sw1_init },
{ .id = MC13892_SW2, .init_data = &sw2_init },
{ .id = MC13892_SW3, .init_data = &sw3_init },
{ .id = MC13892_SW4, .init_data = &sw4_init },
{ .id = MC13892_SWBST, .init_data = &swbst_init },
{ .id = MC13892_VIOHI, .init_data = &viohi_init },
{ .id = MC13892_VPLL, .init_data = &vpll_init },
{ .id = MC13892_VDIG, .init_data = &vdig_init },
{ .id = MC13892_VSD, .init_data = &vsd_init },
{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
{ .id = MC13892_VAUDIO, .init_data = &vaudio_init },
{ .id = MC13892_VCAM, .init_data = &vcam_init },
{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
{ .id = MC13892_VGEN3, .init_data = &vgen3_init },
{ .id = MC13892_VUSB, .init_data = &vusb_init },
{ .id = MC13892_GPO1, .init_data = &gpo1_init },
{ .id = MC13892_GPO2, .init_data = &gpo2_init },
{ .id = MC13892_GPO3, .init_data = &gpo3_init },
{ .id = MC13892_GPO4, .init_data = &gpo4_init },
{ .id = MC13892_PWGT1SPI, .init_data = &pwgt1_init },
{ .id = MC13892_PWGT2SPI, .init_data = &pwgt2_init },
{ .id = MC13892_VCOINCELL, .init_data = &vcoincell_init },
};
static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
.flags = MC13XXX_USE_RTC,
.regulators = {
.num_regulators = ARRAY_SIZE(mx51_efika_regulators),
.regulators = mx51_efika_regulators,
},
};
static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
{
.modalias = "m25p80",
.max_speed_hz = 25000000,
.bus_num = 0,
.chip_select = 1,
.platform_data = &mx51_efika_spi_flash_data,
.irq = -1,
},
{
.modalias = "mc13892",
.max_speed_hz = 1000000,
.bus_num = 0,
.chip_select = 0,
.platform_data = &mx51_efika_mc13892_data,
/* irq number is run-time assigned */
},
};
static int mx51_efika_spi_cs[] = {
EFIKAMX_SPI_CS0,
EFIKAMX_SPI_CS1,
};
static const struct spi_imx_master mx51_efika_spi_pdata __initconst = {
.chipselect = mx51_efika_spi_cs,
.num_chipselect = ARRAY_SIZE(mx51_efika_spi_cs),
};
void __init efika_board_common_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx51efika_pads,
ARRAY_SIZE(mx51efika_pads));
imx51_add_imx_uart(0, &uart_pdata);
mx51_efika_usb();
/* FIXME: comes from original code. check this. */
if (mx51_revision() < IMX_CHIP_REVISION_2_0)
sw2_init.constraints.state_mem.uV = 1100000;
else if (mx51_revision() == IMX_CHIP_REVISION_2_0) {
sw2_init.constraints.state_mem.uV = 1250000;
sw1_init.constraints.state_mem.uV = 1000000;
}
if (machine_is_mx51_efikasb())
vgen1_init.constraints.max_uV = 1200000;
gpio_request(EFIKAMX_PMIC, "pmic irq");
gpio_direction_input(EFIKAMX_PMIC);
mx51_efika_spi_board_info[1].irq = gpio_to_irq(EFIKAMX_PMIC);
spi_register_board_info(mx51_efika_spi_board_info,
ARRAY_SIZE(mx51_efika_spi_board_info));
imx51_add_ecspi(0, &mx51_efika_spi_pdata);
imx51_add_pata_imx();
#if defined(CONFIG_CPU_FREQ_IMX)
get_cpu_op = mx51_get_cpu_op;
#endif
}

6
arch/arm/plat-mxc/include/mach/common.h
View File

@ -52,7 +52,6 @@ extern void imx31_soc_init(void);
extern void imx35_soc_init(void);
extern void imx50_soc_init(void);
extern void imx51_soc_init(void);
extern void imx53_soc_init(void);
extern void imx51_init_late(void);
extern void imx53_init_late(void);
extern void epit_timer_init(void __iomem *base, int irq);
@ -137,11 +136,6 @@ extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
extern void imx51_babbage_common_init(void);
extern void imx53_ard_common_init(void);
extern void imx53_evk_common_init(void);
extern void imx53_qsb_common_init(void);
extern void imx53_smd_common_init(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_clock_map_io(void);

1219
arch/arm/plat-mxc/include/mach/iomux-mx53.h
View File

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