From b577a279914085c6b657c33e9f39ef56d96a3302 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sat, 4 Apr 2020 10:08:49 -0700 Subject: [PATCH 01/72] pinctrl: samsung: Correct setting of eint wakeup mask on s5pv210 Commit a8be2af0218c ("pinctrl: samsung: Write external wakeup interrupt mask") started writing the eint wakeup mask from the pinctrl driver. Unfortunately, it made the assumption that the private retention data was always a regmap while in the case of s5pv210 it is a raw pointer to the clock base (as the eint wakeup mask not in the PMU as with newer Exynos platforms). Fixes: a8be2af0218c ("pinctrl: samsung: Write external wakeup interrupt mask") Cc: Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-exynos.c | 73 ++++++++++++++++-------- 1 file changed, 49 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 0599f5127b01..5126a5a6d4c0 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -40,6 +40,8 @@ struct exynos_irq_chip { u32 eint_pend; u32 eint_wake_mask_value; u32 eint_wake_mask_reg; + void (*set_eint_wakeup_mask)(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip); }; static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) @@ -342,6 +344,47 @@ static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) return 0; } +static void +exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) +{ + struct regmap *pmu_regs; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + pmu_regs = drvdata->retention_ctrl->priv; + dev_info(drvdata->dev, + "Setting external wakeup interrupt mask: 0x%x\n", + irq_chip->eint_wake_mask_value); + + regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, + irq_chip->eint_wake_mask_value); +} + +static void +s5pv210_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, + struct exynos_irq_chip *irq_chip) + +{ + void __iomem *clk_base; + + if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { + dev_warn(drvdata->dev, + "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); + return; + } + + + clk_base = (void __iomem *) drvdata->retention_ctrl->priv; + + __raw_writel(irq_chip->eint_wake_mask_value, + clk_base + irq_chip->eint_wake_mask_reg); +} + /* * irq_chip for wakeup interrupts */ @@ -360,8 +403,9 @@ static const struct exynos_irq_chip s5pv210_wkup_irq_chip __initconst = { .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, - /* Only difference with exynos4210_wkup_irq_chip: */ + /* Only differences with exynos4210_wkup_irq_chip: */ .eint_wake_mask_reg = S5PV210_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = s5pv210_pinctrl_set_eint_wakeup_mask, }; static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { @@ -380,6 +424,7 @@ static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, .eint_wake_mask_reg = EXYNOS_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { @@ -398,6 +443,7 @@ static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, .eint_wake_mask_value = EXYNOS_EINT_WAKEUP_MASK_DISABLED, .eint_wake_mask_reg = EXYNOS5433_EINT_WAKEUP_MASK, + .set_eint_wakeup_mask = exynos_pinctrl_set_eint_wakeup_mask, }; /* list of external wakeup controllers supported */ @@ -574,27 +620,6 @@ int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) return 0; } -static void -exynos_pinctrl_set_eint_wakeup_mask(struct samsung_pinctrl_drv_data *drvdata, - struct exynos_irq_chip *irq_chip) -{ - struct regmap *pmu_regs; - - if (!drvdata->retention_ctrl || !drvdata->retention_ctrl->priv) { - dev_warn(drvdata->dev, - "No retention data configured bank with external wakeup interrupt. Wake-up mask will not be set.\n"); - return; - } - - pmu_regs = drvdata->retention_ctrl->priv; - dev_info(drvdata->dev, - "Setting external wakeup interrupt mask: 0x%x\n", - irq_chip->eint_wake_mask_value); - - regmap_write(pmu_regs, irq_chip->eint_wake_mask_reg, - irq_chip->eint_wake_mask_value); -} - static void exynos_pinctrl_suspend_bank( struct samsung_pinctrl_drv_data *drvdata, struct samsung_pin_bank *bank) @@ -626,8 +651,8 @@ void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) else if (bank->eint_type == EINT_TYPE_WKUP) { if (!irq_chip) { irq_chip = bank->irq_chip; - exynos_pinctrl_set_eint_wakeup_mask(drvdata, - irq_chip); + irq_chip->set_eint_wakeup_mask(drvdata, + irq_chip); } else if (bank->irq_chip != irq_chip) { dev_warn(drvdata->dev, "More than one external wakeup interrupt chip configured (bank: %s). This is not supported by hardware nor by driver.\n", From 36ad7b24486ae5e8705650d623cd2d998221f6ff Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 1 Apr 2020 20:35:01 +0300 Subject: [PATCH 02/72] pinctrl: cherryview: Re-use data structures from pinctrl-intel.h (part 2) We have some data structures duplicated across the drivers. Let's deduplicate them by using ones that being provided by pinctrl-intel.h. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 260 ++++++++------------- 1 file changed, 96 insertions(+), 164 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 4c74fdde576d..fa81f3c0bdc5 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -67,47 +67,6 @@ #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 #define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 -/** - * struct chv_alternate_function - A per group or per pin alternate function - * @pin: Pin number (only used in per pin configs) - * @mode: Mode the pin should be set in - * @invert_oe: Invert OE for this pin - */ -struct chv_alternate_function { - unsigned int pin; - u8 mode; - bool invert_oe; -}; - -/** - * struct chv_pincgroup - describes a CHV pin group - * @name: Name of the group - * @pins: An array of pins in this group - * @npins: Number of pins in this group - * @altfunc: Alternate function applied to all pins in this group - * @overrides: Alternate function override per pin or %NULL if not used - * @noverrides: Number of per pin alternate function overrides if - * @overrides != NULL. - */ -struct chv_pingroup { - const char *name; - const unsigned int *pins; - size_t npins; - struct chv_alternate_function altfunc; - const struct chv_alternate_function *overrides; - size_t noverrides; -}; - -/** - * struct chv_gpio_pinrange - A range of pins that can be used as GPIOs - * @base: Start pin number - * @npins: Number of pins in this range - */ -struct chv_gpio_pinrange { - unsigned int base; - unsigned int npins; -}; - /** * struct chv_community - A community specific configuration * @uid: ACPI _UID used to match the community @@ -117,8 +76,8 @@ struct chv_gpio_pinrange { * @ngroups: Number of groups * @functions: All functions in this community * @nfunctions: Number of functions - * @gpio_ranges: An array of GPIO ranges in this community - * @ngpio_ranges: Number of GPIO ranges + * @gpps: Pad groups + * @ngpps: Number of pad groups in this community * @nirqs: Total number of IRQs this community can generate * @acpi_space_id: An address space ID for ACPI OpRegion handler */ @@ -126,12 +85,12 @@ struct chv_community { const char *uid; const struct pinctrl_pin_desc *pins; size_t npins; - const struct chv_pingroup *groups; + const struct intel_pingroup *groups; size_t ngroups; const struct intel_function *functions; size_t nfunctions; - const struct chv_gpio_pinrange *gpio_ranges; - size_t ngpio_ranges; + const struct intel_padgroup *gpps; + size_t ngpps; size_t nirqs; acpi_adr_space_type acpi_space_id; }; @@ -173,37 +132,14 @@ struct chv_pinctrl { struct chv_pin_context *saved_pin_context; }; -#define ALTERNATE_FUNCTION(p, m, i) \ - { \ - .pin = (p), \ - .mode = (m), \ - .invert_oe = (i), \ - } +#define PINMODE_INVERT_OE BIT(15) -#define PIN_GROUP_WITH_ALT(n, p, m, i) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - } +#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) -#define PIN_GROUP_WITH_OVERRIDE(n, p, m, i, o) \ - { \ - .name = (n), \ - .pins = (p), \ - .npins = ARRAY_SIZE((p)), \ - .altfunc.mode = (m), \ - .altfunc.invert_oe = (i), \ - .overrides = (o), \ - .noverrides = ARRAY_SIZE((o)), \ - } - -#define GPIO_PINRANGE(start, end) \ +#define CHV_GPP(start, end) \ { \ .base = (start), \ - .npins = (end) - (start) + 1, \ + .size = (end) - (start) + 1, \ } static const struct pinctrl_pin_desc southwest_pins[] = { @@ -288,40 +224,37 @@ static const unsigned southwest_i2c6_pins[] = { 47, 51 }; static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; -/* LPE I2S TXD pins need to have invert_oe set */ -static const struct chv_alternate_function southwest_lpe_altfuncs[] = { - ALTERNATE_FUNCTION(30, 1, true), - ALTERNATE_FUNCTION(34, 1, true), - ALTERNATE_FUNCTION(97, 1, true), +/* Some of LPE I2S TXD pins need to have OE inversion set */ +static const unsigned int southwest_lpe_altfuncs[] = { + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ + PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ + PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ }; /* * Two spi3 chipselects are available in different mode than the main spi3 - * functionality, which is using mode 1. + * functionality, which is using mode 2. */ -static const struct chv_alternate_function southwest_spi3_altfuncs[] = { - ALTERNATE_FUNCTION(76, 3, false), - ALTERNATE_FUNCTION(80, 3, false), +static const unsigned int southwest_spi3_altfuncs[] = { + PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ + PINMODE(2, 0), /* 82 */ }; -static const struct chv_pingroup southwest_groups[] = { - PIN_GROUP_WITH_ALT("uart0_grp", southwest_uart0_pins, 2, false), - PIN_GROUP_WITH_ALT("uart1_grp", southwest_uart1_pins, 1, false), - PIN_GROUP_WITH_ALT("uart2_grp", southwest_uart2_pins, 1, false), - PIN_GROUP_WITH_ALT("hda_grp", southwest_hda_pins, 2, false), - PIN_GROUP_WITH_ALT("i2c0_grp", southwest_i2c0_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c1_grp", southwest_i2c1_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c2_grp", southwest_i2c2_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c3_grp", southwest_i2c3_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c4_grp", southwest_i2c4_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c5_grp", southwest_i2c5_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c6_grp", southwest_i2c6_pins, 1, true), - PIN_GROUP_WITH_ALT("i2c_nfc_grp", southwest_i2c_nfc_pins, 2, true), - - PIN_GROUP_WITH_OVERRIDE("lpe_grp", southwest_lpe_pins, 1, false, - southwest_lpe_altfuncs), - PIN_GROUP_WITH_OVERRIDE("spi3_grp", southwest_spi3_pins, 2, false, - southwest_spi3_altfuncs), +static const struct intel_pingroup southwest_groups[] = { + PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), + PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), + PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), + PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), + PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), + PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), + PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), + PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), + PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), + PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), + PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), + PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), + PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), + PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), }; static const char * const southwest_uart0_groups[] = { "uart0_grp" }; @@ -360,14 +293,14 @@ static const struct intel_function southwest_functions[] = { FUNCTION("spi3", southwest_spi3_groups), }; -static const struct chv_gpio_pinrange southwest_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 22), - GPIO_PINRANGE(30, 37), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 67), - GPIO_PINRANGE(75, 82), - GPIO_PINRANGE(90, 97), +static const struct intel_padgroup southwest_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 22), + CHV_GPP(30, 37), + CHV_GPP(45, 52), + CHV_GPP(60, 67), + CHV_GPP(75, 82), + CHV_GPP(90, 97), }; static const struct chv_community southwest_community = { @@ -378,8 +311,8 @@ static const struct chv_community southwest_community = { .ngroups = ARRAY_SIZE(southwest_groups), .functions = southwest_functions, .nfunctions = ARRAY_SIZE(southwest_functions), - .gpio_ranges = southwest_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southwest_gpio_ranges), + .gpps = southwest_gpps, + .ngpps = ARRAY_SIZE(southwest_gpps), /* * Southwest community can generate GPIO interrupts only for the * first 8 interrupts. The upper half (8-15) can only be used to @@ -455,20 +388,20 @@ static const struct pinctrl_pin_desc north_pins[] = { PINCTRL_PIN(72, "PANEL0_VDDEN"), }; -static const struct chv_gpio_pinrange north_gpio_ranges[] = { - GPIO_PINRANGE(0, 8), - GPIO_PINRANGE(15, 27), - GPIO_PINRANGE(30, 41), - GPIO_PINRANGE(45, 56), - GPIO_PINRANGE(60, 72), +static const struct intel_padgroup north_gpps[] = { + CHV_GPP(0, 8), + CHV_GPP(15, 27), + CHV_GPP(30, 41), + CHV_GPP(45, 56), + CHV_GPP(60, 72), }; static const struct chv_community north_community = { .uid = "2", .pins = north_pins, .npins = ARRAY_SIZE(north_pins), - .gpio_ranges = north_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(north_gpio_ranges), + .gpps = north_gpps, + .ngpps = ARRAY_SIZE(north_gpps), /* * North community can generate GPIO interrupts only for the first * 8 interrupts. The upper half (8-15) can only be used to trigger @@ -506,17 +439,17 @@ static const struct pinctrl_pin_desc east_pins[] = { PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), }; -static const struct chv_gpio_pinrange east_gpio_ranges[] = { - GPIO_PINRANGE(0, 11), - GPIO_PINRANGE(15, 26), +static const struct intel_padgroup east_gpps[] = { + CHV_GPP(0, 11), + CHV_GPP(15, 26), }; static const struct chv_community east_community = { .uid = "3", .pins = east_pins, .npins = ARRAY_SIZE(east_pins), - .gpio_ranges = east_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(east_gpio_ranges), + .gpps = east_gpps, + .ngpps = ARRAY_SIZE(east_gpps), .nirqs = 16, .acpi_space_id = 0x93, }; @@ -596,14 +529,14 @@ static const unsigned southeast_sdmmc3_pins[] = { static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; -static const struct chv_pingroup southeast_groups[] = { - PIN_GROUP_WITH_ALT("pwm0_grp", southeast_pwm0_pins, 1, false), - PIN_GROUP_WITH_ALT("pwm1_grp", southeast_pwm1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc1_grp", southeast_sdmmc1_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc2_grp", southeast_sdmmc2_pins, 1, false), - PIN_GROUP_WITH_ALT("sdmmc3_grp", southeast_sdmmc3_pins, 1, false), - PIN_GROUP_WITH_ALT("spi1_grp", southeast_spi1_pins, 1, false), - PIN_GROUP_WITH_ALT("spi2_grp", southeast_spi2_pins, 4, false), +static const struct intel_pingroup southeast_groups[] = { + PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), + PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), + PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), + PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), + PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), }; static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; @@ -624,13 +557,13 @@ static const struct intel_function southeast_functions[] = { FUNCTION("spi2", southeast_spi2_groups), }; -static const struct chv_gpio_pinrange southeast_gpio_ranges[] = { - GPIO_PINRANGE(0, 7), - GPIO_PINRANGE(15, 26), - GPIO_PINRANGE(30, 35), - GPIO_PINRANGE(45, 52), - GPIO_PINRANGE(60, 69), - GPIO_PINRANGE(75, 85), +static const struct intel_padgroup southeast_gpps[] = { + CHV_GPP(0, 7), + CHV_GPP(15, 26), + CHV_GPP(30, 35), + CHV_GPP(45, 52), + CHV_GPP(60, 69), + CHV_GPP(75, 85), }; static const struct chv_community southeast_community = { @@ -641,8 +574,8 @@ static const struct chv_community southeast_community = { .ngroups = ARRAY_SIZE(southeast_groups), .functions = southeast_functions, .nfunctions = ARRAY_SIZE(southeast_functions), - .gpio_ranges = southeast_gpio_ranges, - .ngpio_ranges = ARRAY_SIZE(southeast_gpio_ranges), + .gpps = southeast_gpps, + .ngpps = ARRAY_SIZE(southeast_gpps), .nirqs = 16, .acpi_space_id = 0x94, }; @@ -789,7 +722,7 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, unsigned int group) { struct chv_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - const struct chv_pingroup *grp; + const struct intel_pingroup *grp; unsigned long flags; int i; @@ -808,22 +741,21 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, } for (i = 0; i < grp->npins; i++) { - const struct chv_alternate_function *altfunc = &grp->altfunc; int pin = grp->pins[i]; void __iomem *reg; + unsigned int mode; + bool invert_oe; u32 value; /* Check if there is pin-specific config */ - if (grp->overrides) { - int j; + if (grp->modes) + mode = grp->modes[i]; + else + mode = grp->mode; - for (j = 0; j < grp->noverrides; j++) { - if (grp->overrides[j].pin == pin) { - altfunc = &grp->overrides[j]; - break; - } - } - } + /* Extract OE inversion */ + invert_oe = mode & PINMODE_INVERT_OE; + mode &= ~PINMODE_INVERT_OE; reg = chv_padreg(pctrl, pin, CHV_PADCTRL0); value = readl(reg); @@ -831,18 +763,18 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, value &= ~CHV_PADCTRL0_GPIOEN; /* Set to desired mode */ value &= ~CHV_PADCTRL0_PMODE_MASK; - value |= altfunc->mode << CHV_PADCTRL0_PMODE_SHIFT; + value |= mode << CHV_PADCTRL0_PMODE_SHIFT; chv_writel(value, reg); /* Update for invert_oe */ reg = chv_padreg(pctrl, pin, CHV_PADCTRL1); value = readl(reg) & ~CHV_PADCTRL1_INVRXTX_MASK; - if (altfunc->invert_oe) + if (invert_oe) value |= CHV_PADCTRL1_INVRXTX_TXENABLE; chv_writel(value, reg); dev_dbg(pctrl->dev, "configured pin %u mode %u OE %sinverted\n", - pin, altfunc->mode, altfunc->invert_oe ? "" : "not "); + pin, mode, invert_oe ? "" : "not "); } raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -1590,14 +1522,14 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) { struct chv_pinctrl *pctrl = gpiochip_get_data(chip); const struct chv_community *community = pctrl->community; - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; int ret, i; - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; ret = gpiochip_add_pin_range(chip, dev_name(pctrl->dev), - range->base, range->base, - range->npins); + gpp->base, gpp->base, + gpp->size); if (ret) { dev_err(pctrl->dev, "failed to add GPIO pin range\n"); return ret; @@ -1609,7 +1541,7 @@ static int chv_gpio_add_pin_ranges(struct gpio_chip *chip) static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) { - const struct chv_gpio_pinrange *range; + const struct intel_padgroup *gpp; struct gpio_chip *chip = &pctrl->chip; bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); const struct chv_community *community = pctrl->community; @@ -1657,12 +1589,12 @@ static int chv_gpio_probe(struct chv_pinctrl *pctrl, int irq) } if (!need_valid_mask) { - for (i = 0; i < community->ngpio_ranges; i++) { - range = &community->gpio_ranges[i]; + for (i = 0; i < community->ngpps; i++) { + gpp = &community->gpps[i]; irq_domain_associate_many(chip->irq.domain, irq_base, - range->base, range->npins); - irq_base += range->npins; + gpp->base, gpp->size); + irq_base += gpp->size; } } From 5707dd73c71bb442e1e617c5c7e8f55823fb7317 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Wed, 1 Apr 2020 20:35:02 +0300 Subject: [PATCH 03/72] pinctrl: cherryview: Use GENMASK() consistently Use GENMASK() macro for all definitions where it's appropriate. No functional change intended. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index fa81f3c0bdc5..53f2775f7184 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -35,18 +35,18 @@ #define CHV_PADCTRL0 0x000 #define CHV_PADCTRL0_INTSEL_SHIFT 28 -#define CHV_PADCTRL0_INTSEL_MASK (0xf << CHV_PADCTRL0_INTSEL_SHIFT) +#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) #define CHV_PADCTRL0_TERM_UP BIT(23) #define CHV_PADCTRL0_TERM_SHIFT 20 -#define CHV_PADCTRL0_TERM_MASK (7 << CHV_PADCTRL0_TERM_SHIFT) +#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) #define CHV_PADCTRL0_TERM_20K 1 #define CHV_PADCTRL0_TERM_5K 2 #define CHV_PADCTRL0_TERM_1K 4 #define CHV_PADCTRL0_PMODE_SHIFT 16 -#define CHV_PADCTRL0_PMODE_MASK (0xf << CHV_PADCTRL0_PMODE_SHIFT) +#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) #define CHV_PADCTRL0_GPIOEN BIT(15) #define CHV_PADCTRL0_GPIOCFG_SHIFT 8 -#define CHV_PADCTRL0_GPIOCFG_MASK (7 << CHV_PADCTRL0_GPIOCFG_SHIFT) +#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) #define CHV_PADCTRL0_GPIOCFG_GPIO 0 #define CHV_PADCTRL0_GPIOCFG_GPO 1 #define CHV_PADCTRL0_GPIOCFG_GPI 2 @@ -57,11 +57,11 @@ #define CHV_PADCTRL1 0x004 #define CHV_PADCTRL1_CFGLOCK BIT(31) #define CHV_PADCTRL1_INVRXTX_SHIFT 4 -#define CHV_PADCTRL1_INVRXTX_MASK (0xf << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INVRXTX_TXENABLE (2 << CHV_PADCTRL1_INVRXTX_SHIFT) +#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) +#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) +#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) #define CHV_PADCTRL1_ODEN BIT(3) -#define CHV_PADCTRL1_INVRXTX_RXDATA (4 << CHV_PADCTRL1_INVRXTX_SHIFT) -#define CHV_PADCTRL1_INTWAKECFG_MASK 7 +#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) #define CHV_PADCTRL1_INTWAKECFG_FALLING 1 #define CHV_PADCTRL1_INTWAKECFG_RISING 2 #define CHV_PADCTRL1_INTWAKECFG_BOTH 3 From e5a4ab6a55e2308aad546b594c0d8e5b71d21be9 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:20 +0300 Subject: [PATCH 04/72] pinctrl: intel: Introduce common flags for GPIO mapping scheme Few drivers are using the same flag to tell Intel pin control core how to interpret GPIO base. Provide a generic flags so all drivers can use. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 19 +++++++++++++------ drivers/pinctrl/intel/pinctrl-intel.h | 14 ++++++++++++-- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 74fdfd2b9ff5..a1b286dc7008 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -798,7 +798,7 @@ static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset, for (j = 0; j < comm->ngpps; j++) { const struct intel_padgroup *pgrp = &comm->gpps[j]; - if (pgrp->gpio_base < 0) + if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (offset >= pgrp->gpio_base && @@ -1138,7 +1138,7 @@ static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl, for (i = 0; i < community->ngpps; i++) { const struct intel_padgroup *gpp = &community->gpps[i]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), @@ -1180,7 +1180,7 @@ static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl) for (j = 0; j < community->ngpps; j++) { const struct intel_padgroup *gpp = &community->gpps[j]; - if (gpp->gpio_base < 0) + if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP) continue; if (gpp->gpio_base + gpp->size > ngpio) @@ -1276,8 +1276,15 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, if (gpps[i].size > 32) return -EINVAL; - if (!gpps[i].gpio_base) - gpps[i].gpio_base = gpps[i].base; + /* Special treatment for GPIO base */ + switch (gpps[i].gpio_base) { + case INTEL_GPIO_BASE_MATCH: + gpps[i].gpio_base = gpps[i].base; + break; + case INTEL_GPIO_BASE_NOMAP: + default: + break; + } gpps[i].padown_num = padown_num; @@ -1596,7 +1603,7 @@ static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c, struct device *dev = pctrl->dev; u32 requested; - if (padgrp->gpio_base < 0) + if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP) return; requested = intel_gpio_is_requested(&pctrl->chip, padgrp->gpio_base, padgrp->size); diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index c6f066f6d3fb..89f38fae6da7 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -53,8 +53,7 @@ struct intel_function { * @reg_num: GPI_IS register number * @base: Starting pin of this group * @size: Size of this group (maximum is 32). - * @gpio_base: Starting GPIO base of this group (%0 if matches with @base, - * and %-1 if no GPIO mapping should be created) + * @gpio_base: Starting GPIO base of this group * @padown_num: PAD_OWN register number (assigned by the core driver) * * If pad groups of a community are not the same size, use this structure @@ -68,6 +67,17 @@ struct intel_padgroup { unsigned int padown_num; }; +/** + * enum - Special treatment for GPIO base in pad group + * + * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created + * @INTEL_GPIO_BASE_MATCH: matches with starting pin number + */ +enum { + INTEL_GPIO_BASE_NOMAP = -1, + INTEL_GPIO_BASE_MATCH = 0, +}; + /** * struct intel_community - Intel pin community description * @barno: MMIO BAR number where registers for this community reside From 5ba092edb990b48b522355e7f8ae4be7c37cd7fa Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:21 +0300 Subject: [PATCH 05/72] pinctrl: cannonlake: Use generic flag for special GPIO base treatment Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cannonlake.c | 58 +++++++++++----------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cannonlake.c b/drivers/pinctrl/intel/pinctrl-cannonlake.c index f51b27bbf9f1..515f57a0d180 100644 --- a/drivers/pinctrl/intel/pinctrl-cannonlake.c +++ b/drivers/pinctrl/intel/pinctrl-cannonlake.c @@ -30,8 +30,6 @@ .gpio_base = (g), \ } -#define CNL_NO_GPIO -1 - #define CNL_COMMUNITY(b, s, e, o, g) \ { \ .barno = (b), \ @@ -377,27 +375,27 @@ static const struct intel_padgroup cnlh_community0_gpps[] = { }; static const struct intel_padgroup cnlh_community1_gpps[] = { - CNL_GPP(0, 51, 74, 64), /* GPP_C */ - CNL_GPP(1, 75, 98, 96), /* GPP_D */ - CNL_GPP(2, 99, 106, 128), /* GPP_G */ - CNL_GPP(3, 107, 114, CNL_NO_GPIO), /* AZA */ - CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ - CNL_GPP(5, 147, 154, CNL_NO_GPIO), /* vGPIO_1 */ + CNL_GPP(0, 51, 74, 64), /* GPP_C */ + CNL_GPP(1, 75, 98, 96), /* GPP_D */ + CNL_GPP(2, 99, 106, 128), /* GPP_G */ + CNL_GPP(3, 107, 114, INTEL_GPIO_BASE_NOMAP), /* AZA */ + CNL_GPP(4, 115, 146, 160), /* vGPIO_0 */ + CNL_GPP(5, 147, 154, INTEL_GPIO_BASE_NOMAP), /* vGPIO_1 */ }; static const struct intel_padgroup cnlh_community3_gpps[] = { - CNL_GPP(0, 155, 178, 192), /* GPP_K */ - CNL_GPP(1, 179, 202, 224), /* GPP_H */ - CNL_GPP(2, 203, 215, 256), /* GPP_E */ - CNL_GPP(3, 216, 239, 288), /* GPP_F */ - CNL_GPP(4, 240, 248, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 155, 178, 192), /* GPP_K */ + CNL_GPP(1, 179, 202, 224), /* GPP_H */ + CNL_GPP(2, 203, 215, 256), /* GPP_E */ + CNL_GPP(3, 216, 239, 288), /* GPP_F */ + CNL_GPP(4, 240, 248, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnlh_community4_gpps[] = { - CNL_GPP(0, 249, 259, CNL_NO_GPIO), /* CPU */ - CNL_GPP(1, 260, 268, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(2, 269, 286, 320), /* GPP_I */ - CNL_GPP(3, 287, 298, 352), /* GPP_J */ + CNL_GPP(0, 249, 259, INTEL_GPIO_BASE_NOMAP), /* CPU */ + CNL_GPP(1, 260, 268, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(2, 269, 286, 320), /* GPP_I */ + CNL_GPP(3, 287, 298, 352), /* GPP_J */ }; static const unsigned int cnlh_spi0_pins[] = { 40, 41, 42, 43 }; @@ -790,25 +788,25 @@ static const struct intel_function cnllp_functions[] = { }; static const struct intel_padgroup cnllp_community0_gpps[] = { - CNL_GPP(0, 0, 24, 0), /* GPP_A */ - CNL_GPP(1, 25, 50, 32), /* GPP_B */ - CNL_GPP(2, 51, 58, 64), /* GPP_G */ - CNL_GPP(3, 59, 67, CNL_NO_GPIO), /* SPI */ + CNL_GPP(0, 0, 24, 0), /* GPP_A */ + CNL_GPP(1, 25, 50, 32), /* GPP_B */ + CNL_GPP(2, 51, 58, 64), /* GPP_G */ + CNL_GPP(3, 59, 67, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_padgroup cnllp_community1_gpps[] = { - CNL_GPP(0, 68, 92, 96), /* GPP_D */ - CNL_GPP(1, 93, 116, 128), /* GPP_F */ - CNL_GPP(2, 117, 140, 160), /* GPP_H */ - CNL_GPP(3, 141, 172, 192), /* vGPIO */ - CNL_GPP(4, 173, 180, 224), /* vGPIO */ + CNL_GPP(0, 68, 92, 96), /* GPP_D */ + CNL_GPP(1, 93, 116, 128), /* GPP_F */ + CNL_GPP(2, 117, 140, 160), /* GPP_H */ + CNL_GPP(3, 141, 172, 192), /* vGPIO */ + CNL_GPP(4, 173, 180, 224), /* vGPIO */ }; static const struct intel_padgroup cnllp_community4_gpps[] = { - CNL_GPP(0, 181, 204, 256), /* GPP_C */ - CNL_GPP(1, 205, 228, 288), /* GPP_E */ - CNL_GPP(2, 229, 237, CNL_NO_GPIO), /* JTAG */ - CNL_GPP(3, 238, 243, CNL_NO_GPIO), /* HVCMOS */ + CNL_GPP(0, 181, 204, 256), /* GPP_C */ + CNL_GPP(1, 205, 228, 288), /* GPP_E */ + CNL_GPP(2, 229, 237, INTEL_GPIO_BASE_NOMAP), /* JTAG */ + CNL_GPP(3, 238, 243, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ }; static const struct intel_community cnllp_communities[] = { From cf2f2c3a445f9b45d5baaaf49b7752df33e5d44e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:22 +0300 Subject: [PATCH 06/72] pinctrl: icelake: Use generic flag for special GPIO base treatment Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-icelake.c | 30 ++++++++++++------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-icelake.c b/drivers/pinctrl/intel/pinctrl-icelake.c index 6489e9bbb61f..429b5a83acf0 100644 --- a/drivers/pinctrl/intel/pinctrl-icelake.c +++ b/drivers/pinctrl/intel/pinctrl-icelake.c @@ -29,8 +29,6 @@ .gpio_base = (g), \ } -#define ICL_NO_GPIO -1 - #define ICL_COMMUNITY(b, s, e, g) \ { \ .barno = (b), \ @@ -305,29 +303,29 @@ static const struct pinctrl_pin_desc icllp_pins[] = { }; static const struct intel_padgroup icllp_community0_gpps[] = { - ICL_GPP(0, 0, 7, 0), /* GPP_G */ - ICL_GPP(1, 8, 33, 32), /* GPP_B */ - ICL_GPP(2, 34, 58, 64), /* GPP_A */ + ICL_GPP(0, 0, 7, 0), /* GPP_G */ + ICL_GPP(1, 8, 33, 32), /* GPP_B */ + ICL_GPP(2, 34, 58, 64), /* GPP_A */ }; static const struct intel_padgroup icllp_community1_gpps[] = { - ICL_GPP(0, 59, 82, 96), /* GPP_H */ - ICL_GPP(1, 83, 103, 128), /* GPP_D */ - ICL_GPP(2, 104, 123, 160), /* GPP_F */ - ICL_GPP(3, 124, 152, 192), /* vGPIO */ + ICL_GPP(0, 59, 82, 96), /* GPP_H */ + ICL_GPP(1, 83, 103, 128), /* GPP_D */ + ICL_GPP(2, 104, 123, 160), /* GPP_F */ + ICL_GPP(3, 124, 152, 192), /* vGPIO */ }; static const struct intel_padgroup icllp_community4_gpps[] = { - ICL_GPP(0, 153, 176, 224), /* GPP_C */ - ICL_GPP(1, 177, 182, ICL_NO_GPIO), /* HVCMOS */ - ICL_GPP(2, 183, 206, 256), /* GPP_E */ - ICL_GPP(3, 207, 215, ICL_NO_GPIO), /* JTAG */ + ICL_GPP(0, 153, 176, 224), /* GPP_C */ + ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + ICL_GPP(2, 183, 206, 256), /* GPP_E */ + ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup icllp_community5_gpps[] = { - ICL_GPP(0, 216, 223, 288), /* GPP_R */ - ICL_GPP(1, 224, 231, 320), /* GPP_S */ - ICL_GPP(2, 232, 240, ICL_NO_GPIO), /* SPI */ + ICL_GPP(0, 216, 223, 288), /* GPP_R */ + ICL_GPP(1, 224, 231, 320), /* GPP_S */ + ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community icllp_communities[] = { From d4b41f8bb26d9c0d526784797a7ea77dba7ed21d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:23 +0300 Subject: [PATCH 07/72] pinctrl: tigerlake: Use generic flag for special GPIO base treatment Since we have a generic flag for special GPIO base treatment, use it in the driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-tigerlake.c | 32 +++++++++++------------ 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-tigerlake.c b/drivers/pinctrl/intel/pinctrl-tigerlake.c index 08a86f6fdea6..bcfd7548e282 100644 --- a/drivers/pinctrl/intel/pinctrl-tigerlake.c +++ b/drivers/pinctrl/intel/pinctrl-tigerlake.c @@ -21,8 +21,6 @@ #define TGL_GPI_IS 0x100 #define TGL_GPI_IE 0x120 -#define TGL_NO_GPIO -1 - #define TGL_GPP(r, s, e, g) \ { \ .reg_num = (r), \ @@ -342,30 +340,30 @@ static const struct pinctrl_pin_desc tgllp_pins[] = { }; static const struct intel_padgroup tgllp_community0_gpps[] = { - TGL_GPP(0, 0, 25, 0), /* GPP_B */ - TGL_GPP(1, 26, 41, 32), /* GPP_T */ - TGL_GPP(2, 42, 66, 64), /* GPP_A */ + TGL_GPP(0, 0, 25, 0), /* GPP_B */ + TGL_GPP(1, 26, 41, 32), /* GPP_T */ + TGL_GPP(2, 42, 66, 64), /* GPP_A */ }; static const struct intel_padgroup tgllp_community1_gpps[] = { - TGL_GPP(0, 67, 74, 96), /* GPP_S */ - TGL_GPP(1, 75, 98, 128), /* GPP_H */ - TGL_GPP(2, 99, 119, 160), /* GPP_D */ - TGL_GPP(3, 120, 143, 192), /* GPP_U */ - TGL_GPP(4, 144, 170, 224), /* vGPIO */ + TGL_GPP(0, 67, 74, 96), /* GPP_S */ + TGL_GPP(1, 75, 98, 128), /* GPP_H */ + TGL_GPP(2, 99, 119, 160), /* GPP_D */ + TGL_GPP(3, 120, 143, 192), /* GPP_U */ + TGL_GPP(4, 144, 170, 224), /* vGPIO */ }; static const struct intel_padgroup tgllp_community4_gpps[] = { - TGL_GPP(0, 171, 194, 256), /* GPP_C */ - TGL_GPP(1, 195, 219, 288), /* GPP_F */ - TGL_GPP(2, 220, 225, TGL_NO_GPIO), /* HVCMOS */ - TGL_GPP(3, 226, 250, 320), /* GPP_E */ - TGL_GPP(4, 251, 259, TGL_NO_GPIO), /* JTAG */ + TGL_GPP(0, 171, 194, 256), /* GPP_C */ + TGL_GPP(1, 195, 219, 288), /* GPP_F */ + TGL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + TGL_GPP(3, 226, 250, 320), /* GPP_E */ + TGL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ }; static const struct intel_padgroup tgllp_community5_gpps[] = { - TGL_GPP(0, 260, 267, 352), /* GPP_R */ - TGL_GPP(1, 268, 276, TGL_NO_GPIO), /* SPI */ + TGL_GPP(0, 260, 267, 352), /* GPP_R */ + TGL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ }; static const struct intel_community tgllp_communities[] = { From 9bd59157e16c64b45da5315f5b49b659fe51984b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:24 +0300 Subject: [PATCH 08/72] pinctrl: intel: Introduce new flag to force GPIO base to be 0 In some cases not the first group would like to have GPIO base to be 0. It's not possible right now due to 0 has special meaning already. Thus, introduce a new flag to allow drivers to force GPIO base to be 0 on a certain group. It's assumed that it can be only one group per device with such flag enabled. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.c | 3 +++ drivers/pinctrl/intel/pinctrl-intel.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index a1b286dc7008..6a274e20d926 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -1281,6 +1281,9 @@ static int intel_pinctrl_add_padgroups(struct intel_pinctrl *pctrl, case INTEL_GPIO_BASE_MATCH: gpps[i].gpio_base = gpps[i].base; break; + case INTEL_GPIO_BASE_ZERO: + gpps[i].gpio_base = 0; + break; case INTEL_GPIO_BASE_NOMAP: default: break; diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 89f38fae6da7..87fc0555ef90 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -70,10 +70,12 @@ struct intel_padgroup { /** * enum - Special treatment for GPIO base in pad group * + * @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0 * @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created * @INTEL_GPIO_BASE_MATCH: matches with starting pin number */ enum { + INTEL_GPIO_BASE_ZERO = -2, INTEL_GPIO_BASE_NOMAP = -1, INTEL_GPIO_BASE_MATCH = 0, }; From e278dcb7048b1a27b559e34b0f5f0e50f06221a2 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Mon, 13 Apr 2020 14:18:25 +0300 Subject: [PATCH 09/72] pinctrl: intel: Add Intel Jasper Lake pin controller support This driver adds pinctrl/GPIO support for Intel Jasper Lake SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Cc: Mika Westerberg Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/Kconfig | 8 + drivers/pinctrl/intel/Makefile | 1 + drivers/pinctrl/intel/pinctrl-jasperlake.c | 344 +++++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 drivers/pinctrl/intel/pinctrl-jasperlake.c diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig index ee440ec4c94c..787833e343a4 100644 --- a/drivers/pinctrl/intel/Kconfig +++ b/drivers/pinctrl/intel/Kconfig @@ -111,6 +111,14 @@ config PINCTRL_ICELAKE This pinctrl driver provides an interface that allows configuring of Intel Ice Lake PCH pins and using them as GPIOs. +config PINCTRL_JASPERLAKE + tristate "Intel Jasper Lake PCH pinctrl and GPIO driver" + depends on ACPI + select PINCTRL_INTEL + help + This pinctrl driver provides an interface that allows configuring + of Intel Jasper Lake PCH pins and using them as GPIOs. + config PINCTRL_LEWISBURG tristate "Intel Lewisburg pinctrl and GPIO driver" depends on ACPI diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile index f60f99cfa7aa..f6f63eb8100f 100644 --- a/drivers/pinctrl/intel/Makefile +++ b/drivers/pinctrl/intel/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_PINCTRL_CEDARFORK) += pinctrl-cedarfork.o obj-$(CONFIG_PINCTRL_DENVERTON) += pinctrl-denverton.o obj-$(CONFIG_PINCTRL_GEMINILAKE) += pinctrl-geminilake.o obj-$(CONFIG_PINCTRL_ICELAKE) += pinctrl-icelake.o +obj-$(CONFIG_PINCTRL_JASPERLAKE) += pinctrl-jasperlake.o obj-$(CONFIG_PINCTRL_LEWISBURG) += pinctrl-lewisburg.o obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o obj-$(CONFIG_PINCTRL_TIGERLAKE) += pinctrl-tigerlake.o diff --git a/drivers/pinctrl/intel/pinctrl-jasperlake.c b/drivers/pinctrl/intel/pinctrl-jasperlake.c new file mode 100644 index 000000000000..9bd0e8e6310c --- /dev/null +++ b/drivers/pinctrl/intel/pinctrl-jasperlake.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel Jasper Lake PCH pinctrl/GPIO driver + * + * Copyright (C) 2020, Intel Corporation + * Author: Andy Shevchenko + */ + +#include +#include +#include + +#include + +#include "pinctrl-intel.h" + +#define JSL_PAD_OWN 0x020 +#define JSL_PADCFGLOCK 0x080 +#define JSL_HOSTSW_OWN 0x0b0 +#define JSL_GPI_IS 0x100 +#define JSL_GPI_IE 0x120 + +#define JSL_GPP(r, s, e, g) \ + { \ + .reg_num = (r), \ + .base = (s), \ + .size = ((e) - (s) + 1), \ + .gpio_base = (g), \ + } + +#define JSL_COMMUNITY(b, s, e, g) \ + { \ + .barno = (b), \ + .padown_offset = JSL_PAD_OWN, \ + .padcfglock_offset = JSL_PADCFGLOCK, \ + .hostown_offset = JSL_HOSTSW_OWN, \ + .is_offset = JSL_GPI_IS, \ + .ie_offset = JSL_GPI_IE, \ + .pin_base = (s), \ + .npins = ((e) - (s) + 1), \ + .gpps = (g), \ + .ngpps = ARRAY_SIZE(g), \ + } + +/* Jasper Lake */ +static const struct pinctrl_pin_desc jsl_pins[] = { + /* GPP_F */ + PINCTRL_PIN(0, "CNV_BRI_DT_UART0_RTSB"), + PINCTRL_PIN(1, "CNV_BRI_RSP_UART0_RXD"), + PINCTRL_PIN(2, "EMMC_HIP_MON"), + PINCTRL_PIN(3, "CNV_RGI_RSP_UART0_CTSB"), + PINCTRL_PIN(4, "CNV_RF_RESET_B"), + PINCTRL_PIN(5, "MODEM_CLKREQ"), + PINCTRL_PIN(6, "CNV_PA_BLANKING"), + PINCTRL_PIN(7, "EMMC_CMD"), + PINCTRL_PIN(8, "EMMC_DATA0"), + PINCTRL_PIN(9, "EMMC_DATA1"), + PINCTRL_PIN(10, "EMMC_DATA2"), + PINCTRL_PIN(11, "EMMC_DATA3"), + PINCTRL_PIN(12, "EMMC_DATA4"), + PINCTRL_PIN(13, "EMMC_DATA5"), + PINCTRL_PIN(14, "EMMC_DATA6"), + PINCTRL_PIN(15, "EMMC_DATA7"), + PINCTRL_PIN(16, "EMMC_RCLK"), + PINCTRL_PIN(17, "EMMC_CLK"), + PINCTRL_PIN(18, "EMMC_RESETB"), + PINCTRL_PIN(19, "A4WP_PRESENT"), + /* GPP_B */ + PINCTRL_PIN(20, "CORE_VID_0"), + PINCTRL_PIN(21, "CORE_VID_1"), + PINCTRL_PIN(22, "VRALERTB"), + PINCTRL_PIN(23, "CPU_GP_2"), + PINCTRL_PIN(24, "CPU_GP_3"), + PINCTRL_PIN(25, "SRCCLKREQB_0"), + PINCTRL_PIN(26, "SRCCLKREQB_1"), + PINCTRL_PIN(27, "SRCCLKREQB_2"), + PINCTRL_PIN(28, "SRCCLKREQB_3"), + PINCTRL_PIN(29, "SRCCLKREQB_4"), + PINCTRL_PIN(30, "SRCCLKREQB_5"), + PINCTRL_PIN(31, "PMCALERTB"), + PINCTRL_PIN(32, "SLP_S0B"), + PINCTRL_PIN(33, "PLTRSTB"), + PINCTRL_PIN(34, "SPKR"), + PINCTRL_PIN(35, "GSPI0_CS0B"), + PINCTRL_PIN(36, "GSPI0_CLK"), + PINCTRL_PIN(37, "GSPI0_MISO"), + PINCTRL_PIN(38, "GSPI0_MOSI"), + PINCTRL_PIN(39, "GSPI1_CS0B"), + PINCTRL_PIN(40, "GSPI1_CLK"), + PINCTRL_PIN(41, "GSPI1_MISO"), + PINCTRL_PIN(42, "GSPI1_MOSI"), + PINCTRL_PIN(43, "DDSP_HPD_A"), + PINCTRL_PIN(44, "GSPI0_CLK_LOOPBK"), + PINCTRL_PIN(45, "GSPI1_CLK_LOOPBK"), + /* GPP_A */ + PINCTRL_PIN(46, "ESPI_IO_0"), + PINCTRL_PIN(47, "ESPI_IO_1"), + PINCTRL_PIN(48, "ESPI_IO_2"), + PINCTRL_PIN(49, "ESPI_IO_3"), + PINCTRL_PIN(50, "ESPI_CSB"), + PINCTRL_PIN(51, "ESPI_CLK"), + PINCTRL_PIN(52, "ESPI_RESETB"), + PINCTRL_PIN(53, "SMBCLK"), + PINCTRL_PIN(54, "SMBDATA"), + PINCTRL_PIN(55, "SMBALERTB"), + PINCTRL_PIN(56, "CPU_GP_0"), + PINCTRL_PIN(57, "CPU_GP_1"), + PINCTRL_PIN(58, "USB2_OCB_1"), + PINCTRL_PIN(59, "USB2_OCB_2"), + PINCTRL_PIN(60, "USB2_OCB_3"), + PINCTRL_PIN(61, "DDSP_HPD_A_TIME_SYNC_0"), + PINCTRL_PIN(62, "DDSP_HPD_B"), + PINCTRL_PIN(63, "DDSP_HPD_C"), + PINCTRL_PIN(64, "USB2_OCB_0"), + PINCTRL_PIN(65, "PCHHOTB"), + PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), + /* GPP_S */ + PINCTRL_PIN(67, "SNDW1_CLK"), + PINCTRL_PIN(68, "SNDW1_DATA"), + PINCTRL_PIN(69, "SNDW2_CLK"), + PINCTRL_PIN(70, "SNDW2_DATA"), + PINCTRL_PIN(71, "SNDW1_CLK"), + PINCTRL_PIN(72, "SNDW1_DATA"), + PINCTRL_PIN(73, "SNDW4_CLK_DMIC_CLK_0"), + PINCTRL_PIN(74, "SNDW4_DATA_DMIC_DATA_0"), + /* GPP_R */ + PINCTRL_PIN(75, "HDA_BCLK"), + PINCTRL_PIN(76, "HDA_SYNC"), + PINCTRL_PIN(77, "HDA_SDO"), + PINCTRL_PIN(78, "HDA_SDI_0"), + PINCTRL_PIN(79, "HDA_RSTB"), + PINCTRL_PIN(80, "HDA_SDI_1"), + PINCTRL_PIN(81, "I2S1_SFRM"), + PINCTRL_PIN(82, "I2S1_TXD"), + /* GPP_H */ + PINCTRL_PIN(83, "GPPC_H_0"), + PINCTRL_PIN(84, "SD_PWR_EN_B"), + PINCTRL_PIN(85, "MODEM_CLKREQ"), + PINCTRL_PIN(86, "SX_EXIT_HOLDOFFB"), + PINCTRL_PIN(87, "I2C2_SDA"), + PINCTRL_PIN(88, "I2C2_SCL"), + PINCTRL_PIN(89, "I2C3_SDA"), + PINCTRL_PIN(90, "I2C3_SCL"), + PINCTRL_PIN(91, "I2C4_SDA"), + PINCTRL_PIN(92, "I2C4_SCL"), + PINCTRL_PIN(93, "CPU_VCCIO_PWR_GATEB"), + PINCTRL_PIN(94, "I2S2_SCLK"), + PINCTRL_PIN(95, "I2S2_SFRM"), + PINCTRL_PIN(96, "I2S2_TXD"), + PINCTRL_PIN(97, "I2S2_RXD"), + PINCTRL_PIN(98, "I2S1_SCLK"), + PINCTRL_PIN(99, "GPPC_H_16"), + PINCTRL_PIN(100, "GPPC_H_17"), + PINCTRL_PIN(101, "GPPC_H_18"), + PINCTRL_PIN(102, "GPPC_H_19"), + PINCTRL_PIN(103, "GPPC_H_20"), + PINCTRL_PIN(104, "GPPC_H_21"), + PINCTRL_PIN(105, "GPPC_H_22"), + PINCTRL_PIN(106, "GPPC_H_23"), + /* GPP_D */ + PINCTRL_PIN(107, "SPI1_CSB"), + PINCTRL_PIN(108, "SPI1_CLK"), + PINCTRL_PIN(109, "SPI1_MISO_IO_1"), + PINCTRL_PIN(110, "SPI1_MOSI_IO_0"), + PINCTRL_PIN(111, "ISH_I2C0_SDA"), + PINCTRL_PIN(112, "ISH_I2C0_SCL"), + PINCTRL_PIN(113, "ISH_I2C1_SDA"), + PINCTRL_PIN(114, "ISH_I2C1_SCL"), + PINCTRL_PIN(115, "ISH_SPI_CSB"), + PINCTRL_PIN(116, "ISH_SPI_CLK"), + PINCTRL_PIN(117, "ISH_SPI_MISO"), + PINCTRL_PIN(118, "ISH_SPI_MOSI"), + PINCTRL_PIN(119, "ISH_UART0_RXD"), + PINCTRL_PIN(120, "ISH_UART0_TXD"), + PINCTRL_PIN(121, "ISH_UART0_RTSB"), + PINCTRL_PIN(122, "ISH_UART0_CTSB"), + PINCTRL_PIN(123, "SPI1_IO_2"), + PINCTRL_PIN(124, "SPI1_IO_3"), + PINCTRL_PIN(125, "I2S_MCLK"), + PINCTRL_PIN(126, "CNV_MFUART2_RXD"), + PINCTRL_PIN(127, "CNV_MFUART2_TXD"), + PINCTRL_PIN(128, "CNV_PA_BLANKING"), + PINCTRL_PIN(129, "I2C5_SDA"), + PINCTRL_PIN(130, "I2C5_SCL"), + PINCTRL_PIN(131, "GSPI2_CLK_LOOPBK"), + PINCTRL_PIN(132, "SPI1_CLK_LOOPBK"), + /* vGPIO */ + PINCTRL_PIN(133, "CNV_BTEN"), + PINCTRL_PIN(134, "CNV_WCEN"), + PINCTRL_PIN(135, "CNV_BT_HOST_WAKEB"), + PINCTRL_PIN(136, "CNV_BT_IF_SELECT"), + PINCTRL_PIN(137, "vCNV_BT_UART_TXD"), + PINCTRL_PIN(138, "vCNV_BT_UART_RXD"), + PINCTRL_PIN(139, "vCNV_BT_UART_CTS_B"), + PINCTRL_PIN(140, "vCNV_BT_UART_RTS_B"), + PINCTRL_PIN(141, "vCNV_MFUART1_TXD"), + PINCTRL_PIN(142, "vCNV_MFUART1_RXD"), + PINCTRL_PIN(143, "vCNV_MFUART1_CTS_B"), + PINCTRL_PIN(144, "vCNV_MFUART1_RTS_B"), + PINCTRL_PIN(145, "vUART0_TXD"), + PINCTRL_PIN(146, "vUART0_RXD"), + PINCTRL_PIN(147, "vUART0_CTS_B"), + PINCTRL_PIN(148, "vUART0_RTS_B"), + PINCTRL_PIN(149, "vISH_UART0_TXD"), + PINCTRL_PIN(150, "vISH_UART0_RXD"), + PINCTRL_PIN(151, "vISH_UART0_CTS_B"), + PINCTRL_PIN(152, "vISH_UART0_RTS_B"), + PINCTRL_PIN(153, "vCNV_BT_I2S_BCLK"), + PINCTRL_PIN(154, "vCNV_BT_I2S_WS_SYNC"), + PINCTRL_PIN(155, "vCNV_BT_I2S_SDO"), + PINCTRL_PIN(156, "vCNV_BT_I2S_SDI"), + PINCTRL_PIN(157, "vI2S2_SCLK"), + PINCTRL_PIN(158, "vI2S2_SFRM"), + PINCTRL_PIN(159, "vI2S2_TXD"), + PINCTRL_PIN(160, "vI2S2_RXD"), + PINCTRL_PIN(161, "vSD3_CD_B"), + /* GPP_C */ + PINCTRL_PIN(162, "GPPC_C_0"), + PINCTRL_PIN(163, "GPPC_C_1"), + PINCTRL_PIN(164, "GPPC_C_2"), + PINCTRL_PIN(165, "GPPC_C_3"), + PINCTRL_PIN(166, "GPPC_C_4"), + PINCTRL_PIN(167, "GPPC_C_5"), + PINCTRL_PIN(168, "SUSWARNB_SUSPWRDNACK"), + PINCTRL_PIN(169, "SUSACKB"), + PINCTRL_PIN(170, "UART0_RXD"), + PINCTRL_PIN(171, "UART0_TXD"), + PINCTRL_PIN(172, "UART0_RTSB"), + PINCTRL_PIN(173, "UART0_CTSB"), + PINCTRL_PIN(174, "UART1_RXD"), + PINCTRL_PIN(175, "UART1_TXD"), + PINCTRL_PIN(176, "UART1_RTSB"), + PINCTRL_PIN(177, "UART1_CTSB"), + PINCTRL_PIN(178, "I2C0_SDA"), + PINCTRL_PIN(179, "I2C0_SCL"), + PINCTRL_PIN(180, "I2C1_SDA"), + PINCTRL_PIN(181, "I2C1_SCL"), + PINCTRL_PIN(182, "UART2_RXD"), + PINCTRL_PIN(183, "UART2_TXD"), + PINCTRL_PIN(184, "UART2_RTSB"), + PINCTRL_PIN(185, "UART2_CTSB"), + /* HVCMOS */ + PINCTRL_PIN(186, "L_BKLTEN"), + PINCTRL_PIN(187, "L_BKLTCTL"), + PINCTRL_PIN(188, "L_VDDEN"), + PINCTRL_PIN(189, "SYS_PWROK"), + PINCTRL_PIN(190, "SYS_RESETB"), + PINCTRL_PIN(191, "MLK_RSTB"), + /* GPP_E */ + PINCTRL_PIN(192, "ISH_GP_0"), + PINCTRL_PIN(193, "ISH_GP_1"), + PINCTRL_PIN(194, "IMGCLKOUT_1"), + PINCTRL_PIN(195, "ISH_GP_2"), + PINCTRL_PIN(196, "IMGCLKOUT_2"), + PINCTRL_PIN(197, "SATA_LEDB"), + PINCTRL_PIN(198, "IMGCLKOUT_3"), + PINCTRL_PIN(199, "ISH_GP_3"), + PINCTRL_PIN(200, "ISH_GP_4"), + PINCTRL_PIN(201, "ISH_GP_5"), + PINCTRL_PIN(202, "ISH_GP_6"), + PINCTRL_PIN(203, "ISH_GP_7"), + PINCTRL_PIN(204, "IMGCLKOUT_4"), + PINCTRL_PIN(205, "DDPA_CTRLCLK"), + PINCTRL_PIN(206, "DDPA_CTRLDATA"), + PINCTRL_PIN(207, "DDPB_CTRLCLK"), + PINCTRL_PIN(208, "DDPB_CTRLDATA"), + PINCTRL_PIN(209, "DDPC_CTRLCLK"), + PINCTRL_PIN(210, "DDPC_CTRLDATA"), + PINCTRL_PIN(211, "IMGCLKOUT_5"), + PINCTRL_PIN(212, "CNV_BRI_DT"), + PINCTRL_PIN(213, "CNV_BRI_RSP"), + PINCTRL_PIN(214, "CNV_RGI_DT"), + PINCTRL_PIN(215, "CNV_RGI_RSP"), + /* GPP_G */ + PINCTRL_PIN(216, "SD3_CMD"), + PINCTRL_PIN(217, "SD3_D0"), + PINCTRL_PIN(218, "SD3_D1"), + PINCTRL_PIN(219, "SD3_D2"), + PINCTRL_PIN(220, "SD3_D3"), + PINCTRL_PIN(221, "SD3_CDB"), + PINCTRL_PIN(222, "SD3_CLK"), + PINCTRL_PIN(223, "SD3_WP"), +}; + +static const struct intel_padgroup jsl_community0_gpps[] = { + JSL_GPP(0, 0, 19, 320), /* GPP_F */ + JSL_GPP(1, 20, 45, 32), /* GPP_B */ + JSL_GPP(2, 46, 66, 64), /* GPP_A */ + JSL_GPP(3, 67, 74, 96), /* GPP_S */ + JSL_GPP(4, 75, 82, 128), /* GPP_R */ +}; + +static const struct intel_padgroup jsl_community1_gpps[] = { + JSL_GPP(0, 83, 106, 160), /* GPP_H */ + JSL_GPP(1, 107, 132, 192), /* GPP_D */ + JSL_GPP(2, 133, 161, 224), /* vGPIO */ + JSL_GPP(3, 162, 185, 256), /* GPP_C */ +}; + +static const struct intel_padgroup jsl_community4_gpps[] = { + JSL_GPP(0, 186, 191, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ + JSL_GPP(1, 192, 215, 288), /* GPP_E */ +}; + +static const struct intel_padgroup jsl_community5_gpps[] = { + JSL_GPP(0, 216, 223, INTEL_GPIO_BASE_ZERO), /* GPP_G */ +}; + +static const struct intel_community jsl_communities[] = { + JSL_COMMUNITY(0, 0, 82, jsl_community0_gpps), + JSL_COMMUNITY(1, 83, 185, jsl_community1_gpps), + JSL_COMMUNITY(2, 186, 215, jsl_community4_gpps), + JSL_COMMUNITY(3, 216, 223, jsl_community5_gpps), +}; + +static const struct intel_pinctrl_soc_data jsl_soc_data = { + .pins = jsl_pins, + .npins = ARRAY_SIZE(jsl_pins), + .communities = jsl_communities, + .ncommunities = ARRAY_SIZE(jsl_communities), +}; + +static const struct acpi_device_id jsl_pinctrl_acpi_match[] = { + { "INT34C8", (kernel_ulong_t)&jsl_soc_data }, + { } +}; +MODULE_DEVICE_TABLE(acpi, jsl_pinctrl_acpi_match); + +static INTEL_PINCTRL_PM_OPS(jsl_pinctrl_pm_ops); + +static struct platform_driver jsl_pinctrl_driver = { + .probe = intel_pinctrl_probe_by_hid, + .driver = { + .name = "jasperlake-pinctrl", + .acpi_match_table = jsl_pinctrl_acpi_match, + .pm = &jsl_pinctrl_pm_ops, + }, +}; + +module_platform_driver(jsl_pinctrl_driver); + +MODULE_AUTHOR("Andy Shevchenko "); +MODULE_DESCRIPTION("Intel Jasper Lake PCH pinctrl/GPIO driver"); +MODULE_LICENSE("GPL v2"); From f86a1bb536064a431c36d4333f4a2295b2419477 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 14 Apr 2020 19:13:37 +0300 Subject: [PATCH 10/72] pinctrl: baytrail: Use platform_get_irq_optional() explicitly There is no need to repeat functionality of platform_get_irq_optional() in the driver. Replace it with explicit call to the helper. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-baytrail.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-baytrail.c b/drivers/pinctrl/intel/pinctrl-baytrail.c index 9b821c9cbd16..0ff7c55173da 100644 --- a/drivers/pinctrl/intel/pinctrl-baytrail.c +++ b/drivers/pinctrl/intel/pinctrl-baytrail.c @@ -1506,8 +1506,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) { struct platform_device *pdev = to_platform_device(vg->dev); struct gpio_chip *gc; - struct resource *irq_rc; - int ret; + int irq, ret; /* Set up gpio chip */ vg->chip = byt_gpio_chip; @@ -1527,8 +1526,8 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) #endif /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; vg->irqchip.name = "BYT-GPIO", @@ -1548,7 +1547,7 @@ static int byt_gpio_probe(struct intel_pinctrl *vg) sizeof(*girq->parents), GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } From 7e23ab72e73bc601b4cf2983382691d9f165c8d1 Mon Sep 17 00:00:00 2001 From: Ding Xiang Date: Mon, 30 Mar 2020 15:56:26 +0800 Subject: [PATCH 11/72] pinctrl: nomadik:remove unneeded variable ret is unneeded, just return 0. Signed-off-by: Ding Xiang Link: https://lore.kernel.org/r/1585554986-26521-1-git-send-email-dingxiang@cmss.chinamobile.com Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik.c b/drivers/pinctrl/nomadik/pinctrl-nomadik.c index ca7bbe4164c0..ba25c4654391 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik.c @@ -1343,8 +1343,6 @@ static const struct nmk_cfg_param nmk_cfg_params[] = { static int nmk_dt_pin_config(int index, int val, unsigned long *config) { - int ret = 0; - if (nmk_cfg_params[index].choice == NULL) *config = nmk_cfg_params[index].config; else { @@ -1354,7 +1352,7 @@ static int nmk_dt_pin_config(int index, int val, unsigned long *config) nmk_cfg_params[index].choice[val]; } } - return ret; + return 0; } static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name) From 8174a8512e3e5acbf9e2202b24934b7f7fd28e13 Mon Sep 17 00:00:00 2001 From: Light Hsieh Date: Wed, 8 Apr 2020 04:08:16 +0800 Subject: [PATCH 12/72] pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module In the future we want to be able to build the MediaTek pinctrl driver, based on paris, as kernel module. This patch allows pinctrl-paris.c, the external interrupt controller mtk-eint.c, and pinctrl-mtk-common-v2.c to be loadable as module. Signed-off-by: Sean Wang Signed-off-by: Light Hsieh Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/9feeb04805e5a406fe22a92e3f280abda39ddda4.1586289920.git.sean.wang@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 11 +++++++-- drivers/pinctrl/mediatek/Makefile | 5 ++-- drivers/pinctrl/mediatek/mtk-eint.c | 9 +++++++ .../pinctrl/mediatek/pinctrl-mtk-common-v2.c | 24 +++++++++++++++++++ drivers/pinctrl/mediatek/pinctrl-paris.c | 6 +++++ 5 files changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 701f9af63f5e..551ac716b10c 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -3,10 +3,12 @@ menu "MediaTek pinctrl drivers" depends on ARCH_MEDIATEK || COMPILE_TEST config EINT_MTK - bool "MediaTek External Interrupt Support" + tristate "MediaTek External Interrupt Support" depends on PINCTRL_MTK || PINCTRL_MTK_MOORE || PINCTRL_MTK_PARIS || COMPILE_TEST select GPIOLIB select IRQ_DOMAIN + default y if PINCTRL_MTK || PINCTRL_MTK_MOORE + default PINCTRL_MTK_PARIS config PINCTRL_MTK bool @@ -17,6 +19,9 @@ config PINCTRL_MTK select EINT_MTK select OF_GPIO +config PINCTRL_MTK_V2 + tristate + config PINCTRL_MTK_MOORE bool depends on OF @@ -25,15 +30,17 @@ config PINCTRL_MTK_MOORE select GENERIC_PINMUX_FUNCTIONS select GPIOLIB select OF_GPIO + select PINCTRL_MTK_V2 config PINCTRL_MTK_PARIS - bool + tristate depends on OF select PINMUX select GENERIC_PINCONF select GPIOLIB select EINT_MTK select OF_GPIO + select PINCTRL_MTK_V2 # For ARMv7 SoCs config PINCTRL_MT2701 diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile index a74325abd877..4b7132876e71 100644 --- a/drivers/pinctrl/mediatek/Makefile +++ b/drivers/pinctrl/mediatek/Makefile @@ -2,8 +2,9 @@ # Core obj-$(CONFIG_EINT_MTK) += mtk-eint.o obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o -obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o pinctrl-mtk-common-v2.o -obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_V2) += pinctrl-mtk-common-v2.o +obj-$(CONFIG_PINCTRL_MTK_MOORE) += pinctrl-moore.o +obj-$(CONFIG_PINCTRL_MTK_PARIS) += pinctrl-paris.o # SoC Drivers obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o diff --git a/drivers/pinctrl/mediatek/mtk-eint.c b/drivers/pinctrl/mediatek/mtk-eint.c index 7e526bcf5e0b..22736f60c16c 100644 --- a/drivers/pinctrl/mediatek/mtk-eint.c +++ b/drivers/pinctrl/mediatek/mtk-eint.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include @@ -379,6 +380,7 @@ int mtk_eint_do_suspend(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_suspend); int mtk_eint_do_resume(struct mtk_eint *eint) { @@ -386,6 +388,7 @@ int mtk_eint_do_resume(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_resume); int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, unsigned int debounce) @@ -440,6 +443,7 @@ int mtk_eint_set_debounce(struct mtk_eint *eint, unsigned long eint_num, return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_set_debounce); int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) { @@ -451,6 +455,7 @@ int mtk_eint_find_irq(struct mtk_eint *eint, unsigned long eint_n) return irq; } +EXPORT_SYMBOL_GPL(mtk_eint_find_irq); int mtk_eint_do_init(struct mtk_eint *eint) { @@ -495,3 +500,7 @@ int mtk_eint_do_init(struct mtk_eint *eint) return 0; } +EXPORT_SYMBOL_GPL(mtk_eint_do_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek EINT Driver"); diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index d3169a87e1b3..6ea40b501328 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include "mtk-eint.h" @@ -204,6 +205,7 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_set_value); int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int field, int *value) @@ -223,6 +225,7 @@ int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, return 0; } +EXPORT_SYMBOL_GPL(mtk_hw_get_value); static int mtk_xt_find_eint_num(struct mtk_pinctrl *hw, unsigned long eint_n) { @@ -361,6 +364,7 @@ int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev) return mtk_eint_do_init(hw->eint); } +EXPORT_SYMBOL_GPL(mtk_build_eint); /* Revision 0 */ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, @@ -380,6 +384,7 @@ int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set); int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -402,6 +407,7 @@ int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get); int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -421,6 +427,7 @@ int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set); int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, int *res) @@ -440,6 +447,7 @@ int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get); /* Revision 1 */ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, @@ -454,6 +462,7 @@ int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_set_rev1); int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *res) @@ -471,6 +480,7 @@ int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_disable_get_rev1); int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup) @@ -490,6 +500,7 @@ int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_rev1); int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -515,6 +526,7 @@ int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_rev1); /* Combo for the following pull register type: * 1. PU + PD @@ -715,6 +727,7 @@ int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_set_combo); int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, @@ -735,6 +748,7 @@ int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, out: return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_bias_get_combo); /* Revision 0 */ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, @@ -764,6 +778,7 @@ int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set); int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -788,6 +803,7 @@ int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get); /* Revision 1 */ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, @@ -809,6 +825,7 @@ int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_rev1); int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) @@ -826,18 +843,21 @@ int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_rev1); int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) { return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DRV, arg); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_set_raw); int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, int *val) { return mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DRV, val); } +EXPORT_SYMBOL_GPL(mtk_pinconf_drive_get_raw); int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -878,6 +898,7 @@ int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_set); int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, bool pullup, @@ -920,6 +941,7 @@ int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_pull_get); int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 arg) @@ -946,6 +968,7 @@ int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, return err; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_set); int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, u32 *val) @@ -969,3 +992,4 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, return 0; } +EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c index 3853ec3a2a8e..d006ce4c9238 100644 --- a/drivers/pinctrl/mediatek/pinctrl-paris.c +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c @@ -10,6 +10,7 @@ */ #include +#include #include #include "pinctrl-paris.h" @@ -633,6 +634,7 @@ ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw, return len; } +EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin); #define PIN_DBG_BUF_SZ 96 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, @@ -1021,6 +1023,7 @@ int mtk_paris_pinctrl_probe(struct platform_device *pdev, return 0; } +EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe); static int mtk_paris_pinctrl_suspend(struct device *device) { @@ -1040,3 +1043,6 @@ const struct dev_pm_ops mtk_paris_pinctrl_pm_ops = { .suspend_noirq = mtk_paris_pinctrl_suspend, .resume_noirq = mtk_paris_pinctrl_resume, }; + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris"); From 9c95f7c2836c19cd243fb55f17643e6757e11405 Mon Sep 17 00:00:00 2001 From: Light Hsieh Date: Wed, 8 Apr 2020 04:08:17 +0800 Subject: [PATCH 13/72] pinctrl: mediatek: make MediaTek MT6765 pinctrl ready for buiding loadable module This patch make pinctrl-mt6765 ready for building as loadable module. Signed-off-by: Sean Wang Signed-off-by: Light Hsieh Link: https://lore.kernel.org/r/42100afe6f97d28447c153bea6b54ea556cf95ca.1586289920.git.sean.wang@mediatek.com Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/Kconfig | 2 +- drivers/pinctrl/mediatek/pinctrl-mt6765.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index 551ac716b10c..f32d3644c509 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -87,7 +87,7 @@ config PINCTRL_MT2712 select PINCTRL_MTK config PINCTRL_MT6765 - bool "Mediatek MT6765 pin control" + tristate "Mediatek MT6765 pin control" depends on OF depends on ARM64 || COMPILE_TEST default ARM64 && ARCH_MEDIATEK diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c index 905dae8c3fd8..2c59d3936256 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c @@ -6,6 +6,7 @@ * */ +#include #include "pinctrl-mtk-mt6765.h" #include "pinctrl-paris.h" @@ -1103,3 +1104,6 @@ static int __init mt6765_pinctrl_init(void) return platform_driver_register(&mt6765_pinctrl_driver); } arch_initcall(mt6765_pinctrl_init); + +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("MediaTek MT6765 Pinctrl Driver"); From 39eb3cc8ab8a5cb7b0a2b728cb653e58319449e9 Mon Sep 17 00:00:00 2001 From: Corentin Labbe Date: Thu, 2 Apr 2020 09:08:52 +0000 Subject: [PATCH 14/72] pinctrl: sunxi: handle probe defferal When checking the logs on my sun8i-a33-olinuxino I saw: sun8i-a23-r-pinctrl 1f02c00.pinctrl: Reset controller missing but this driver was working after. This message is just here because the reset controller was still not probed. So don't say anything if the return code say to wait. Signed-off-by: Corentin Labbe Link: https://lore.kernel.org/r/1585818532-23051-1-git-send-email-clabbe@baylibre.com Acked-by: Maxime Ripard Signed-off-by: Linus Walleij --- drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c index 8a08c4afc6a8..9e5b61449999 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c @@ -103,8 +103,11 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev) rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); if (IS_ERR(rstc)) { - dev_err(&pdev->dev, "Reset controller missing\n"); - return PTR_ERR(rstc); + ret = PTR_ERR(rstc); + if (ret == -EPROBE_DEFER) + return ret; + dev_err(&pdev->dev, "Reset controller missing err=%d\n", ret); + return ret; } ret = reset_control_deassert(rstc); From 087905f925c93131611d78526fb40e90cd7e7731 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 27 Mar 2020 18:55:57 +0800 Subject: [PATCH 15/72] dt-bindings: arm: fsl-scu: Add imx8dxl pinctrl support Update binding doc to support i.MX8DXL pinctrl. Signed-off-by: Anson Huang Acked-by: Rob Herring Link: https://lore.kernel.org/r/1585306559-13973-1-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index 623fedf12180..715047444391 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -108,7 +108,8 @@ This binding uses the i.MX common pinctrl binding[3]. Required properties: - compatible: Should be one of: "fsl,imx8qm-iomuxc", - "fsl,imx8qxp-iomuxc". + "fsl,imx8qxp-iomuxc", + "fsl,imx8dxl-iomuxc". Required properties for Pinctrl sub nodes: - fsl,pins: Each entry consists of 3 integers which represents @@ -116,7 +117,8 @@ Required properties for Pinctrl sub nodes: integers are specified using a PIN_FUNC_ID macro, which can be found in , - . + , + . The last integer CONFIG is the pad setting value like pull-up on this pin. From f9a8744dde48f368768b3a6de389b7ec2751d192 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 27 Mar 2020 18:55:58 +0800 Subject: [PATCH 16/72] pinctrl: imx: Add imx8dxl driver i.MX8DXL contains a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol, add support for the SCU based i.MX8DXL pinctrl driver. Signed-off-by: Anson Huang Link: https://lore.kernel.org/r/1585306559-13973-2-git-send-email-Anson.Huang@nxp.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/Kconfig | 7 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx8dxl.c | 193 ++++++ include/dt-bindings/pinctrl/pads-imx8dxl.h | 639 ++++++++++++++++++++ 4 files changed, 840 insertions(+) create mode 100644 drivers/pinctrl/freescale/pinctrl-imx8dxl.c create mode 100644 include/dt-bindings/pinctrl/pads-imx8dxl.h diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index c784663b00ad..4ca44dd69e53 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -165,6 +165,13 @@ config PINCTRL_IMX8QXP help Say Y here to enable the imx8qxp pinctrl driver +config PINCTRL_IMX8DXL + bool "IMX8DXL pinctrl driver" + depends on IMX_SCU && ARCH_MXC && ARM64 + select PINCTRL_IMX_SCU + help + Say Y here to enable the imx8dxl pinctrl driver + config PINCTRL_VF610 bool "Freescale Vybrid VF610 pinctrl driver" depends on SOC_VF610 diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 0ebd3af21e4d..c61722565289 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_PINCTRL_IMX8MP) += pinctrl-imx8mp.o obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o +obj-$(CONFIG_PINCTRL_IMX8DXL) += pinctrl-imx8dxl.o obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx8dxl.c b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c new file mode 100644 index 000000000000..7f32e57b7f6a --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-imx8dxl.c @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019~2020 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "pinctrl-imx.h" + +static const struct pinctrl_pin_desc imx8dxl_pinctrl_pads[] = { + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_PERST_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_CLKREQ_B), + IMX_PINCTRL_PIN(IMX8DXL_PCIE_CTRL0_WAKE_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC0), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC1), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC2), + IMX_PINCTRL_PIN(IMX8DXL_USB_SS3_TC3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CLK), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_CMD), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA4), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA5), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA6), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_DATA7), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_STROBE), + IMX_PINCTRL_PIN(IMX8DXL_EMMC0_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_RESET_B), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_VSELECT), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_RE_P_N), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_WP), + IMX_PINCTRL_PIN(IMX8DXL_USDHC1_CD_B), + IMX_PINCTRL_PIN(IMX8DXL_CTL_NAND_DQS_P_N), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDIO), + IMX_PINCTRL_PIN(IMX8DXL_ENET0_MDC), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXC), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD3), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD2), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_TXD1), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RXD0), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_RGMII_RX_CTL), + IMX_PINCTRL_PIN(IMX8DXL_ENET1_REFCLK_125M_25M), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS0), + IMX_PINCTRL_PIN(IMX8DXL_SPI3_CS1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN1), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_IN0), + IMX_PINCTRL_PIN(IMX8DXL_MCLK_OUT0), + IMX_PINCTRL_PIN(IMX8DXL_UART1_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART1_RTS_B), + IMX_PINCTRL_PIN(IMX8DXL_UART1_CTS_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS1), + IMX_PINCTRL_PIN(IMX8DXL_SPI0_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN1), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN0), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN3), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN2), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN5), + IMX_PINCTRL_PIN(IMX8DXL_ADC_IN4), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN0_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN1_TX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_RX), + IMX_PINCTRL_PIN(IMX8DXL_FLEXCAN2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_RX), + IMX_PINCTRL_PIN(IMX8DXL_UART0_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_TX), + IMX_PINCTRL_PIN(IMX8DXL_UART2_RX), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH), + IMX_PINCTRL_PIN(IMX8DXL_JTAG_TRST_B), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SCL), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_I2C_SDA), + IMX_PINCTRL_PIN(IMX8DXL_PMIC_INT_B), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_00), + IMX_PINCTRL_PIN(IMX8DXL_SCU_GPIO0_01), + IMX_PINCTRL_PIN(IMX8DXL_SCU_PMIC_STANDBY), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE1), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE0), + IMX_PINCTRL_PIN(IMX8DXL_SCU_BOOT_MODE2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT3), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_OUT4), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN0), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN1), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN2), + IMX_PINCTRL_PIN(IMX8DXL_SNVS_TAMPER_IN3), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SCK), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDO), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_SDI), + IMX_PINCTRL_PIN(IMX8DXL_SPI1_CS0), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0A_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SCLK), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DQS), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA1), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA0), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA3), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_DATA2), + IMX_PINCTRL_PIN(IMX8DXL_QSPI0B_SS0_B), + IMX_PINCTRL_PIN(IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B) +}; + + +static struct imx_pinctrl_soc_info imx8dxl_pinctrl_info = { + .pins = imx8dxl_pinctrl_pads, + .npins = ARRAY_SIZE(imx8dxl_pinctrl_pads), + .flags = IMX_USE_SCU, +}; + +static const struct of_device_id imx8dxl_pinctrl_of_match[] = { + { .compatible = "fsl,imx8dxl-iomuxc", }, + { /* sentinel */ } +}; + +static int imx8dxl_pinctrl_probe(struct platform_device *pdev) +{ + int ret; + + ret = imx_pinctrl_sc_ipc_init(pdev); + if (ret) + return ret; + + return imx_pinctrl_probe(pdev, &imx8dxl_pinctrl_info); +} + +static struct platform_driver imx8dxl_pinctrl_driver = { + .driver = { + .name = "fsl,imx8dxl-iomuxc", + .of_match_table = of_match_ptr(imx8dxl_pinctrl_of_match), + .suppress_bind_attrs = true, + }, + .probe = imx8dxl_pinctrl_probe, +}; + +static int __init imx8dxl_pinctrl_init(void) +{ + return platform_driver_register(&imx8dxl_pinctrl_driver); +} +arch_initcall(imx8dxl_pinctrl_init); diff --git a/include/dt-bindings/pinctrl/pads-imx8dxl.h b/include/dt-bindings/pinctrl/pads-imx8dxl.h new file mode 100644 index 000000000000..b1d7b84c3e0a --- /dev/null +++ b/include/dt-bindings/pinctrl/pads-imx8dxl.h @@ -0,0 +1,639 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019~2020 NXP + */ + +#ifndef _IMX8DXL_PADS_H +#define _IMX8DXL_PADS_H + +/* pin id */ +#define IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B 1 +#define IMX8DXL_PCIE_CTRL0_WAKE_B 2 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 +#define IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2 6 +#define IMX8DXL_USB_SS3_TC3 7 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 8 +#define IMX8DXL_EMMC0_CLK 9 +#define IMX8DXL_EMMC0_CMD 10 +#define IMX8DXL_EMMC0_DATA0 11 +#define IMX8DXL_EMMC0_DATA1 12 +#define IMX8DXL_EMMC0_DATA2 13 +#define IMX8DXL_EMMC0_DATA3 14 +#define IMX8DXL_EMMC0_DATA4 15 +#define IMX8DXL_EMMC0_DATA5 16 +#define IMX8DXL_EMMC0_DATA6 17 +#define IMX8DXL_EMMC0_DATA7 18 +#define IMX8DXL_EMMC0_STROBE 19 +#define IMX8DXL_EMMC0_RESET_B 20 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 21 +#define IMX8DXL_USDHC1_RESET_B 22 +#define IMX8DXL_USDHC1_VSELECT 23 +#define IMX8DXL_CTL_NAND_RE_P_N 24 +#define IMX8DXL_USDHC1_WP 25 +#define IMX8DXL_USDHC1_CD_B 26 +#define IMX8DXL_CTL_NAND_DQS_P_N 27 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 28 +#define IMX8DXL_ENET0_RGMII_TXC 29 +#define IMX8DXL_ENET0_RGMII_TX_CTL 30 +#define IMX8DXL_ENET0_RGMII_TXD0 31 +#define IMX8DXL_ENET0_RGMII_TXD1 32 +#define IMX8DXL_ENET0_RGMII_TXD2 33 +#define IMX8DXL_ENET0_RGMII_TXD3 34 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35 +#define IMX8DXL_ENET0_RGMII_RXC 36 +#define IMX8DXL_ENET0_RGMII_RX_CTL 37 +#define IMX8DXL_ENET0_RGMII_RXD0 38 +#define IMX8DXL_ENET0_RGMII_RXD1 39 +#define IMX8DXL_ENET0_RGMII_RXD2 40 +#define IMX8DXL_ENET0_RGMII_RXD3 41 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 42 +#define IMX8DXL_ENET0_REFCLK_125M_25M 43 +#define IMX8DXL_ENET0_MDIO 44 +#define IMX8DXL_ENET0_MDC 45 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 46 +#define IMX8DXL_ENET1_RGMII_TXC 47 +#define IMX8DXL_ENET1_RGMII_TXD2 48 +#define IMX8DXL_ENET1_RGMII_TX_CTL 49 +#define IMX8DXL_ENET1_RGMII_TXD3 50 +#define IMX8DXL_ENET1_RGMII_RXC 51 +#define IMX8DXL_ENET1_RGMII_RXD3 52 +#define IMX8DXL_ENET1_RGMII_RXD2 53 +#define IMX8DXL_ENET1_RGMII_RXD1 54 +#define IMX8DXL_ENET1_RGMII_TXD0 55 +#define IMX8DXL_ENET1_RGMII_TXD1 56 +#define IMX8DXL_ENET1_RGMII_RXD0 57 +#define IMX8DXL_ENET1_RGMII_RX_CTL 58 +#define IMX8DXL_ENET1_REFCLK_125M_25M 59 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 60 +#define IMX8DXL_SPI3_SCK 61 +#define IMX8DXL_SPI3_SDO 62 +#define IMX8DXL_SPI3_SDI 63 +#define IMX8DXL_SPI3_CS0 64 +#define IMX8DXL_SPI3_CS1 65 +#define IMX8DXL_MCLK_IN1 66 +#define IMX8DXL_MCLK_IN0 67 +#define IMX8DXL_MCLK_OUT0 68 +#define IMX8DXL_UART1_TX 69 +#define IMX8DXL_UART1_RX 70 +#define IMX8DXL_UART1_RTS_B 71 +#define IMX8DXL_UART1_CTS_B 72 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 73 +#define IMX8DXL_SPI0_SCK 74 +#define IMX8DXL_SPI0_SDI 75 +#define IMX8DXL_SPI0_SDO 76 +#define IMX8DXL_SPI0_CS1 77 +#define IMX8DXL_SPI0_CS0 78 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 79 +#define IMX8DXL_ADC_IN1 80 +#define IMX8DXL_ADC_IN0 81 +#define IMX8DXL_ADC_IN3 82 +#define IMX8DXL_ADC_IN2 83 +#define IMX8DXL_ADC_IN5 84 +#define IMX8DXL_ADC_IN4 85 +#define IMX8DXL_FLEXCAN0_RX 86 +#define IMX8DXL_FLEXCAN0_TX 87 +#define IMX8DXL_FLEXCAN1_RX 88 +#define IMX8DXL_FLEXCAN1_TX 89 +#define IMX8DXL_FLEXCAN2_RX 90 +#define IMX8DXL_FLEXCAN2_TX 91 +#define IMX8DXL_UART0_RX 92 +#define IMX8DXL_UART0_TX 93 +#define IMX8DXL_UART2_TX 94 +#define IMX8DXL_UART2_RX 95 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 96 +#define IMX8DXL_JTAG_TRST_B 97 +#define IMX8DXL_PMIC_I2C_SCL 98 +#define IMX8DXL_PMIC_I2C_SDA 99 +#define IMX8DXL_PMIC_INT_B 100 +#define IMX8DXL_SCU_GPIO0_00 101 +#define IMX8DXL_SCU_GPIO0_01 102 +#define IMX8DXL_SCU_PMIC_STANDBY 103 +#define IMX8DXL_SCU_BOOT_MODE1 104 +#define IMX8DXL_SCU_BOOT_MODE0 105 +#define IMX8DXL_SCU_BOOT_MODE2 106 +#define IMX8DXL_SNVS_TAMPER_OUT1 107 +#define IMX8DXL_SNVS_TAMPER_OUT2 108 +#define IMX8DXL_SNVS_TAMPER_OUT3 109 +#define IMX8DXL_SNVS_TAMPER_OUT4 110 +#define IMX8DXL_SNVS_TAMPER_IN0 111 +#define IMX8DXL_SNVS_TAMPER_IN1 112 +#define IMX8DXL_SNVS_TAMPER_IN2 113 +#define IMX8DXL_SNVS_TAMPER_IN3 114 +#define IMX8DXL_SPI1_SCK 115 +#define IMX8DXL_SPI1_SDO 116 +#define IMX8DXL_SPI1_SDI 117 +#define IMX8DXL_SPI1_CS0 118 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 119 +#define IMX8DXL_QSPI0A_DATA1 120 +#define IMX8DXL_QSPI0A_DATA0 121 +#define IMX8DXL_QSPI0A_DATA3 122 +#define IMX8DXL_QSPI0A_DATA2 123 +#define IMX8DXL_QSPI0A_SS0_B 124 +#define IMX8DXL_QSPI0A_DQS 125 +#define IMX8DXL_QSPI0A_SCLK 126 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 127 +#define IMX8DXL_QSPI0B_SCLK 128 +#define IMX8DXL_QSPI0B_DQS 129 +#define IMX8DXL_QSPI0B_DATA1 130 +#define IMX8DXL_QSPI0B_DATA0 131 +#define IMX8DXL_QSPI0B_DATA3 132 +#define IMX8DXL_QSPI0B_DATA2 133 +#define IMX8DXL_QSPI0B_SS0_B 134 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 135 + +/* format: */ +#define IMX8DXL_PCIE_CTRL0_PERST_B_HSIO_PCIE0_PERST_B IMX8DXL_PCIE_CTRL0_PERST_B 0 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 4 +#define IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO7_IO00 IMX8DXL_PCIE_CTRL0_PERST_B 5 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B IMX8DXL_PCIE_CTRL0_CLKREQ_B 0 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 4 +#define IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO7_IO01 IMX8DXL_PCIE_CTRL0_CLKREQ_B 5 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_HSIO_PCIE0_WAKE_B IMX8DXL_PCIE_CTRL0_WAKE_B 0 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 4 +#define IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO7_IO02 IMX8DXL_PCIE_CTRL0_WAKE_B 5 +#define IMX8DXL_USB_SS3_TC0_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC0 0 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR IMX8DXL_USB_SS3_TC0 1 +#define IMX8DXL_USB_SS3_TC0_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC0 2 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 IMX8DXL_USB_SS3_TC0 4 +#define IMX8DXL_USB_SS3_TC0_LSIO_GPIO7_IO03 IMX8DXL_USB_SS3_TC0 5 +#define IMX8DXL_USB_SS3_TC1_ADMA_I2C1_SCL IMX8DXL_USB_SS3_TC1 0 +#define IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR IMX8DXL_USB_SS3_TC1 1 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 IMX8DXL_USB_SS3_TC1 4 +#define IMX8DXL_USB_SS3_TC1_LSIO_GPIO7_IO04 IMX8DXL_USB_SS3_TC1 5 +#define IMX8DXL_USB_SS3_TC2_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC2 0 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG1_OC IMX8DXL_USB_SS3_TC2 1 +#define IMX8DXL_USB_SS3_TC2_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC2 2 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 IMX8DXL_USB_SS3_TC2 4 +#define IMX8DXL_USB_SS3_TC2_LSIO_GPIO7_IO05 IMX8DXL_USB_SS3_TC2 5 +#define IMX8DXL_USB_SS3_TC3_ADMA_I2C1_SDA IMX8DXL_USB_SS3_TC3 0 +#define IMX8DXL_USB_SS3_TC3_CONN_USB_OTG2_OC IMX8DXL_USB_SS3_TC3 1 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 IMX8DXL_USB_SS3_TC3 4 +#define IMX8DXL_USB_SS3_TC3_LSIO_GPIO7_IO06 IMX8DXL_USB_SS3_TC3 5 +#define IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK IMX8DXL_EMMC0_CLK 0 +#define IMX8DXL_EMMC0_CLK_CONN_NAND_READY_B IMX8DXL_EMMC0_CLK 1 +#define IMX8DXL_EMMC0_CLK_LSIO_GPIO4_IO07 IMX8DXL_EMMC0_CLK 4 +#define IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD IMX8DXL_EMMC0_CMD 0 +#define IMX8DXL_EMMC0_CMD_CONN_NAND_DQS IMX8DXL_EMMC0_CMD 1 +#define IMX8DXL_EMMC0_CMD_LSIO_GPIO4_IO08 IMX8DXL_EMMC0_CMD 4 +#define IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 IMX8DXL_EMMC0_DATA0 0 +#define IMX8DXL_EMMC0_DATA0_CONN_NAND_DATA00 IMX8DXL_EMMC0_DATA0 1 +#define IMX8DXL_EMMC0_DATA0_LSIO_GPIO4_IO09 IMX8DXL_EMMC0_DATA0 4 +#define IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 IMX8DXL_EMMC0_DATA1 0 +#define IMX8DXL_EMMC0_DATA1_CONN_NAND_DATA01 IMX8DXL_EMMC0_DATA1 1 +#define IMX8DXL_EMMC0_DATA1_LSIO_GPIO4_IO10 IMX8DXL_EMMC0_DATA1 4 +#define IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 IMX8DXL_EMMC0_DATA2 0 +#define IMX8DXL_EMMC0_DATA2_CONN_NAND_DATA02 IMX8DXL_EMMC0_DATA2 1 +#define IMX8DXL_EMMC0_DATA2_LSIO_GPIO4_IO11 IMX8DXL_EMMC0_DATA2 4 +#define IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 IMX8DXL_EMMC0_DATA3 0 +#define IMX8DXL_EMMC0_DATA3_CONN_NAND_DATA03 IMX8DXL_EMMC0_DATA3 1 +#define IMX8DXL_EMMC0_DATA3_LSIO_GPIO4_IO12 IMX8DXL_EMMC0_DATA3 4 +#define IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 IMX8DXL_EMMC0_DATA4 0 +#define IMX8DXL_EMMC0_DATA4_CONN_NAND_DATA04 IMX8DXL_EMMC0_DATA4 1 +#define IMX8DXL_EMMC0_DATA4_LSIO_GPIO4_IO13 IMX8DXL_EMMC0_DATA4 4 +#define IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 IMX8DXL_EMMC0_DATA5 0 +#define IMX8DXL_EMMC0_DATA5_CONN_NAND_DATA05 IMX8DXL_EMMC0_DATA5 1 +#define IMX8DXL_EMMC0_DATA5_LSIO_GPIO4_IO14 IMX8DXL_EMMC0_DATA5 4 +#define IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 IMX8DXL_EMMC0_DATA6 0 +#define IMX8DXL_EMMC0_DATA6_CONN_NAND_DATA06 IMX8DXL_EMMC0_DATA6 1 +#define IMX8DXL_EMMC0_DATA6_LSIO_GPIO4_IO15 IMX8DXL_EMMC0_DATA6 4 +#define IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 IMX8DXL_EMMC0_DATA7 0 +#define IMX8DXL_EMMC0_DATA7_CONN_NAND_DATA07 IMX8DXL_EMMC0_DATA7 1 +#define IMX8DXL_EMMC0_DATA7_LSIO_GPIO4_IO16 IMX8DXL_EMMC0_DATA7 4 +#define IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE IMX8DXL_EMMC0_STROBE 0 +#define IMX8DXL_EMMC0_STROBE_CONN_NAND_CLE IMX8DXL_EMMC0_STROBE 1 +#define IMX8DXL_EMMC0_STROBE_LSIO_GPIO4_IO17 IMX8DXL_EMMC0_STROBE 4 +#define IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B IMX8DXL_EMMC0_RESET_B 0 +#define IMX8DXL_EMMC0_RESET_B_CONN_NAND_WP_B IMX8DXL_EMMC0_RESET_B 1 +#define IMX8DXL_EMMC0_RESET_B_LSIO_GPIO4_IO18 IMX8DXL_EMMC0_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_CONN_USDHC1_RESET_B IMX8DXL_USDHC1_RESET_B 0 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_RE_N IMX8DXL_USDHC1_RESET_B 1 +#define IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK IMX8DXL_USDHC1_RESET_B 2 +#define IMX8DXL_USDHC1_RESET_B_CONN_NAND_WE_B IMX8DXL_USDHC1_RESET_B 3 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO4_IO19 IMX8DXL_USDHC1_RESET_B 4 +#define IMX8DXL_USDHC1_RESET_B_LSIO_GPIO7_IO08 IMX8DXL_USDHC1_RESET_B 5 +#define IMX8DXL_USDHC1_VSELECT_CONN_USDHC1_VSELECT IMX8DXL_USDHC1_VSELECT 0 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_P IMX8DXL_USDHC1_VSELECT 1 +#define IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO IMX8DXL_USDHC1_VSELECT 2 +#define IMX8DXL_USDHC1_VSELECT_CONN_NAND_RE_B IMX8DXL_USDHC1_VSELECT 3 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO4_IO20 IMX8DXL_USDHC1_VSELECT 4 +#define IMX8DXL_USDHC1_VSELECT_LSIO_GPIO7_IO09 IMX8DXL_USDHC1_VSELECT 5 +#define IMX8DXL_USDHC1_WP_CONN_USDHC1_WP IMX8DXL_USDHC1_WP 0 +#define IMX8DXL_USDHC1_WP_CONN_NAND_DQS_N IMX8DXL_USDHC1_WP 1 +#define IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI IMX8DXL_USDHC1_WP 2 +#define IMX8DXL_USDHC1_WP_CONN_NAND_ALE IMX8DXL_USDHC1_WP 3 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO4_IO21 IMX8DXL_USDHC1_WP 4 +#define IMX8DXL_USDHC1_WP_LSIO_GPIO7_IO10 IMX8DXL_USDHC1_WP 5 +#define IMX8DXL_USDHC1_CD_B_CONN_USDHC1_CD_B IMX8DXL_USDHC1_CD_B 0 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS_P IMX8DXL_USDHC1_CD_B 1 +#define IMX8DXL_USDHC1_CD_B_ADMA_SPI2_CS0 IMX8DXL_USDHC1_CD_B 2 +#define IMX8DXL_USDHC1_CD_B_CONN_NAND_DQS IMX8DXL_USDHC1_CD_B 3 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 IMX8DXL_USDHC1_CD_B 4 +#define IMX8DXL_USDHC1_CD_B_LSIO_GPIO7_IO11 IMX8DXL_USDHC1_CD_B 5 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC IMX8DXL_ENET0_RGMII_TXC 0 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT IMX8DXL_ENET0_RGMII_TXC 1 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_IN IMX8DXL_ENET0_RGMII_TXC 2 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_NAND_CE1_B IMX8DXL_ENET0_RGMII_TXC 3 +#define IMX8DXL_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 IMX8DXL_ENET0_RGMII_TXC 4 +#define IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK IMX8DXL_ENET0_RGMII_TXC 5 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL IMX8DXL_ENET0_RGMII_TX_CTL 0 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC1_RESET_B IMX8DXL_ENET0_RGMII_TX_CTL 3 +#define IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 IMX8DXL_ENET0_RGMII_TX_CTL 4 +#define IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD IMX8DXL_ENET0_RGMII_TX_CTL 5 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 IMX8DXL_ENET0_RGMII_TXD0 0 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT IMX8DXL_ENET0_RGMII_TXD0 3 +#define IMX8DXL_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 IMX8DXL_ENET0_RGMII_TXD0 4 +#define IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 IMX8DXL_ENET0_RGMII_TXD0 5 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 IMX8DXL_ENET0_RGMII_TXD1 0 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC1_WP IMX8DXL_ENET0_RGMII_TXD1 3 +#define IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 IMX8DXL_ENET0_RGMII_TXD1 4 +#define IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 IMX8DXL_ENET0_RGMII_TXD1 5 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 IMX8DXL_ENET0_RGMII_TXD2 0 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_NAND_CE0_B IMX8DXL_ENET0_RGMII_TXD2 2 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B IMX8DXL_ENET0_RGMII_TXD2 3 +#define IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 IMX8DXL_ENET0_RGMII_TXD2 4 +#define IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 IMX8DXL_ENET0_RGMII_TXD2 5 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 IMX8DXL_ENET0_RGMII_TXD3 0 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_NAND_RE_B IMX8DXL_ENET0_RGMII_TXD3 2 +#define IMX8DXL_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 IMX8DXL_ENET0_RGMII_TXD3 4 +#define IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 IMX8DXL_ENET0_RGMII_TXD3 5 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC IMX8DXL_ENET0_RGMII_RXC 0 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_NAND_WE_B IMX8DXL_ENET0_RGMII_RXC 2 +#define IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK IMX8DXL_ENET0_RGMII_RXC 3 +#define IMX8DXL_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 IMX8DXL_ENET0_RGMII_RXC 4 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL IMX8DXL_ENET0_RGMII_RX_CTL 0 +#define IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD IMX8DXL_ENET0_RGMII_RX_CTL 3 +#define IMX8DXL_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 IMX8DXL_ENET0_RGMII_RX_CTL 4 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 IMX8DXL_ENET0_RGMII_RXD0 0 +#define IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 IMX8DXL_ENET0_RGMII_RXD0 3 +#define IMX8DXL_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 IMX8DXL_ENET0_RGMII_RXD0 4 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 IMX8DXL_ENET0_RGMII_RXD1 0 +#define IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 IMX8DXL_ENET0_RGMII_RXD1 3 +#define IMX8DXL_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 IMX8DXL_ENET0_RGMII_RXD1 4 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 IMX8DXL_ENET0_RGMII_RXD2 0 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER IMX8DXL_ENET0_RGMII_RXD2 1 +#define IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 IMX8DXL_ENET0_RGMII_RXD2 3 +#define IMX8DXL_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 IMX8DXL_ENET0_RGMII_RXD2 4 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 IMX8DXL_ENET0_RGMII_RXD3 0 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_NAND_ALE IMX8DXL_ENET0_RGMII_RXD3 2 +#define IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 IMX8DXL_ENET0_RGMII_RXD3 3 +#define IMX8DXL_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 IMX8DXL_ENET0_RGMII_RXD3 4 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M IMX8DXL_ENET0_REFCLK_125M_25M 0 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_ENET0_PPS IMX8DXL_ENET0_REFCLK_125M_25M 1 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_IN IMX8DXL_ENET0_REFCLK_125M_25M 2 +#define IMX8DXL_ENET0_REFCLK_125M_25M_CONN_EQOS_PPS_OUT IMX8DXL_ENET0_REFCLK_125M_25M 3 +#define IMX8DXL_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 IMX8DXL_ENET0_REFCLK_125M_25M 4 +#define IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO IMX8DXL_ENET0_MDIO 0 +#define IMX8DXL_ENET0_MDIO_ADMA_I2C3_SDA IMX8DXL_ENET0_MDIO 1 +#define IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO IMX8DXL_ENET0_MDIO 2 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO5_IO10 IMX8DXL_ENET0_MDIO 4 +#define IMX8DXL_ENET0_MDIO_LSIO_GPIO7_IO16 IMX8DXL_ENET0_MDIO 5 +#define IMX8DXL_ENET0_MDC_CONN_ENET0_MDC IMX8DXL_ENET0_MDC 0 +#define IMX8DXL_ENET0_MDC_ADMA_I2C3_SCL IMX8DXL_ENET0_MDC 1 +#define IMX8DXL_ENET0_MDC_CONN_EQOS_MDC IMX8DXL_ENET0_MDC 2 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO5_IO11 IMX8DXL_ENET0_MDC 4 +#define IMX8DXL_ENET0_MDC_LSIO_GPIO7_IO17 IMX8DXL_ENET0_MDC 5 +#define IMX8DXL_ENET1_RGMII_TXC_LSIO_GPIO0_IO00 IMX8DXL_ENET1_RGMII_TXC 0 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_OUT IMX8DXL_ENET1_RGMII_TXC 1 +#define IMX8DXL_ENET1_RGMII_TXC_ADMA_LCDIF_D00 IMX8DXL_ENET1_RGMII_TXC 2 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC IMX8DXL_ENET1_RGMII_TXC 3 +#define IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RCLK50M_IN IMX8DXL_ENET1_RGMII_TXC 4 +#define IMX8DXL_ENET1_RGMII_TXD2_ADMA_LCDIF_D01 IMX8DXL_ENET1_RGMII_TXD2 2 +#define IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 IMX8DXL_ENET1_RGMII_TXD2 3 +#define IMX8DXL_ENET1_RGMII_TXD2_LSIO_GPIO0_IO01 IMX8DXL_ENET1_RGMII_TXD2 4 +#define IMX8DXL_ENET1_RGMII_TX_CTL_ADMA_LCDIF_D02 IMX8DXL_ENET1_RGMII_TX_CTL 2 +#define IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL IMX8DXL_ENET1_RGMII_TX_CTL 3 +#define IMX8DXL_ENET1_RGMII_TX_CTL_LSIO_GPIO0_IO02 IMX8DXL_ENET1_RGMII_TX_CTL 4 +#define IMX8DXL_ENET1_RGMII_TXD3_ADMA_LCDIF_D03 IMX8DXL_ENET1_RGMII_TXD3 2 +#define IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 IMX8DXL_ENET1_RGMII_TXD3 3 +#define IMX8DXL_ENET1_RGMII_TXD3_LSIO_GPIO0_IO03 IMX8DXL_ENET1_RGMII_TXD3 4 +#define IMX8DXL_ENET1_RGMII_RXC_ADMA_LCDIF_D04 IMX8DXL_ENET1_RGMII_RXC 2 +#define IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC IMX8DXL_ENET1_RGMII_RXC 3 +#define IMX8DXL_ENET1_RGMII_RXC_LSIO_GPIO0_IO04 IMX8DXL_ENET1_RGMII_RXC 4 +#define IMX8DXL_ENET1_RGMII_RXD3_ADMA_LCDIF_D05 IMX8DXL_ENET1_RGMII_RXD3 2 +#define IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 IMX8DXL_ENET1_RGMII_RXD3 3 +#define IMX8DXL_ENET1_RGMII_RXD3_LSIO_GPIO0_IO05 IMX8DXL_ENET1_RGMII_RXD3 4 +#define IMX8DXL_ENET1_RGMII_RXD2_ADMA_LCDIF_D06 IMX8DXL_ENET1_RGMII_RXD2 2 +#define IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 IMX8DXL_ENET1_RGMII_RXD2 3 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO0_IO06 IMX8DXL_ENET1_RGMII_RXD2 4 +#define IMX8DXL_ENET1_RGMII_RXD2_LSIO_GPIO6_IO00 IMX8DXL_ENET1_RGMII_RXD2 5 +#define IMX8DXL_ENET1_RGMII_RXD1_ADMA_LCDIF_D07 IMX8DXL_ENET1_RGMII_RXD1 2 +#define IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 IMX8DXL_ENET1_RGMII_RXD1 3 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO0_IO07 IMX8DXL_ENET1_RGMII_RXD1 4 +#define IMX8DXL_ENET1_RGMII_RXD1_LSIO_GPIO6_IO01 IMX8DXL_ENET1_RGMII_RXD1 5 +#define IMX8DXL_ENET1_RGMII_TXD0_ADMA_LCDIF_D08 IMX8DXL_ENET1_RGMII_TXD0 2 +#define IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 IMX8DXL_ENET1_RGMII_TXD0 3 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO0_IO08 IMX8DXL_ENET1_RGMII_TXD0 4 +#define IMX8DXL_ENET1_RGMII_TXD0_LSIO_GPIO6_IO02 IMX8DXL_ENET1_RGMII_TXD0 5 +#define IMX8DXL_ENET1_RGMII_TXD1_ADMA_LCDIF_D09 IMX8DXL_ENET1_RGMII_TXD1 2 +#define IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 IMX8DXL_ENET1_RGMII_TXD1 3 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO0_IO09 IMX8DXL_ENET1_RGMII_TXD1 4 +#define IMX8DXL_ENET1_RGMII_TXD1_LSIO_GPIO6_IO03 IMX8DXL_ENET1_RGMII_TXD1 5 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_SPDIF0_RX IMX8DXL_ENET1_RGMII_RXD0 0 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_MQS_R IMX8DXL_ENET1_RGMII_RXD0 1 +#define IMX8DXL_ENET1_RGMII_RXD0_ADMA_LCDIF_D10 IMX8DXL_ENET1_RGMII_RXD0 2 +#define IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 IMX8DXL_ENET1_RGMII_RXD0 3 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO0_IO10 IMX8DXL_ENET1_RGMII_RXD0 4 +#define IMX8DXL_ENET1_RGMII_RXD0_LSIO_GPIO6_IO04 IMX8DXL_ENET1_RGMII_RXD0 5 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_SPDIF0_TX IMX8DXL_ENET1_RGMII_RX_CTL 0 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_MQS_L IMX8DXL_ENET1_RGMII_RX_CTL 1 +#define IMX8DXL_ENET1_RGMII_RX_CTL_ADMA_LCDIF_D11 IMX8DXL_ENET1_RGMII_RX_CTL 2 +#define IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL IMX8DXL_ENET1_RGMII_RX_CTL 3 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO0_IO11 IMX8DXL_ENET1_RGMII_RX_CTL 4 +#define IMX8DXL_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO05 IMX8DXL_ENET1_RGMII_RX_CTL 5 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_SPDIF0_EXT_CLK IMX8DXL_ENET1_REFCLK_125M_25M 0 +#define IMX8DXL_ENET1_REFCLK_125M_25M_ADMA_LCDIF_D12 IMX8DXL_ENET1_REFCLK_125M_25M 2 +#define IMX8DXL_ENET1_REFCLK_125M_25M_CONN_EQOS_REFCLK_125M_25M IMX8DXL_ENET1_REFCLK_125M_25M 3 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO0_IO12 IMX8DXL_ENET1_REFCLK_125M_25M 4 +#define IMX8DXL_ENET1_REFCLK_125M_25M_LSIO_GPIO6_IO06 IMX8DXL_ENET1_REFCLK_125M_25M 5 +#define IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK IMX8DXL_SPI3_SCK 0 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D13 IMX8DXL_SPI3_SCK 2 +#define IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 IMX8DXL_SPI3_SCK 4 +#define IMX8DXL_SPI3_SCK_ADMA_LCDIF_D00 IMX8DXL_SPI3_SCK 5 +#define IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO IMX8DXL_SPI3_SDO 0 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D14 IMX8DXL_SPI3_SDO 2 +#define IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 IMX8DXL_SPI3_SDO 4 +#define IMX8DXL_SPI3_SDO_ADMA_LCDIF_D01 IMX8DXL_SPI3_SDO 5 +#define IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI IMX8DXL_SPI3_SDI 0 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D15 IMX8DXL_SPI3_SDI 2 +#define IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 IMX8DXL_SPI3_SDI 4 +#define IMX8DXL_SPI3_SDI_ADMA_LCDIF_D02 IMX8DXL_SPI3_SDI 5 +#define IMX8DXL_SPI3_CS0_ADMA_SPI3_CS0 IMX8DXL_SPI3_CS0 0 +#define IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 IMX8DXL_SPI3_CS0 1 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_HSYNC IMX8DXL_SPI3_CS0 2 +#define IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 IMX8DXL_SPI3_CS0 4 +#define IMX8DXL_SPI3_CS0_ADMA_LCDIF_CS IMX8DXL_SPI3_CS0 5 +#define IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 IMX8DXL_SPI3_CS1 0 +#define IMX8DXL_SPI3_CS1_ADMA_I2C3_SCL IMX8DXL_SPI3_CS1 1 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RESET IMX8DXL_SPI3_CS1 2 +#define IMX8DXL_SPI3_CS1_ADMA_SPI2_CS0 IMX8DXL_SPI3_CS1 3 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_D16 IMX8DXL_SPI3_CS1 4 +#define IMX8DXL_SPI3_CS1_ADMA_LCDIF_RD_E IMX8DXL_SPI3_CS1 5 +#define IMX8DXL_MCLK_IN1_ADMA_ACM_MCLK_IN1 IMX8DXL_MCLK_IN1 0 +#define IMX8DXL_MCLK_IN1_ADMA_I2C3_SDA IMX8DXL_MCLK_IN1 1 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_EN IMX8DXL_MCLK_IN1 2 +#define IMX8DXL_MCLK_IN1_ADMA_SPI2_SCK IMX8DXL_MCLK_IN1 3 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D17 IMX8DXL_MCLK_IN1 4 +#define IMX8DXL_MCLK_IN1_ADMA_LCDIF_D03 IMX8DXL_MCLK_IN1 5 +#define IMX8DXL_MCLK_IN0_ADMA_ACM_MCLK_IN0 IMX8DXL_MCLK_IN0 0 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_VSYNC IMX8DXL_MCLK_IN0 2 +#define IMX8DXL_MCLK_IN0_ADMA_SPI2_SDI IMX8DXL_MCLK_IN0 3 +#define IMX8DXL_MCLK_IN0_LSIO_GPIO0_IO19 IMX8DXL_MCLK_IN0 4 +#define IMX8DXL_MCLK_IN0_ADMA_LCDIF_RS IMX8DXL_MCLK_IN0 5 +#define IMX8DXL_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 IMX8DXL_MCLK_OUT0 0 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_CLK IMX8DXL_MCLK_OUT0 2 +#define IMX8DXL_MCLK_OUT0_ADMA_SPI2_SDO IMX8DXL_MCLK_OUT0 3 +#define IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 IMX8DXL_MCLK_OUT0 4 +#define IMX8DXL_MCLK_OUT0_ADMA_LCDIF_WR_RWN IMX8DXL_MCLK_OUT0 5 +#define IMX8DXL_UART1_TX_ADMA_UART1_TX IMX8DXL_UART1_TX 0 +#define IMX8DXL_UART1_TX_LSIO_PWM0_OUT IMX8DXL_UART1_TX 1 +#define IMX8DXL_UART1_TX_LSIO_GPT0_CAPTURE IMX8DXL_UART1_TX 2 +#define IMX8DXL_UART1_TX_LSIO_GPIO0_IO21 IMX8DXL_UART1_TX 4 +#define IMX8DXL_UART1_TX_ADMA_LCDIF_D04 IMX8DXL_UART1_TX 5 +#define IMX8DXL_UART1_RX_ADMA_UART1_RX IMX8DXL_UART1_RX 0 +#define IMX8DXL_UART1_RX_LSIO_PWM1_OUT IMX8DXL_UART1_RX 1 +#define IMX8DXL_UART1_RX_LSIO_GPT0_COMPARE IMX8DXL_UART1_RX 2 +#define IMX8DXL_UART1_RX_LSIO_GPT1_CLK IMX8DXL_UART1_RX 3 +#define IMX8DXL_UART1_RX_LSIO_GPIO0_IO22 IMX8DXL_UART1_RX 4 +#define IMX8DXL_UART1_RX_ADMA_LCDIF_D05 IMX8DXL_UART1_RX 5 +#define IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B IMX8DXL_UART1_RTS_B 0 +#define IMX8DXL_UART1_RTS_B_LSIO_PWM2_OUT IMX8DXL_UART1_RTS_B 1 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D16 IMX8DXL_UART1_RTS_B 2 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT1_CAPTURE IMX8DXL_UART1_RTS_B 3 +#define IMX8DXL_UART1_RTS_B_LSIO_GPT0_CLK IMX8DXL_UART1_RTS_B 4 +#define IMX8DXL_UART1_RTS_B_ADMA_LCDIF_D06 IMX8DXL_UART1_RTS_B 5 +#define IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B IMX8DXL_UART1_CTS_B 0 +#define IMX8DXL_UART1_CTS_B_LSIO_PWM3_OUT IMX8DXL_UART1_CTS_B 1 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D17 IMX8DXL_UART1_CTS_B 2 +#define IMX8DXL_UART1_CTS_B_LSIO_GPT1_COMPARE IMX8DXL_UART1_CTS_B 3 +#define IMX8DXL_UART1_CTS_B_LSIO_GPIO0_IO24 IMX8DXL_UART1_CTS_B 4 +#define IMX8DXL_UART1_CTS_B_ADMA_LCDIF_D07 IMX8DXL_UART1_CTS_B 5 +#define IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK IMX8DXL_SPI0_SCK 0 +#define IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC IMX8DXL_SPI0_SCK 1 +#define IMX8DXL_SPI0_SCK_M40_I2C0_SCL IMX8DXL_SPI0_SCK 2 +#define IMX8DXL_SPI0_SCK_M40_GPIO0_IO00 IMX8DXL_SPI0_SCK 3 +#define IMX8DXL_SPI0_SCK_LSIO_GPIO1_IO04 IMX8DXL_SPI0_SCK 4 +#define IMX8DXL_SPI0_SCK_ADMA_LCDIF_D08 IMX8DXL_SPI0_SCK 5 +#define IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI IMX8DXL_SPI0_SDI 0 +#define IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD IMX8DXL_SPI0_SDI 1 +#define IMX8DXL_SPI0_SDI_M40_TPM0_CH0 IMX8DXL_SPI0_SDI 2 +#define IMX8DXL_SPI0_SDI_M40_GPIO0_IO02 IMX8DXL_SPI0_SDI 3 +#define IMX8DXL_SPI0_SDI_LSIO_GPIO1_IO05 IMX8DXL_SPI0_SDI 4 +#define IMX8DXL_SPI0_SDI_ADMA_LCDIF_D09 IMX8DXL_SPI0_SDI 5 +#define IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO IMX8DXL_SPI0_SDO 0 +#define IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS IMX8DXL_SPI0_SDO 1 +#define IMX8DXL_SPI0_SDO_M40_I2C0_SDA IMX8DXL_SPI0_SDO 2 +#define IMX8DXL_SPI0_SDO_M40_GPIO0_IO01 IMX8DXL_SPI0_SDO 3 +#define IMX8DXL_SPI0_SDO_LSIO_GPIO1_IO06 IMX8DXL_SPI0_SDO 4 +#define IMX8DXL_SPI0_SDO_ADMA_LCDIF_D10 IMX8DXL_SPI0_SDO 5 +#define IMX8DXL_SPI0_CS1_ADMA_SPI0_CS1 IMX8DXL_SPI0_CS1 0 +#define IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC IMX8DXL_SPI0_CS1 1 +#define IMX8DXL_SPI0_CS1_ADMA_SAI1_TXD IMX8DXL_SPI0_CS1 2 +#define IMX8DXL_SPI0_CS1_ADMA_LCD_PWM0_OUT IMX8DXL_SPI0_CS1 3 +#define IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 IMX8DXL_SPI0_CS1 4 +#define IMX8DXL_SPI0_CS1_ADMA_LCDIF_D11 IMX8DXL_SPI0_CS1 5 +#define IMX8DXL_SPI0_CS0_ADMA_SPI0_CS0 IMX8DXL_SPI0_CS0 0 +#define IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD IMX8DXL_SPI0_CS0 1 +#define IMX8DXL_SPI0_CS0_M40_TPM0_CH1 IMX8DXL_SPI0_CS0 2 +#define IMX8DXL_SPI0_CS0_M40_GPIO0_IO03 IMX8DXL_SPI0_CS0 3 +#define IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 IMX8DXL_SPI0_CS0 4 +#define IMX8DXL_SPI0_CS0_ADMA_LCDIF_D12 IMX8DXL_SPI0_CS0 5 +#define IMX8DXL_ADC_IN1_ADMA_ADC_IN1 IMX8DXL_ADC_IN1 0 +#define IMX8DXL_ADC_IN1_M40_I2C0_SDA IMX8DXL_ADC_IN1 1 +#define IMX8DXL_ADC_IN1_M40_GPIO0_IO01 IMX8DXL_ADC_IN1 2 +#define IMX8DXL_ADC_IN1_ADMA_I2C0_SDA IMX8DXL_ADC_IN1 3 +#define IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 IMX8DXL_ADC_IN1 4 +#define IMX8DXL_ADC_IN1_ADMA_LCDIF_D13 IMX8DXL_ADC_IN1 5 +#define IMX8DXL_ADC_IN0_ADMA_ADC_IN0 IMX8DXL_ADC_IN0 0 +#define IMX8DXL_ADC_IN0_M40_I2C0_SCL IMX8DXL_ADC_IN0 1 +#define IMX8DXL_ADC_IN0_M40_GPIO0_IO00 IMX8DXL_ADC_IN0 2 +#define IMX8DXL_ADC_IN0_ADMA_I2C0_SCL IMX8DXL_ADC_IN0 3 +#define IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 IMX8DXL_ADC_IN0 4 +#define IMX8DXL_ADC_IN0_ADMA_LCDIF_D14 IMX8DXL_ADC_IN0 5 +#define IMX8DXL_ADC_IN3_ADMA_ADC_IN3 IMX8DXL_ADC_IN3 0 +#define IMX8DXL_ADC_IN3_M40_UART0_TX IMX8DXL_ADC_IN3 1 +#define IMX8DXL_ADC_IN3_M40_GPIO0_IO03 IMX8DXL_ADC_IN3 2 +#define IMX8DXL_ADC_IN3_ADMA_ACM_MCLK_OUT0 IMX8DXL_ADC_IN3 3 +#define IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 IMX8DXL_ADC_IN3 4 +#define IMX8DXL_ADC_IN3_ADMA_LCDIF_D15 IMX8DXL_ADC_IN3 5 +#define IMX8DXL_ADC_IN2_ADMA_ADC_IN2 IMX8DXL_ADC_IN2 0 +#define IMX8DXL_ADC_IN2_M40_UART0_RX IMX8DXL_ADC_IN2 1 +#define IMX8DXL_ADC_IN2_M40_GPIO0_IO02 IMX8DXL_ADC_IN2 2 +#define IMX8DXL_ADC_IN2_ADMA_ACM_MCLK_IN0 IMX8DXL_ADC_IN2 3 +#define IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 IMX8DXL_ADC_IN2 4 +#define IMX8DXL_ADC_IN2_ADMA_LCDIF_D16 IMX8DXL_ADC_IN2 5 +#define IMX8DXL_ADC_IN5_ADMA_ADC_IN5 IMX8DXL_ADC_IN5 0 +#define IMX8DXL_ADC_IN5_M40_TPM0_CH1 IMX8DXL_ADC_IN5 1 +#define IMX8DXL_ADC_IN5_M40_GPIO0_IO05 IMX8DXL_ADC_IN5 2 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_LCDBUSY IMX8DXL_ADC_IN5 3 +#define IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 IMX8DXL_ADC_IN5 4 +#define IMX8DXL_ADC_IN5_ADMA_LCDIF_D17 IMX8DXL_ADC_IN5 5 +#define IMX8DXL_ADC_IN4_ADMA_ADC_IN4 IMX8DXL_ADC_IN4 0 +#define IMX8DXL_ADC_IN4_M40_TPM0_CH0 IMX8DXL_ADC_IN4 1 +#define IMX8DXL_ADC_IN4_M40_GPIO0_IO04 IMX8DXL_ADC_IN4 2 +#define IMX8DXL_ADC_IN4_ADMA_LCDIF_LCDRESET IMX8DXL_ADC_IN4 3 +#define IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 IMX8DXL_ADC_IN4 4 +#define IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX IMX8DXL_FLEXCAN0_RX 0 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI2_RXC IMX8DXL_FLEXCAN0_RX 1 +#define IMX8DXL_FLEXCAN0_RX_ADMA_UART0_RTS_B IMX8DXL_FLEXCAN0_RX 2 +#define IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC IMX8DXL_FLEXCAN0_RX 3 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO1_IO15 IMX8DXL_FLEXCAN0_RX 4 +#define IMX8DXL_FLEXCAN0_RX_LSIO_GPIO6_IO08 IMX8DXL_FLEXCAN0_RX 5 +#define IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX IMX8DXL_FLEXCAN0_TX 0 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI2_RXD IMX8DXL_FLEXCAN0_TX 1 +#define IMX8DXL_FLEXCAN0_TX_ADMA_UART0_CTS_B IMX8DXL_FLEXCAN0_TX 2 +#define IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS IMX8DXL_FLEXCAN0_TX 3 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO1_IO16 IMX8DXL_FLEXCAN0_TX 4 +#define IMX8DXL_FLEXCAN0_TX_LSIO_GPIO6_IO09 IMX8DXL_FLEXCAN0_TX 5 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX IMX8DXL_FLEXCAN1_RX 0 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI2_RXFS IMX8DXL_FLEXCAN1_RX 1 +#define IMX8DXL_FLEXCAN1_RX_ADMA_FTM_CH2 IMX8DXL_FLEXCAN1_RX 2 +#define IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD IMX8DXL_FLEXCAN1_RX 3 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO1_IO17 IMX8DXL_FLEXCAN1_RX 4 +#define IMX8DXL_FLEXCAN1_RX_LSIO_GPIO6_IO10 IMX8DXL_FLEXCAN1_RX 5 +#define IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX IMX8DXL_FLEXCAN1_TX 0 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI3_RXC IMX8DXL_FLEXCAN1_TX 1 +#define IMX8DXL_FLEXCAN1_TX_ADMA_DMA0_REQ_IN0 IMX8DXL_FLEXCAN1_TX 2 +#define IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD IMX8DXL_FLEXCAN1_TX 3 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO1_IO18 IMX8DXL_FLEXCAN1_TX 4 +#define IMX8DXL_FLEXCAN1_TX_LSIO_GPIO6_IO11 IMX8DXL_FLEXCAN1_TX 5 +#define IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX IMX8DXL_FLEXCAN2_RX 0 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI3_RXD IMX8DXL_FLEXCAN2_RX 1 +#define IMX8DXL_FLEXCAN2_RX_ADMA_UART3_RX IMX8DXL_FLEXCAN2_RX 2 +#define IMX8DXL_FLEXCAN2_RX_ADMA_SAI1_RXFS IMX8DXL_FLEXCAN2_RX 3 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO1_IO19 IMX8DXL_FLEXCAN2_RX 4 +#define IMX8DXL_FLEXCAN2_RX_LSIO_GPIO6_IO12 IMX8DXL_FLEXCAN2_RX 5 +#define IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX IMX8DXL_FLEXCAN2_TX 0 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI3_RXFS IMX8DXL_FLEXCAN2_TX 1 +#define IMX8DXL_FLEXCAN2_TX_ADMA_UART3_TX IMX8DXL_FLEXCAN2_TX 2 +#define IMX8DXL_FLEXCAN2_TX_ADMA_SAI1_RXC IMX8DXL_FLEXCAN2_TX 3 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO1_IO20 IMX8DXL_FLEXCAN2_TX 4 +#define IMX8DXL_FLEXCAN2_TX_LSIO_GPIO6_IO13 IMX8DXL_FLEXCAN2_TX 5 +#define IMX8DXL_UART0_RX_ADMA_UART0_RX IMX8DXL_UART0_RX 0 +#define IMX8DXL_UART0_RX_ADMA_MQS_R IMX8DXL_UART0_RX 1 +#define IMX8DXL_UART0_RX_ADMA_FLEXCAN0_RX IMX8DXL_UART0_RX 2 +#define IMX8DXL_UART0_RX_SCU_UART0_RX IMX8DXL_UART0_RX 3 +#define IMX8DXL_UART0_RX_LSIO_GPIO1_IO21 IMX8DXL_UART0_RX 4 +#define IMX8DXL_UART0_RX_LSIO_GPIO6_IO14 IMX8DXL_UART0_RX 5 +#define IMX8DXL_UART0_TX_ADMA_UART0_TX IMX8DXL_UART0_TX 0 +#define IMX8DXL_UART0_TX_ADMA_MQS_L IMX8DXL_UART0_TX 1 +#define IMX8DXL_UART0_TX_ADMA_FLEXCAN0_TX IMX8DXL_UART0_TX 2 +#define IMX8DXL_UART0_TX_SCU_UART0_TX IMX8DXL_UART0_TX 3 +#define IMX8DXL_UART0_TX_LSIO_GPIO1_IO22 IMX8DXL_UART0_TX 4 +#define IMX8DXL_UART0_TX_LSIO_GPIO6_IO15 IMX8DXL_UART0_TX 5 +#define IMX8DXL_UART2_TX_ADMA_UART2_TX IMX8DXL_UART2_TX 0 +#define IMX8DXL_UART2_TX_ADMA_FTM_CH1 IMX8DXL_UART2_TX 1 +#define IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX IMX8DXL_UART2_TX 2 +#define IMX8DXL_UART2_TX_LSIO_GPIO1_IO23 IMX8DXL_UART2_TX 4 +#define IMX8DXL_UART2_TX_LSIO_GPIO6_IO16 IMX8DXL_UART2_TX 5 +#define IMX8DXL_UART2_RX_ADMA_UART2_RX IMX8DXL_UART2_RX 0 +#define IMX8DXL_UART2_RX_ADMA_FTM_CH0 IMX8DXL_UART2_RX 1 +#define IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX IMX8DXL_UART2_RX 2 +#define IMX8DXL_UART2_RX_LSIO_GPIO1_IO24 IMX8DXL_UART2_RX 4 +#define IMX8DXL_UART2_RX_LSIO_GPIO6_IO17 IMX8DXL_UART2_RX 5 +#define IMX8DXL_JTAG_TRST_B_SCU_JTAG_TRST_B IMX8DXL_JTAG_TRST_B 0 +#define IMX8DXL_JTAG_TRST_B_SCU_WDOG0_WDOG_OUT IMX8DXL_JTAG_TRST_B 1 +#define IMX8DXL_PMIC_I2C_SCL_SCU_PMIC_I2C_SCL IMX8DXL_PMIC_I2C_SCL 0 +#define IMX8DXL_PMIC_I2C_SCL_SCU_GPIO0_IOXX_PMIC_A35_ON IMX8DXL_PMIC_I2C_SCL 1 +#define IMX8DXL_PMIC_I2C_SCL_LSIO_GPIO2_IO01 IMX8DXL_PMIC_I2C_SCL 4 +#define IMX8DXL_PMIC_I2C_SDA_SCU_PMIC_I2C_SDA IMX8DXL_PMIC_I2C_SDA 0 +#define IMX8DXL_PMIC_I2C_SDA_SCU_GPIO0_IOXX_PMIC_GPU_ON IMX8DXL_PMIC_I2C_SDA 1 +#define IMX8DXL_PMIC_I2C_SDA_LSIO_GPIO2_IO02 IMX8DXL_PMIC_I2C_SDA 4 +#define IMX8DXL_PMIC_INT_B_SCU_DSC_PMIC_INT_B IMX8DXL_PMIC_INT_B 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_GPIO0_IO00 IMX8DXL_SCU_GPIO0_00 0 +#define IMX8DXL_SCU_GPIO0_00_SCU_UART0_RX IMX8DXL_SCU_GPIO0_00 1 +#define IMX8DXL_SCU_GPIO0_00_M40_UART0_RX IMX8DXL_SCU_GPIO0_00 2 +#define IMX8DXL_SCU_GPIO0_00_ADMA_UART3_RX IMX8DXL_SCU_GPIO0_00 3 +#define IMX8DXL_SCU_GPIO0_00_LSIO_GPIO2_IO03 IMX8DXL_SCU_GPIO0_00 4 +#define IMX8DXL_SCU_GPIO0_01_SCU_GPIO0_IO01 IMX8DXL_SCU_GPIO0_01 0 +#define IMX8DXL_SCU_GPIO0_01_SCU_UART0_TX IMX8DXL_SCU_GPIO0_01 1 +#define IMX8DXL_SCU_GPIO0_01_M40_UART0_TX IMX8DXL_SCU_GPIO0_01 2 +#define IMX8DXL_SCU_GPIO0_01_ADMA_UART3_TX IMX8DXL_SCU_GPIO0_01 3 +#define IMX8DXL_SCU_GPIO0_01_SCU_WDOG0_WDOG_OUT IMX8DXL_SCU_GPIO0_01 4 +#define IMX8DXL_SCU_PMIC_STANDBY_SCU_DSC_PMIC_STANDBY IMX8DXL_SCU_PMIC_STANDBY 0 +#define IMX8DXL_SCU_BOOT_MODE1_SCU_DSC_BOOT_MODE1 IMX8DXL_SCU_BOOT_MODE1 0 +#define IMX8DXL_SCU_BOOT_MODE0_SCU_DSC_BOOT_MODE0 IMX8DXL_SCU_BOOT_MODE0 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_BOOT_MODE2 IMX8DXL_SCU_BOOT_MODE2 0 +#define IMX8DXL_SCU_BOOT_MODE2_SCU_DSC_RTC_CLOCK_OUTPUT_32K IMX8DXL_SCU_BOOT_MODE2 1 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN IMX8DXL_SNVS_TAMPER_OUT1 4 +#define IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO6_IO19_IN IMX8DXL_SNVS_TAMPER_OUT1 5 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN IMX8DXL_SNVS_TAMPER_OUT2 4 +#define IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO6_IO20_IN IMX8DXL_SNVS_TAMPER_OUT2 5 +#define IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC IMX8DXL_SNVS_TAMPER_OUT3 2 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO2_IO07_IN IMX8DXL_SNVS_TAMPER_OUT3 4 +#define IMX8DXL_SNVS_TAMPER_OUT3_LSIO_GPIO6_IO21_IN IMX8DXL_SNVS_TAMPER_OUT3 5 +#define IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD IMX8DXL_SNVS_TAMPER_OUT4 2 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN IMX8DXL_SNVS_TAMPER_OUT4 4 +#define IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO6_IO22_IN IMX8DXL_SNVS_TAMPER_OUT4 5 +#define IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS IMX8DXL_SNVS_TAMPER_IN0 2 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN IMX8DXL_SNVS_TAMPER_IN0 4 +#define IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO6_IO23_IN IMX8DXL_SNVS_TAMPER_IN0 5 +#define IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC IMX8DXL_SNVS_TAMPER_IN1 2 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN IMX8DXL_SNVS_TAMPER_IN1 4 +#define IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO6_IO24_IN IMX8DXL_SNVS_TAMPER_IN1 5 +#define IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD IMX8DXL_SNVS_TAMPER_IN2 2 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN IMX8DXL_SNVS_TAMPER_IN2 4 +#define IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO6_IO25_IN IMX8DXL_SNVS_TAMPER_IN2 5 +#define IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS IMX8DXL_SNVS_TAMPER_IN3 2 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO2_IO12_IN IMX8DXL_SNVS_TAMPER_IN3 4 +#define IMX8DXL_SNVS_TAMPER_IN3_LSIO_GPIO6_IO26_IN IMX8DXL_SNVS_TAMPER_IN3 5 +#define IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA IMX8DXL_SPI1_SCK 2 +#define IMX8DXL_SPI1_SCK_ADMA_SPI1_SCK IMX8DXL_SPI1_SCK 3 +#define IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 IMX8DXL_SPI1_SCK 4 +#define IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL IMX8DXL_SPI1_SDO 2 +#define IMX8DXL_SPI1_SDO_ADMA_SPI1_SDO IMX8DXL_SPI1_SDO 3 +#define IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 IMX8DXL_SPI1_SDO 4 +#define IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL IMX8DXL_SPI1_SDI 2 +#define IMX8DXL_SPI1_SDI_ADMA_SPI1_SDI IMX8DXL_SPI1_SDI 3 +#define IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 IMX8DXL_SPI1_SDI 4 +#define IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA IMX8DXL_SPI1_CS0 2 +#define IMX8DXL_SPI1_CS0_ADMA_SPI1_CS0 IMX8DXL_SPI1_CS0 3 +#define IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 IMX8DXL_SPI1_CS0 4 +#define IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 IMX8DXL_QSPI0A_DATA1 0 +#define IMX8DXL_QSPI0A_DATA1_LSIO_GPIO3_IO10 IMX8DXL_QSPI0A_DATA1 4 +#define IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 IMX8DXL_QSPI0A_DATA0 0 +#define IMX8DXL_QSPI0A_DATA0_LSIO_GPIO3_IO09 IMX8DXL_QSPI0A_DATA0 4 +#define IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 IMX8DXL_QSPI0A_DATA3 0 +#define IMX8DXL_QSPI0A_DATA3_LSIO_GPIO3_IO12 IMX8DXL_QSPI0A_DATA3 4 +#define IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 IMX8DXL_QSPI0A_DATA2 0 +#define IMX8DXL_QSPI0A_DATA2_LSIO_GPIO3_IO11 IMX8DXL_QSPI0A_DATA2 4 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B IMX8DXL_QSPI0A_SS0_B 0 +#define IMX8DXL_QSPI0A_SS0_B_LSIO_GPIO3_IO14 IMX8DXL_QSPI0A_SS0_B 4 +#define IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS IMX8DXL_QSPI0A_DQS 0 +#define IMX8DXL_QSPI0A_DQS_LSIO_GPIO3_IO13 IMX8DXL_QSPI0A_DQS 4 +#define IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK IMX8DXL_QSPI0A_SCLK 0 +#define IMX8DXL_QSPI0A_SCLK_LSIO_GPIO3_IO16 IMX8DXL_QSPI0A_SCLK 4 +#define IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK IMX8DXL_QSPI0B_SCLK 0 +#define IMX8DXL_QSPI0B_SCLK_LSIO_GPIO3_IO17 IMX8DXL_QSPI0B_SCLK 4 +#define IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS IMX8DXL_QSPI0B_DQS 0 +#define IMX8DXL_QSPI0B_DQS_LSIO_GPIO3_IO22 IMX8DXL_QSPI0B_DQS 4 +#define IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 IMX8DXL_QSPI0B_DATA1 0 +#define IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 IMX8DXL_QSPI0B_DATA1 4 +#define IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 IMX8DXL_QSPI0B_DATA0 0 +#define IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 IMX8DXL_QSPI0B_DATA0 4 +#define IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 IMX8DXL_QSPI0B_DATA3 0 +#define IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 IMX8DXL_QSPI0B_DATA3 4 +#define IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 IMX8DXL_QSPI0B_DATA2 0 +#define IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 IMX8DXL_QSPI0B_DATA2 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B IMX8DXL_QSPI0B_SS0_B 0 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_GPIO3_IO23 IMX8DXL_QSPI0B_SS0_B 4 +#define IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0A_SS1_B IMX8DXL_QSPI0B_SS0_B 5 + +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0 +#define IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8DXL_COMP_CTL_GPIO_3V3_USB3IO 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0 +#define IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8DXL_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0 + +#endif From 6aba6ed879b3471903c8ada28ba968a268df6143 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:41 +0300 Subject: [PATCH 17/72] pinctrl: mcp23s08: Get rid of legacy platform data Platform data is a legacy interface to supply device properties to the driver. In this case we even don't have in-kernel users for it. Just remove it for good. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-1-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 42 +++++++++--------------------- include/linux/spi/mcp23s08.h | 18 ------------- 2 files changed, 12 insertions(+), 48 deletions(-) delete mode 100644 include/linux/spi/mcp23s08.h diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 3a235487e38d..2c8b8c45b70e 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -914,16 +913,9 @@ MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); static int mcp230xx_probe(struct i2c_client *client, const struct i2c_device_id *id) { - struct mcp23s08_platform_data *pdata, local_pdata; struct mcp23s08 *mcp; int status; - pdata = dev_get_platdata(&client->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - } - mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); if (!mcp) return -ENOMEM; @@ -937,7 +929,7 @@ static int mcp230xx_probe(struct i2c_client *client, mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, - id->driver_data, pdata->base, 0); + id->driver_data, -1, 0); if (status) return status; @@ -986,13 +978,13 @@ static void mcp23s08_i2c_exit(void) { } static int mcp23s08_probe(struct spi_device *spi) { - struct mcp23s08_platform_data *pdata, local_pdata; unsigned addr; int chips = 0; struct mcp23s08_driver_data *data; int status, type; unsigned ngpio = 0; const struct of_device_id *match; + u32 spi_present_mask; match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); if (match) @@ -1000,32 +992,24 @@ static int mcp23s08_probe(struct spi_device *spi) else type = spi_get_device_id(spi)->driver_data; - pdata = dev_get_platdata(&spi->dev); - if (!pdata) { - pdata = &local_pdata; - pdata->base = -1; - + status = device_property_read_u32(&spi->dev, + "microchip,spi-present-mask", &spi_present_mask); + if (status) { status = device_property_read_u32(&spi->dev, - "microchip,spi-present-mask", &pdata->spi_present_mask); + "mcp,spi-present-mask", &spi_present_mask); if (status) { - status = device_property_read_u32(&spi->dev, - "mcp,spi-present-mask", - &pdata->spi_present_mask); - - if (status) { - dev_err(&spi->dev, "missing spi-present-mask"); - return -ENODEV; - } + dev_err(&spi->dev, "missing spi-present-mask"); + return -ENODEV; } } - if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) { + if (!spi_present_mask || spi_present_mask > 0xff) { dev_err(&spi->dev, "invalid spi-present-mask"); return -ENODEV; } for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (pdata->spi_present_mask & BIT(addr)) + if (spi_present_mask & BIT(addr)) chips++; } @@ -1040,7 +1024,7 @@ static int mcp23s08_probe(struct spi_device *spi) spi_set_drvdata(spi, data); for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (!(pdata->spi_present_mask & BIT(addr))) + if (!(spi_present_mask & BIT(addr))) continue; chips--; data->mcp[addr] = &data->chip[chips]; @@ -1054,12 +1038,10 @@ static int mcp23s08_probe(struct spi_device *spi) mcp23s08_irq_bus_unlock; status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, 0x40 | (addr << 1), type, - pdata->base, addr); + -1, addr); if (status < 0) return status; - if (pdata->base != -1) - pdata->base += data->mcp[addr]->chip.ngpio; ngpio += data->mcp[addr]->chip.ngpio; } data->ngpio = ngpio; diff --git a/include/linux/spi/mcp23s08.h b/include/linux/spi/mcp23s08.h deleted file mode 100644 index 738a45b435f2..000000000000 --- a/include/linux/spi/mcp23s08.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -struct mcp23s08_platform_data { - /* For mcp23s08, up to 4 slaves (numbered 0..3) can share one SPI - * chipselect, each providing 1 gpio_chip instance with 8 gpios. - * For mpc23s17, up to 8 slaves (numbered 0..7) can share one SPI - * chipselect, each providing 1 gpio_chip (port A + port B) with - * 16 gpios. - */ - u32 spi_present_mask; - - /* "base" is the number of the first GPIO or -1 for dynamic - * assignment. If there are gaps in chip addressing the GPIO - * numbers are sequential .. so for example if only slaves 0 - * and 3 are present, their GPIOs range from base to base+15 - * (or base+31 for s17 variant). - */ - unsigned base; -}; From 84d02e785d34be9363a825d696cca1f07fac2634 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:42 +0300 Subject: [PATCH 18/72] pinctrl: mcp23s08: Deduplicate IRQ chip filling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In both cases, SPI and I²C, IRQ chip is filled in the same way. Deduplicate this by moving common part to mcp23s08_probe_one(). Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-2-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 2c8b8c45b70e..e05219d3331f 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -669,7 +669,14 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->dev = dev; mcp->addr = addr; + mcp->irq_active_high = false; + mcp->irq_chip.name = dev_name(dev); + mcp->irq_chip.irq_mask = mcp23s08_irq_mask; + mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; + mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; + mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; + mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; mcp->chip.direction_input = mcp23s08_direction_input; mcp->chip.get = mcp23s08_get; @@ -921,12 +928,6 @@ static int mcp230xx_probe(struct i2c_client *client, return -ENOMEM; mcp->irq = client->irq; - mcp->irq_chip.name = dev_name(&client->dev); - mcp->irq_chip.irq_mask = mcp23s08_irq_mask; - mcp->irq_chip.irq_unmask = mcp23s08_irq_unmask; - mcp->irq_chip.irq_set_type = mcp23s08_irq_set_type; - mcp->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - mcp->irq_chip.irq_bus_sync_unlock = mcp23s08_irq_bus_unlock; status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, id->driver_data, -1, 0); @@ -1029,13 +1030,6 @@ static int mcp23s08_probe(struct spi_device *spi) chips--; data->mcp[addr] = &data->chip[chips]; data->mcp[addr]->irq = spi->irq; - data->mcp[addr]->irq_chip.name = dev_name(&spi->dev); - data->mcp[addr]->irq_chip.irq_mask = mcp23s08_irq_mask; - data->mcp[addr]->irq_chip.irq_unmask = mcp23s08_irq_unmask; - data->mcp[addr]->irq_chip.irq_set_type = mcp23s08_irq_set_type; - data->mcp[addr]->irq_chip.irq_bus_lock = mcp23s08_irq_bus_lock; - data->mcp[addr]->irq_chip.irq_bus_sync_unlock = - mcp23s08_irq_bus_unlock; status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, 0x40 | (addr << 1), type, -1, addr); From d3da29b628a86777d25c741c44b8af35f10020a0 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:43 +0300 Subject: [PATCH 19/72] =?UTF-8?q?pinctrl:=20mcp23s08:=20Consolidate=20SPI?= =?UTF-8?q?=20and=20I=C2=B2C=20code?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are three parts of each, SPI and I²C, driver spread over the code under ifdeffery. Consolidate them so it will be only one for SPI and one for I²C. The code has been cosmetically changed to avoid intrusive change. Clean up is considered in the nearest future. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-3-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 461 +++++++++++++++-------------- 1 file changed, 233 insertions(+), 228 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index e05219d3331f..30a5b6bfbb86 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -27,8 +27,6 @@ #define MCP_TYPE_S18 4 #define MCP_TYPE_018 5 -#define MCP_MAX_DEV_PER_CS 8 - /* Registers are all 8 bits wide. * * The mcp23s17 has twice as many bits, and can be configured to work @@ -308,80 +306,6 @@ static const struct pinconf_ops mcp_pinconf_ops = { /*----------------------------------------------------------------------*/ -#ifdef CONFIG_SPI_MASTER - -static int mcp23sxx_spi_write(void *context, const void *data, size_t count) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = data, .len = count, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_gather_write(void *context, - const void *reg, size_t reg_size, - const void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = reg, .len = reg_size, }, - { .tx_buf = val, .len = val_size, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - spi_message_add_tail(&t[2], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, - void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - u8 tx[2]; - - if (reg_size != 1) - return -EINVAL; - - tx[0] = mcp->addr | 0x01; - tx[1] = *((u8 *) reg); - - return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); -} - -static const struct regmap_bus mcp23sxx_spi_regmap = { - .write = mcp23sxx_spi_write, - .gather_write = mcp23sxx_spi_gather_write, - .read = mcp23sxx_spi_read, -}; - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -/* A given spi_device can represent up to eight mcp23sxx chips - * sharing the same chipselect but using different addresses - * (e.g. chips #0 and #3 might be populated, but not #1 or $2). - * Driver data holds all the per-chip data. - */ -struct mcp23s08_driver_data { - unsigned ngpio; - struct mcp23s08 *mcp[8]; - struct mcp23s08 chip[]; -}; - - static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset) { struct mcp23s08 *mcp = gpiochip_get_data(chip); @@ -656,14 +580,12 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) /*----------------------------------------------------------------------*/ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, - void *data, unsigned addr, unsigned type, + unsigned int addr, unsigned int type, unsigned int base, int cs) { int status, ret; bool mirror = false; bool open_drain = false; - struct regmap_config *one_regmap_config = NULL; - int raw_chip_address = (addr & ~0x40) >> 1; mutex_init(&mcp->lock); @@ -687,83 +609,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, mcp->chip.of_node = dev->of_node; #endif - switch (type) { -#ifdef CONFIG_SPI_MASTER - case MCP_TYPE_S08: - case MCP_TYPE_S17: - switch (type) { - case MCP_TYPE_S08: - one_regmap_config = - devm_kmemdup(dev, &mcp23x08_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s08.%d", raw_chip_address); - break; - case MCP_TYPE_S17: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s17.%d", raw_chip_address); - break; - } - if (!one_regmap_config) - return -ENOMEM; - - one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address); - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - break; - - case MCP_TYPE_S18: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - if (!one_regmap_config) - return -ENOMEM; - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23s18"; - break; -#endif /* CONFIG_SPI_MASTER */ - -#if IS_ENABLED(CONFIG_I2C) - case MCP_TYPE_008: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = "mcp23008"; - break; - - case MCP_TYPE_017: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23017"; - break; - - case MCP_TYPE_018: - mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23018"; - break; -#endif /* CONFIG_I2C */ - - default: - dev_err(dev, "invalid device type (%d)\n", type); - return -EINVAL; - } - - if (IS_ERR(mcp->regmap)) - return PTR_ERR(mcp->regmap); - mcp->chip.base = base; mcp->chip.can_sleep = true; mcp->chip.parent = dev; @@ -822,14 +667,6 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, goto fail; } - if (one_regmap_config) { - mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, - "mcp23xxx-pinctrl.%d", raw_chip_address); - if (!mcp->pinctrl_desc.name) - return -ENOMEM; - } else { - mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; - } mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops; mcp->pinctrl_desc.confops = &mcp_pinconf_ops; mcp->pinctrl_desc.npins = mcp->chip.ngpio; @@ -856,36 +693,72 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, /*----------------------------------------------------------------------*/ -#ifdef CONFIG_OF -#ifdef CONFIG_SPI_MASTER -static const struct of_device_id mcp23s08_spi_of_match[] = { - { - .compatible = "microchip,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "microchip,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { - .compatible = "microchip,mcp23s18", - .data = (void *) MCP_TYPE_S18, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "mcp,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, +#if IS_ENABLED(CONFIG_I2C) + +static int mcp230xx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + unsigned int type = id->driver_data; + struct mcp23s08 *mcp; + int status; + + mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); + if (!mcp) + return -ENOMEM; + + mcp->irq = client->irq; + + switch (type) { + case MCP_TYPE_008: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = "mcp23008"; + break; + + case MCP_TYPE_017: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23017"; + break; + + case MCP_TYPE_018: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23018"; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + + status = mcp23s08_probe_one(mcp, dev, client->addr, type, -1, 0); + if (status) + return status; + + i2c_set_clientdata(client, mcp); + + return 0; +} + +static const struct i2c_device_id mcp230xx_id[] = { + { "mcp23008", MCP_TYPE_008 }, + { "mcp23017", MCP_TYPE_017 }, + { "mcp23018", MCP_TYPE_018 }, { }, }; -MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); -#endif +MODULE_DEVICE_TABLE(i2c, mcp230xx_id); -#if IS_ENABLED(CONFIG_I2C) +#ifdef CONFIG_OF static const struct of_device_id mcp23s08_i2c_of_match[] = { { .compatible = "microchip,mcp23008", @@ -911,42 +784,8 @@ static const struct of_device_id mcp23s08_i2c_of_match[] = { { }, }; MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); -#endif #endif /* CONFIG_OF */ - -#if IS_ENABLED(CONFIG_I2C) - -static int mcp230xx_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct mcp23s08 *mcp; - int status; - - mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); - if (!mcp) - return -ENOMEM; - - mcp->irq = client->irq; - - status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr, - id->driver_data, -1, 0); - if (status) - return status; - - i2c_set_clientdata(client, mcp); - - return 0; -} - -static const struct i2c_device_id mcp230xx_id[] = { - { "mcp23008", MCP_TYPE_008 }, - { "mcp23017", MCP_TYPE_017 }, - { "mcp23018", MCP_TYPE_018 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, mcp230xx_id); - static struct i2c_driver mcp230xx_driver = { .driver = { .name = "mcp230xx", @@ -977,8 +816,138 @@ static void mcp23s08_i2c_exit(void) { } #ifdef CONFIG_SPI_MASTER +#define MCP_MAX_DEV_PER_CS 8 + +static int mcp23sxx_spi_write(void *context, const void *data, size_t count) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = data, .len = count, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = reg, .len = reg_size, }, + { .tx_buf = val, .len = val_size, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + u8 tx[2]; + + if (reg_size != 1) + return -EINVAL; + + tx[0] = mcp->addr | 0x01; + tx[1] = *((u8 *) reg); + + return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); +} + +static const struct regmap_bus mcp23sxx_spi_regmap = { + .write = mcp23sxx_spi_write, + .gather_write = mcp23sxx_spi_gather_write, + .read = mcp23sxx_spi_read, +}; + +/* A given spi_device can represent up to eight mcp23sxx chips + * sharing the same chipselect but using different addresses + * (e.g. chips #0 and #3 might be populated, but not #1 or $2). + * Driver data holds all the per-chip data. + */ +struct mcp23s08_driver_data { + unsigned ngpio; + struct mcp23s08 *mcp[8]; + struct mcp23s08 chip[]; +}; + +static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type) +{ + struct regmap_config *one_regmap_config = NULL; + + switch (type) { + case MCP_TYPE_S08: + case MCP_TYPE_S17: + switch (type) { + case MCP_TYPE_S08: + one_regmap_config = + devm_kmemdup(dev, &mcp23x08_regmap, + sizeof(struct regmap_config), GFP_KERNEL); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, + "mcp23s08.%d", addr); + break; + case MCP_TYPE_S17: + one_regmap_config = + devm_kmemdup(dev, &mcp23x17_regmap, + sizeof(struct regmap_config), GFP_KERNEL); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, + "mcp23s17.%d", addr); + break; + } + if (!one_regmap_config) + return -ENOMEM; + + one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, + one_regmap_config); + break; + + case MCP_TYPE_S18: + one_regmap_config = + devm_kmemdup(dev, &mcp23x17_regmap, + sizeof(struct regmap_config), GFP_KERNEL); + if (!one_regmap_config) + return -ENOMEM; + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, + one_regmap_config); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23s18"; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + return 0; +} + static int mcp23s08_probe(struct spi_device *spi) { + struct device *dev = &spi->dev; unsigned addr; int chips = 0; struct mcp23s08_driver_data *data; @@ -1030,9 +999,17 @@ static int mcp23s08_probe(struct spi_device *spi) chips--; data->mcp[addr] = &data->chip[chips]; data->mcp[addr]->irq = spi->irq; - status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi, - 0x40 | (addr << 1), type, - -1, addr); + + status = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); + if (status) + return status; + + data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, + "mcp23xxx-pinctrl.%d", addr); + if (!data->mcp[addr]->pinctrl_desc.name) + return -ENOMEM; + + status = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1, addr); if (status < 0) return status; @@ -1051,6 +1028,34 @@ static const struct spi_device_id mcp23s08_ids[] = { }; MODULE_DEVICE_TABLE(spi, mcp23s08_ids); +#ifdef CONFIG_OF +static const struct of_device_id mcp23s08_spi_of_match[] = { + { + .compatible = "microchip,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "microchip,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { + .compatible = "microchip,mcp23s18", + .data = (void *) MCP_TYPE_S18, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "mcp,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { }, +}; +MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); +#endif + static struct spi_driver mcp23s08_driver = { .probe = mcp23s08_probe, .id_table = mcp23s08_ids, From 0521701c8d10f832a401cc7ebfa92bb73782d792 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:44 +0300 Subject: [PATCH 20/72] pinctrl: mcp23s08: Drop unused parameter in mcp23s08_probe_one() The cs parameter in mcp23s08_probe_one() is never used. Drop it for good. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-4-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 30a5b6bfbb86..513864c74860 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -581,7 +581,7 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, unsigned int addr, unsigned int type, - unsigned int base, int cs) + unsigned int base) { int status, ret; bool mirror = false; @@ -741,7 +741,7 @@ static int mcp230xx_probe(struct i2c_client *client, mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; - status = mcp23s08_probe_one(mcp, dev, client->addr, type, -1, 0); + status = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); if (status) return status; @@ -1009,7 +1009,7 @@ static int mcp23s08_probe(struct spi_device *spi) if (!data->mcp[addr]->pinctrl_desc.name) return -ENOMEM; - status = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1, addr); + status = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); if (status < 0) return status; From 0874758ecb2b3faa200a86dda45dbc29335f883e Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:45 +0300 Subject: [PATCH 21/72] pinctrl: mcp23s08: Refactor mcp23s08_spi_regmap_init() There is a lot of duplication for one small helper function. Refactor mcp23s08_spi_regmap_init() to prepare everything first and then register regmap at the end. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-5-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 63 ++++++++++++++---------------- 1 file changed, 29 insertions(+), 34 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 513864c74860..07b69242a5b3 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -888,50 +888,38 @@ struct mcp23s08_driver_data { static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, unsigned int addr, unsigned int type) { - struct regmap_config *one_regmap_config = NULL; + const struct regmap_config *config; + struct regmap_config *copy; + const char *name; switch (type) { case MCP_TYPE_S08: - case MCP_TYPE_S17: - switch (type) { - case MCP_TYPE_S08: - one_regmap_config = - devm_kmemdup(dev, &mcp23x08_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s08.%d", addr); - break; - case MCP_TYPE_S17: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, - "mcp23s17.%d", addr); - break; - } - if (!one_regmap_config) - return -ENOMEM; + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", + addr); - one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); + config = &mcp23x08_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S17: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", + addr); + + config = &mcp23x17_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); break; case MCP_TYPE_S18: - one_regmap_config = - devm_kmemdup(dev, &mcp23x17_regmap, - sizeof(struct regmap_config), GFP_KERNEL); - if (!one_regmap_config) - return -ENOMEM; - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, - one_regmap_config); mcp->reg_shift = 1; mcp->chip.ngpio = 16; mcp->chip.label = "mcp23s18"; + + config = &mcp23x17_regmap; + name = config->name; break; default: @@ -939,6 +927,13 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, return -EINVAL; } + copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); + if (!copy) + return -ENOMEM; + + copy->name = name; + + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); if (IS_ERR(mcp->regmap)) return PTR_ERR(mcp->regmap); From 88af89b52a1b7493f1e5ec165856b4c6767cf654 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:46 +0300 Subject: [PATCH 22/72] pinctrl: mcp23s08: Propagate error code from device_property_read_u32() Return error code from device_property_read_u32() as is in mcp23s08_probe(). While here, drop status variable in mcp23s08_irq_set_type() which always 0. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-6-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 07b69242a5b3..515d1aa32732 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -485,7 +485,6 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(data); struct mcp23s08 *mcp = gpiochip_get_data(gc); unsigned int pos = data->hwirq; - int status = 0; if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { mcp_set_bit(mcp, MCP_INTCON, pos, false); @@ -508,7 +507,7 @@ static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type) } else return -EINVAL; - return status; + return 0; } static void mcp23s08_irq_bus_lock(struct irq_data *data) @@ -964,7 +963,7 @@ static int mcp23s08_probe(struct spi_device *spi) "mcp,spi-present-mask", &spi_present_mask); if (status) { dev_err(&spi->dev, "missing spi-present-mask"); - return -ENODEV; + return status; } } From 1ac30db20be2da288131a865b94c772512e9ad47 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:47 +0300 Subject: [PATCH 23/72] pinctrl: mcp23s08: Make use of device properties Device property API allows to gather device resources from different sources, such as ACPI. Convert the drivers to unleash the power of device property API. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-7-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 515d1aa32732..330c2203e0f2 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -11,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -20,12 +20,12 @@ /* * MCP types supported by driver */ -#define MCP_TYPE_S08 0 -#define MCP_TYPE_S17 1 -#define MCP_TYPE_008 2 -#define MCP_TYPE_017 3 -#define MCP_TYPE_S18 4 -#define MCP_TYPE_018 5 +#define MCP_TYPE_S08 1 +#define MCP_TYPE_S17 2 +#define MCP_TYPE_008 3 +#define MCP_TYPE_017 4 +#define MCP_TYPE_S18 5 +#define MCP_TYPE_018 6 /* Registers are all 8 bits wide. * @@ -757,7 +757,6 @@ static const struct i2c_device_id mcp230xx_id[] = { }; MODULE_DEVICE_TABLE(i2c, mcp230xx_id); -#ifdef CONFIG_OF static const struct of_device_id mcp23s08_i2c_of_match[] = { { .compatible = "microchip,mcp23008", @@ -783,12 +782,11 @@ static const struct of_device_id mcp23s08_i2c_of_match[] = { { }, }; MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); -#endif /* CONFIG_OF */ static struct i2c_driver mcp230xx_driver = { .driver = { .name = "mcp230xx", - .of_match_table = of_match_ptr(mcp23s08_i2c_of_match), + .of_match_table = mcp23s08_i2c_of_match, }, .probe = mcp230xx_probe, .id_table = mcp230xx_id, @@ -942,17 +940,17 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, static int mcp23s08_probe(struct spi_device *spi) { struct device *dev = &spi->dev; + const void *match; unsigned addr; int chips = 0; struct mcp23s08_driver_data *data; int status, type; unsigned ngpio = 0; - const struct of_device_id *match; u32 spi_present_mask; - match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev); + match = device_get_match_data(dev); if (match) - type = (int)(uintptr_t)match->data; + type = (int)(uintptr_t)match; else type = spi_get_device_id(spi)->driver_data; @@ -1022,7 +1020,6 @@ static const struct spi_device_id mcp23s08_ids[] = { }; MODULE_DEVICE_TABLE(spi, mcp23s08_ids); -#ifdef CONFIG_OF static const struct of_device_id mcp23s08_spi_of_match[] = { { .compatible = "microchip,mcp23s08", @@ -1048,14 +1045,13 @@ static const struct of_device_id mcp23s08_spi_of_match[] = { { }, }; MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); -#endif static struct spi_driver mcp23s08_driver = { .probe = mcp23s08_probe, .id_table = mcp23s08_ids, .driver = { .name = "mcp23s08", - .of_match_table = of_match_ptr(mcp23s08_spi_of_match), + .of_match_table = mcp23s08_spi_of_match, }, }; From 7b04aaaf660be525bf0df892a198a24ad66ac93d Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:48 +0300 Subject: [PATCH 24/72] pinctrl: mcp23s08: Use for_each_set_bit() and hweight_long() Here is a simplification of SPI code by using for_each_set_bit() and hweight_long() library functions. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-8-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 30 +++++++++++------------------- 1 file changed, 11 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index 330c2203e0f2..ea8decc36d50 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* MCP23S08 SPI/I2C GPIO driver */ +#include #include #include #include @@ -940,13 +941,14 @@ static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, static int mcp23s08_probe(struct spi_device *spi) { struct device *dev = &spi->dev; + unsigned long spi_present_mask; const void *match; + int chips; + u32 v; unsigned addr; - int chips = 0; struct mcp23s08_driver_data *data; int status, type; unsigned ngpio = 0; - u32 spi_present_mask; match = device_get_match_data(dev); if (match) @@ -954,29 +956,22 @@ static int mcp23s08_probe(struct spi_device *spi) else type = spi_get_device_id(spi)->driver_data; - status = device_property_read_u32(&spi->dev, - "microchip,spi-present-mask", &spi_present_mask); + status = device_property_read_u32(dev, "microchip,spi-present-mask", &v); if (status) { - status = device_property_read_u32(&spi->dev, - "mcp,spi-present-mask", &spi_present_mask); + status = device_property_read_u32(dev, "mcp,spi-present-mask", &v); if (status) { dev_err(&spi->dev, "missing spi-present-mask"); return status; } } + spi_present_mask = v; - if (!spi_present_mask || spi_present_mask > 0xff) { + if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) { dev_err(&spi->dev, "invalid spi-present-mask"); return -ENODEV; } - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (spi_present_mask & BIT(addr)) - chips++; - } - - if (!chips) - return -ENODEV; + chips = hweight_long(spi_present_mask); data = devm_kzalloc(&spi->dev, struct_size(data, chip, chips), GFP_KERNEL); @@ -985,11 +980,8 @@ static int mcp23s08_probe(struct spi_device *spi) spi_set_drvdata(spi, data); - for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) { - if (!(spi_present_mask & BIT(addr))) - continue; - chips--; - data->mcp[addr] = &data->chip[chips]; + for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { + data->mcp[addr] = &data->chip[--chips]; data->mcp[addr]->irq = spi->irq; status = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); From 0f04a81784fe3ddc00cae74c517265b3ddb8825c Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 7 Apr 2020 20:38:49 +0300 Subject: [PATCH 25/72] =?UTF-8?q?pinctrl:=20mcp23s08:=20Split=20to=20three?= =?UTF-8?q?=20parts:=20core,=20I=C2=B2C,=20SPI?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split the driver to three parts: core, I²C, SPI. No functional change intended. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20200407173849.43628-9-andriy.shevchenko@linux.intel.com Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 13 +- drivers/pinctrl/Makefile | 2 + drivers/pinctrl/pinctrl-mcp23s08.c | 458 +------------------------ drivers/pinctrl/pinctrl-mcp23s08.h | 52 +++ drivers/pinctrl/pinctrl-mcp23s08_i2c.c | 124 +++++++ drivers/pinctrl/pinctrl-mcp23s08_spi.c | 262 ++++++++++++++ 6 files changed, 459 insertions(+), 452 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-mcp23s08.h create mode 100644 drivers/pinctrl/pinctrl-mcp23s08_i2c.c create mode 100644 drivers/pinctrl/pinctrl-mcp23s08_spi.c diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 834c59950d1c..f646f070d98f 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -172,15 +172,22 @@ config PINCTRL_GEMINI select GENERIC_PINCONF select MFD_SYSCON +config PINCTRL_MCP23S08_I2C + tristate + select REGMAP_I2C + +config PINCTRL_MCP23S08_SPI + tristate + select REGMAP_SPI + config PINCTRL_MCP23S08 tristate "Microchip MCP23xxx I/O expander" depends on SPI_MASTER || I2C - depends on I2C || I2C=n select GPIOLIB select GPIOLIB_IRQCHIP - select REGMAP_I2C if I2C - select REGMAP_SPI if SPI_MASTER select GENERIC_PINCONF + select PINCTRL_MCP23S08_I2C if I2C + select PINCTRL_MCP23S08_SPI if SPI_MASTER help SPI/I2C driver for Microchip MCP23S08 / MCP23S17 / MCP23S18 / MCP23008 / MCP23017 / MCP23018 I/O expanders. diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0b36a1cfca8a..1731b2154df9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -21,6 +21,8 @@ obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o +obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o +obj-$(CONFIG_PINCTRL_MCP23S08_SPI) += pinctrl-mcp23s08_spi.o obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o obj-$(CONFIG_PINCTRL_MESON) += meson/ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index ea8decc36d50..cb545557dcd4 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -7,9 +7,8 @@ #include #include #include +#include #include -#include -#include #include #include #include @@ -18,15 +17,7 @@ #include #include -/* - * MCP types supported by driver - */ -#define MCP_TYPE_S08 1 -#define MCP_TYPE_S17 2 -#define MCP_TYPE_008 3 -#define MCP_TYPE_017 4 -#define MCP_TYPE_S18 5 -#define MCP_TYPE_018 6 +#include "pinctrl-mcp23s08.h" /* Registers are all 8 bits wide. * @@ -51,31 +42,6 @@ #define MCP_GPIO 0x09 #define MCP_OLAT 0x0a -struct mcp23s08; - -struct mcp23s08 { - u8 addr; - bool irq_active_high; - bool reg_shift; - - u16 irq_rise; - u16 irq_fall; - int irq; - bool irq_controller; - int cached_gpio; - /* lock protects regmap access with bypass/cache flags */ - struct mutex lock; - - struct gpio_chip chip; - struct irq_chip irq_chip; - - struct regmap *regmap; - struct device *dev; - - struct pinctrl_dev *pctldev; - struct pinctrl_desc pinctrl_desc; -}; - static const struct reg_default mcp23x08_defaults[] = { {.reg = MCP_IODIR, .def = 0xff}, {.reg = MCP_IPOL, .def = 0x00}, @@ -107,7 +73,7 @@ static const struct regmap_access_table mcp23x08_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x08_regmap = { +const struct regmap_config mcp23x08_regmap = { .reg_bits = 8, .val_bits = 8, @@ -119,6 +85,7 @@ static const struct regmap_config mcp23x08_regmap = { .cache_type = REGCACHE_FLAT, .max_register = MCP_OLAT, }; +EXPORT_SYMBOL_GPL(mcp23x08_regmap); static const struct reg_default mcp23x16_defaults[] = { {.reg = MCP_IODIR << 1, .def = 0xffff}, @@ -151,7 +118,7 @@ static const struct regmap_access_table mcp23x16_precious_table = { .n_yes_ranges = 1, }; -static const struct regmap_config mcp23x17_regmap = { +const struct regmap_config mcp23x17_regmap = { .reg_bits = 8, .val_bits = 16, @@ -164,6 +131,7 @@ static const struct regmap_config mcp23x17_regmap = { .cache_type = REGCACHE_FLAT, .val_format_endian = REGMAP_ENDIAN_LITTLE, }; +EXPORT_SYMBOL_GPL(mcp23x17_regmap); static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val) { @@ -579,9 +547,8 @@ static int mcp23s08_irqchip_setup(struct mcp23s08 *mcp) /*----------------------------------------------------------------------*/ -static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, - unsigned int addr, unsigned int type, - unsigned int base) +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base) { int status, ret; bool mirror = false; @@ -690,411 +657,4 @@ static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret); return ret; } - -/*----------------------------------------------------------------------*/ - -#if IS_ENABLED(CONFIG_I2C) - -static int mcp230xx_probe(struct i2c_client *client, - const struct i2c_device_id *id) -{ - struct device *dev = &client->dev; - unsigned int type = id->driver_data; - struct mcp23s08 *mcp; - int status; - - mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL); - if (!mcp) - return -ENOMEM; - - mcp->irq = client->irq; - - switch (type) { - case MCP_TYPE_008: - mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = "mcp23008"; - break; - - case MCP_TYPE_017: - mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23017"; - break; - - case MCP_TYPE_018: - mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23018"; - break; - - default: - dev_err(dev, "invalid device type (%d)\n", type); - return -EINVAL; - } - - if (IS_ERR(mcp->regmap)) - return PTR_ERR(mcp->regmap); - - mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; - - status = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); - if (status) - return status; - - i2c_set_clientdata(client, mcp); - - return 0; -} - -static const struct i2c_device_id mcp230xx_id[] = { - { "mcp23008", MCP_TYPE_008 }, - { "mcp23017", MCP_TYPE_017 }, - { "mcp23018", MCP_TYPE_018 }, - { }, -}; -MODULE_DEVICE_TABLE(i2c, mcp230xx_id); - -static const struct of_device_id mcp23s08_i2c_of_match[] = { - { - .compatible = "microchip,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "microchip,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { - .compatible = "microchip,mcp23018", - .data = (void *) MCP_TYPE_018, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23008", - .data = (void *) MCP_TYPE_008, - }, - { - .compatible = "mcp,mcp23017", - .data = (void *) MCP_TYPE_017, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); - -static struct i2c_driver mcp230xx_driver = { - .driver = { - .name = "mcp230xx", - .of_match_table = mcp23s08_i2c_of_match, - }, - .probe = mcp230xx_probe, - .id_table = mcp230xx_id, -}; - -static int __init mcp23s08_i2c_init(void) -{ - return i2c_add_driver(&mcp230xx_driver); -} - -static void mcp23s08_i2c_exit(void) -{ - i2c_del_driver(&mcp230xx_driver); -} - -#else - -static int __init mcp23s08_i2c_init(void) { return 0; } -static void mcp23s08_i2c_exit(void) { } - -#endif /* CONFIG_I2C */ - -/*----------------------------------------------------------------------*/ - -#ifdef CONFIG_SPI_MASTER - -#define MCP_MAX_DEV_PER_CS 8 - -static int mcp23sxx_spi_write(void *context, const void *data, size_t count) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = data, .len = count, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_gather_write(void *context, - const void *reg, size_t reg_size, - const void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - struct spi_message m; - struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, - { .tx_buf = reg, .len = reg_size, }, - { .tx_buf = val, .len = val_size, }, }; - - spi_message_init(&m); - spi_message_add_tail(&t[0], &m); - spi_message_add_tail(&t[1], &m); - spi_message_add_tail(&t[2], &m); - - return spi_sync(spi, &m); -} - -static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, - void *val, size_t val_size) -{ - struct mcp23s08 *mcp = context; - struct spi_device *spi = to_spi_device(mcp->dev); - u8 tx[2]; - - if (reg_size != 1) - return -EINVAL; - - tx[0] = mcp->addr | 0x01; - tx[1] = *((u8 *) reg); - - return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); -} - -static const struct regmap_bus mcp23sxx_spi_regmap = { - .write = mcp23sxx_spi_write, - .gather_write = mcp23sxx_spi_gather_write, - .read = mcp23sxx_spi_read, -}; - -/* A given spi_device can represent up to eight mcp23sxx chips - * sharing the same chipselect but using different addresses - * (e.g. chips #0 and #3 might be populated, but not #1 or $2). - * Driver data holds all the per-chip data. - */ -struct mcp23s08_driver_data { - unsigned ngpio; - struct mcp23s08 *mcp[8]; - struct mcp23s08 chip[]; -}; - -static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, - unsigned int addr, unsigned int type) -{ - const struct regmap_config *config; - struct regmap_config *copy; - const char *name; - - switch (type) { - case MCP_TYPE_S08: - mcp->reg_shift = 0; - mcp->chip.ngpio = 8; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", - addr); - - config = &mcp23x08_regmap; - name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); - break; - - case MCP_TYPE_S17: - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", - addr); - - config = &mcp23x17_regmap; - name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); - break; - - case MCP_TYPE_S18: - mcp->reg_shift = 1; - mcp->chip.ngpio = 16; - mcp->chip.label = "mcp23s18"; - - config = &mcp23x17_regmap; - name = config->name; - break; - - default: - dev_err(dev, "invalid device type (%d)\n", type); - return -EINVAL; - } - - copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); - if (!copy) - return -ENOMEM; - - copy->name = name; - - mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); - if (IS_ERR(mcp->regmap)) - return PTR_ERR(mcp->regmap); - - return 0; -} - -static int mcp23s08_probe(struct spi_device *spi) -{ - struct device *dev = &spi->dev; - unsigned long spi_present_mask; - const void *match; - int chips; - u32 v; - unsigned addr; - struct mcp23s08_driver_data *data; - int status, type; - unsigned ngpio = 0; - - match = device_get_match_data(dev); - if (match) - type = (int)(uintptr_t)match; - else - type = spi_get_device_id(spi)->driver_data; - - status = device_property_read_u32(dev, "microchip,spi-present-mask", &v); - if (status) { - status = device_property_read_u32(dev, "mcp,spi-present-mask", &v); - if (status) { - dev_err(&spi->dev, "missing spi-present-mask"); - return status; - } - } - spi_present_mask = v; - - if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) { - dev_err(&spi->dev, "invalid spi-present-mask"); - return -ENODEV; - } - - chips = hweight_long(spi_present_mask); - - data = devm_kzalloc(&spi->dev, - struct_size(data, chip, chips), GFP_KERNEL); - if (!data) - return -ENOMEM; - - spi_set_drvdata(spi, data); - - for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { - data->mcp[addr] = &data->chip[--chips]; - data->mcp[addr]->irq = spi->irq; - - status = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); - if (status) - return status; - - data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, - "mcp23xxx-pinctrl.%d", addr); - if (!data->mcp[addr]->pinctrl_desc.name) - return -ENOMEM; - - status = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); - if (status < 0) - return status; - - ngpio += data->mcp[addr]->chip.ngpio; - } - data->ngpio = ngpio; - - return 0; -} - -static const struct spi_device_id mcp23s08_ids[] = { - { "mcp23s08", MCP_TYPE_S08 }, - { "mcp23s17", MCP_TYPE_S17 }, - { "mcp23s18", MCP_TYPE_S18 }, - { }, -}; -MODULE_DEVICE_TABLE(spi, mcp23s08_ids); - -static const struct of_device_id mcp23s08_spi_of_match[] = { - { - .compatible = "microchip,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "microchip,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { - .compatible = "microchip,mcp23s18", - .data = (void *) MCP_TYPE_S18, - }, -/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ - { - .compatible = "mcp,mcp23s08", - .data = (void *) MCP_TYPE_S08, - }, - { - .compatible = "mcp,mcp23s17", - .data = (void *) MCP_TYPE_S17, - }, - { }, -}; -MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); - -static struct spi_driver mcp23s08_driver = { - .probe = mcp23s08_probe, - .id_table = mcp23s08_ids, - .driver = { - .name = "mcp23s08", - .of_match_table = mcp23s08_spi_of_match, - }, -}; - -static int __init mcp23s08_spi_init(void) -{ - return spi_register_driver(&mcp23s08_driver); -} - -static void mcp23s08_spi_exit(void) -{ - spi_unregister_driver(&mcp23s08_driver); -} - -#else - -static int __init mcp23s08_spi_init(void) { return 0; } -static void mcp23s08_spi_exit(void) { } - -#endif /* CONFIG_SPI_MASTER */ - -/*----------------------------------------------------------------------*/ - -static int __init mcp23s08_init(void) -{ - int ret; - - ret = mcp23s08_spi_init(); - if (ret) - goto spi_fail; - - ret = mcp23s08_i2c_init(); - if (ret) - goto i2c_fail; - - return 0; - - i2c_fail: - mcp23s08_spi_exit(); - spi_fail: - return ret; -} -/* register after spi/i2c postcore initcall and before - * subsys initcalls that may rely on these GPIOs - */ -subsys_initcall(mcp23s08_init); - -static void __exit mcp23s08_exit(void) -{ - mcp23s08_spi_exit(); - mcp23s08_i2c_exit(); -} -module_exit(mcp23s08_exit); - -MODULE_LICENSE("GPL"); +EXPORT_SYMBOL_GPL(mcp23s08_probe_one); diff --git a/drivers/pinctrl/pinctrl-mcp23s08.h b/drivers/pinctrl/pinctrl-mcp23s08.h new file mode 100644 index 000000000000..90dc27081a3c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* MCP23S08 SPI/I2C GPIO driver */ + +#include +#include +#include +#include +#include + +/* + * MCP types supported by driver + */ +#define MCP_TYPE_S08 1 +#define MCP_TYPE_S17 2 +#define MCP_TYPE_008 3 +#define MCP_TYPE_017 4 +#define MCP_TYPE_S18 5 +#define MCP_TYPE_018 6 + +struct device; +struct regmap; + +struct pinctrl_dev; + +struct mcp23s08 { + u8 addr; + bool irq_active_high; + bool reg_shift; + + u16 irq_rise; + u16 irq_fall; + int irq; + bool irq_controller; + int cached_gpio; + /* lock protects regmap access with bypass/cache flags */ + struct mutex lock; + + struct gpio_chip chip; + struct irq_chip irq_chip; + + struct regmap *regmap; + struct device *dev; + + struct pinctrl_dev *pctldev; + struct pinctrl_desc pinctrl_desc; +}; + +extern const struct regmap_config mcp23x08_regmap; +extern const struct regmap_config mcp23x17_regmap; + +int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type, unsigned int base); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_i2c.c b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c new file mode 100644 index 000000000000..e0b001c8c08c --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_i2c.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 I2C GPIO driver */ + +#include +#include +#include +#include + +#include "pinctrl-mcp23s08.h" + +static int mcp230xx_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + unsigned int type = id->driver_data; + struct mcp23s08 *mcp; + int ret; + + mcp = devm_kzalloc(dev, sizeof(*mcp), GFP_KERNEL); + if (!mcp) + return -ENOMEM; + + switch (type) { + case MCP_TYPE_008: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x08_regmap); + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = "mcp23008"; + break; + + case MCP_TYPE_017: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23017"; + break; + + case MCP_TYPE_018: + mcp->regmap = devm_regmap_init_i2c(client, &mcp23x17_regmap); + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23018"; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + mcp->irq = client->irq; + mcp->pinctrl_desc.name = "mcp23xxx-pinctrl"; + + ret = mcp23s08_probe_one(mcp, dev, client->addr, type, -1); + if (ret) + return ret; + + i2c_set_clientdata(client, mcp); + + return 0; +} + +static const struct i2c_device_id mcp230xx_id[] = { + { "mcp23008", MCP_TYPE_008 }, + { "mcp23017", MCP_TYPE_017 }, + { "mcp23018", MCP_TYPE_018 }, + { } +}; +MODULE_DEVICE_TABLE(i2c, mcp230xx_id); + +static const struct of_device_id mcp23s08_i2c_of_match[] = { + { + .compatible = "microchip,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "microchip,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { + .compatible = "microchip,mcp23018", + .data = (void *) MCP_TYPE_018, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23008", + .data = (void *) MCP_TYPE_008, + }, + { + .compatible = "mcp,mcp23017", + .data = (void *) MCP_TYPE_017, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match); + +static struct i2c_driver mcp230xx_driver = { + .driver = { + .name = "mcp230xx", + .of_match_table = mcp23s08_i2c_of_match, + }, + .probe = mcp230xx_probe, + .id_table = mcp230xx_id, +}; + +static int __init mcp23s08_i2c_init(void) +{ + return i2c_add_driver(&mcp230xx_driver); +} + +/* + * Register after I²C postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_i2c_init); + +static void mcp23s08_i2c_exit(void) +{ + i2c_del_driver(&mcp230xx_driver); +} +module_exit(mcp23s08_i2c_exit); + +MODULE_LICENSE("GPL"); diff --git a/drivers/pinctrl/pinctrl-mcp23s08_spi.c b/drivers/pinctrl/pinctrl-mcp23s08_spi.c new file mode 100644 index 000000000000..e06fb885fd2b --- /dev/null +++ b/drivers/pinctrl/pinctrl-mcp23s08_spi.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* MCP23S08 SPI GPIO driver */ + +#include +#include +#include +#include +#include + +#include "pinctrl-mcp23s08.h" + +#define MCP_MAX_DEV_PER_CS 8 + +/* + * A given spi_device can represent up to eight mcp23sxx chips + * sharing the same chipselect but using different addresses + * (e.g. chips #0 and #3 might be populated, but not #1 or #2). + * Driver data holds all the per-chip data. + */ +struct mcp23s08_driver_data { + unsigned ngpio; + struct mcp23s08 *mcp[8]; + struct mcp23s08 chip[]; +}; + +static int mcp23sxx_spi_write(void *context, const void *data, size_t count) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = data, .len = count, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_gather_write(void *context, + const void *reg, size_t reg_size, + const void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + struct spi_message m; + struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, }, + { .tx_buf = reg, .len = reg_size, }, + { .tx_buf = val, .len = val_size, }, }; + + spi_message_init(&m); + spi_message_add_tail(&t[0], &m); + spi_message_add_tail(&t[1], &m); + spi_message_add_tail(&t[2], &m); + + return spi_sync(spi, &m); +} + +static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct mcp23s08 *mcp = context; + struct spi_device *spi = to_spi_device(mcp->dev); + u8 tx[2]; + + if (reg_size != 1) + return -EINVAL; + + tx[0] = mcp->addr | 0x01; + tx[1] = *((u8 *) reg); + + return spi_write_then_read(spi, tx, sizeof(tx), val, val_size); +} + +static const struct regmap_bus mcp23sxx_spi_regmap = { + .write = mcp23sxx_spi_write, + .gather_write = mcp23sxx_spi_gather_write, + .read = mcp23sxx_spi_read, +}; + +static int mcp23s08_spi_regmap_init(struct mcp23s08 *mcp, struct device *dev, + unsigned int addr, unsigned int type) +{ + const struct regmap_config *config; + struct regmap_config *copy; + const char *name; + + switch (type) { + case MCP_TYPE_S08: + mcp->reg_shift = 0; + mcp->chip.ngpio = 8; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s08.%d", addr); + + config = &mcp23x08_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S17: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL, "mcp23s17.%d", addr); + + config = &mcp23x17_regmap; + name = devm_kasprintf(dev, GFP_KERNEL, "%d", addr); + break; + + case MCP_TYPE_S18: + mcp->reg_shift = 1; + mcp->chip.ngpio = 16; + mcp->chip.label = "mcp23s18"; + + config = &mcp23x17_regmap; + name = config->name; + break; + + default: + dev_err(dev, "invalid device type (%d)\n", type); + return -EINVAL; + } + + copy = devm_kmemdup(dev, &config, sizeof(config), GFP_KERNEL); + if (!copy) + return -ENOMEM; + + copy->name = name; + + mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp, copy); + if (IS_ERR(mcp->regmap)) + return PTR_ERR(mcp->regmap); + + return 0; +} + +static int mcp23s08_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct mcp23s08_driver_data *data; + unsigned long spi_present_mask; + const void *match; + unsigned int addr; + unsigned int ngpio = 0; + int chips; + int type; + int ret; + u32 v; + + match = device_get_match_data(dev); + if (match) + type = (int)(uintptr_t)match; + else + type = spi_get_device_id(spi)->driver_data; + + ret = device_property_read_u32(dev, "microchip,spi-present-mask", &v); + if (ret) { + ret = device_property_read_u32(dev, "mcp,spi-present-mask", &v); + if (ret) { + dev_err(dev, "missing spi-present-mask"); + return ret; + } + } + spi_present_mask = v; + + if (!spi_present_mask || spi_present_mask >= BIT(MCP_MAX_DEV_PER_CS)) { + dev_err(dev, "invalid spi-present-mask"); + return -ENODEV; + } + + chips = hweight_long(spi_present_mask); + + data = devm_kzalloc(dev, struct_size(data, chip, chips), GFP_KERNEL); + if (!data) + return -ENOMEM; + + spi_set_drvdata(spi, data); + + for_each_set_bit(addr, &spi_present_mask, MCP_MAX_DEV_PER_CS) { + data->mcp[addr] = &data->chip[--chips]; + data->mcp[addr]->irq = spi->irq; + + ret = mcp23s08_spi_regmap_init(data->mcp[addr], dev, addr, type); + if (ret) + return ret; + + data->mcp[addr]->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL, + "mcp23xxx-pinctrl.%d", + addr); + if (!data->mcp[addr]->pinctrl_desc.name) + return -ENOMEM; + + ret = mcp23s08_probe_one(data->mcp[addr], dev, 0x40 | (addr << 1), type, -1); + if (ret < 0) + return ret; + + ngpio += data->mcp[addr]->chip.ngpio; + } + data->ngpio = ngpio; + + return 0; +} + +static const struct spi_device_id mcp23s08_ids[] = { + { "mcp23s08", MCP_TYPE_S08 }, + { "mcp23s17", MCP_TYPE_S17 }, + { "mcp23s18", MCP_TYPE_S18 }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp23s08_ids); + +static const struct of_device_id mcp23s08_spi_of_match[] = { + { + .compatible = "microchip,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "microchip,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { + .compatible = "microchip,mcp23s18", + .data = (void *) MCP_TYPE_S18, + }, +/* NOTE: The use of the mcp prefix is deprecated and will be removed. */ + { + .compatible = "mcp,mcp23s08", + .data = (void *) MCP_TYPE_S08, + }, + { + .compatible = "mcp,mcp23s17", + .data = (void *) MCP_TYPE_S17, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match); + +static struct spi_driver mcp23s08_driver = { + .probe = mcp23s08_probe, + .id_table = mcp23s08_ids, + .driver = { + .name = "mcp23s08", + .of_match_table = mcp23s08_spi_of_match, + }, +}; + +static int __init mcp23s08_spi_init(void) +{ + return spi_register_driver(&mcp23s08_driver); +} + +/* + * Register after SPI postcore initcall and before + * subsys initcalls that may rely on these GPIOs. + */ +subsys_initcall(mcp23s08_spi_init); + +static void mcp23s08_spi_exit(void) +{ + spi_unregister_driver(&mcp23s08_driver); +} +module_exit(mcp23s08_spi_exit); + +MODULE_LICENSE("GPL"); From 5f3b82a168d597099dfc20e47e9389c1f7d0c11b Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 14 Apr 2020 19:13:38 +0300 Subject: [PATCH 26/72] pinctrl: lynxpoint: Use platform_get_irq_optional() explicitly There is no need to repeat functionality of platform_get_irq_optional() in the driver. Replace it with explicit call to the helper. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg Reviewed-by: Linus Walleij --- drivers/pinctrl/intel/pinctrl-lynxpoint.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-lynxpoint.c b/drivers/pinctrl/intel/pinctrl-lynxpoint.c index e928742c7181..a45b8f2182fd 100644 --- a/drivers/pinctrl/intel/pinctrl-lynxpoint.c +++ b/drivers/pinctrl/intel/pinctrl-lynxpoint.c @@ -794,11 +794,11 @@ static int lp_gpio_probe(struct platform_device *pdev) const struct intel_pinctrl_soc_data *soc; struct intel_pinctrl *lg; struct gpio_chip *gc; - struct resource *io_rc, *irq_rc; struct device *dev = &pdev->dev; + struct resource *io_rc; void __iomem *regs; unsigned int i; - int ret; + int irq, ret; soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev); if (!soc) @@ -870,8 +870,8 @@ static int lp_gpio_probe(struct platform_device *pdev) gc->parent = dev; /* set up interrupts */ - irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (irq_rc && irq_rc->start) { + irq = platform_get_irq_optional(pdev, 0); + if (irq > 0) { struct gpio_irq_chip *girq; girq = &gc->irq; @@ -884,7 +884,7 @@ static int lp_gpio_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; - girq->parents[0] = (unsigned int)irq_rc->start; + girq->parents[0] = irq; girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_bad_irq; } From 5da42a3d2540732f66ae8c228d902aa7a27b4f6a Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Wed, 8 Apr 2020 07:05:04 +0000 Subject: [PATCH 27/72] pinctrl: qcom: Remove duplicated include from pinctrl-msm.c Remove duplicated include. Fixes: 13bec8d49bdf ("pinctrl: qcom: use scm_call to route GPIO irq to Apps") Signed-off-by: YueHaibing Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200408070504.134847-1-yuehaibing@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/pinctrl-msm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index 9a398a211d30..898fc041e197 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -23,7 +23,6 @@ #include #include #include -#include #include From 7045e673c2fd6465a1472f09f73f75a8edcd7e68 Mon Sep 17 00:00:00 2001 From: Jason Yan Date: Fri, 17 Apr 2020 17:21:25 +0800 Subject: [PATCH 28/72] pinctrl: mcp23s08: add module license Fix the following build warning: WARNING: modpost: missing MODULE_LICENSE() in drivers/pinctrl/pinctrl-mcp23s08.o see include/linux/module.h for more information Signed-off-by: Jason Yan Link: https://lore.kernel.org/r/20200417092125.12513-1-yanaijie@huawei.com Reported-by: Randy Dunlap Reported-by: Stephen Rothwell Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-mcp23s08.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-mcp23s08.c b/drivers/pinctrl/pinctrl-mcp23s08.c index cb545557dcd4..151931b593f6 100644 --- a/drivers/pinctrl/pinctrl-mcp23s08.c +++ b/drivers/pinctrl/pinctrl-mcp23s08.c @@ -658,3 +658,4 @@ int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev, return ret; } EXPORT_SYMBOL_GPL(mcp23s08_probe_one); +MODULE_LICENSE("GPL"); From 3dbf1ee6abbb30d21db0649b93a34576da64ab00 Mon Sep 17 00:00:00 2001 From: Grace Kao Date: Fri, 17 Apr 2020 12:11:54 +0800 Subject: [PATCH 29/72] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler According to Braswell NDA Specification Update (#557593), concurrent read accesses may result in returning 0xffffffff and write instructions may be dropped. We have an established format for the commit references, i.e. cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler") Fixes: 0bd50d719b00 ("pinctrl: cherryview: prevent concurrent access to GPIO controllers") Signed-off-by: Grace Kao Reported-by: Brian Norris Reviewed-by: Brian Norris Acked-by: Mika Westerberg Signed-off-by: Andy Shevchenko --- drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 53f2775f7184..8e3953a223d0 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -1411,11 +1411,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) struct chv_pinctrl *pctrl = gpiochip_get_data(gc); struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; + unsigned long flags; u32 intr_line; chained_irq_enter(chip, desc); + raw_spin_lock_irqsave(&chv_lock, flags); pending = readl(pctrl->regs + CHV_INTSTAT); + raw_spin_unlock_irqrestore(&chv_lock, flags); + for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) { unsigned int irq, offset; From 4b4e8e93eccc2abc4209fe226ec89e7fbe9f3c61 Mon Sep 17 00:00:00 2001 From: Jason Yan Date: Fri, 17 Apr 2020 19:16:04 +0800 Subject: [PATCH 30/72] pinctrl: rza1: Fix wrong array assignment of rza1l_swio_entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The rza1l_swio_entries referred to the wrong array rza1h_swio_pins, which was intended to be rza1l_swio_pins. So let's fix it. This is detected by the following gcc warning: drivers/pinctrl/pinctrl-rza1.c:401:35: warning: ‘rza1l_swio_pins’ defined but not used [-Wunused-const-variable=] static const struct rza1_swio_pin rza1l_swio_pins[] = { ^~~~~~~~~~~~~~~ Fixes: 039bc58e73b77723 ("pinctrl: rza1: Add support for RZ/A1L") Reported-by: Hulk Robot Signed-off-by: Jason Yan Link: https://lore.kernel.org/r/20200417111604.19143-1-yanaijie@huawei.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/pinctrl-rza1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index da2d8365c690..ff4a7fb518bb 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -418,7 +418,7 @@ static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = { }; static const struct rza1_swio_entry rza1l_swio_entries[] = { - [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins }, + [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins }, }; /* RZ/A1L (r7s72102x) pinmux flags table */ From 41fe32ecc7aff4527a4ee477870d9b1164be95a4 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 17 Apr 2020 16:10:03 +0200 Subject: [PATCH 31/72] MAINTAINERS: Add DT Bindings for Renesas Pin Function Controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "PIN CONTROLLER - RENESAS" section lacks the related DT bindings. Add them. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/20200417141003.22816-1-geert+renesas@glider.be --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index e64e5db31497..edeb025d9187 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13346,6 +13346,7 @@ M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc +F: Documentation/devicetree/bindings/pinctrl/renesas,* F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ From 2ccb9cc3b4d8653603c302083848e7d44bc89b58 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 21 Apr 2020 22:00:48 +0300 Subject: [PATCH 32/72] pinctrl: intel: Update description in struct intel_community It appears that most of the drivers, that are using struct intel_community, utilize gpps rather than gpp_size. Update comment accordingly. While here, correct the description of gpp_size, i.e. remove double space and drop redundant 'etc.' part. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 87fc0555ef90..934612e81cc3 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -95,7 +95,7 @@ enum { * @features: Additional features supported by the hardware * @pin_base: Starting pin of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, - * HOSTSW_OWN, GPI_IS, GPI_IE, etc. Used when @gpps is %NULL. + * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at * minimum. Use %0 if the number of registers can be * determined by the size of the group. @@ -106,8 +106,8 @@ enum { * @regs: Community specific common registers (reserved for core driver) * @pad_regs: Community specific pad registers (reserved for core driver) * - * Most Intel GPIO host controllers this driver supports each pad group is - * of equal size (except the last one). In that case the driver can just + * In some of Intel GPIO host controllers this driver supports each pad group + * is of equal size (except the last one). In that case the driver can just * fill in @gpp_size field and let the core driver to handle the rest. If * the controller has pad groups of variable size the client driver can * pass custom @gpps and @ngpps instead. From 6d649fca349155698ba4b8858b258a62003c5c54 Mon Sep 17 00:00:00 2001 From: Andy Shevchenko Date: Tue, 21 Apr 2020 22:00:49 +0300 Subject: [PATCH 33/72] pinctrl: intel: Move npins closer to pin_base in struct intel_community It's common across the drivers to use the (pin_base, npins) pair to describe community characteristics. Thus, move them in the struct intel_community to be closer to each other. While at it, add a blank line to cut driver usable fields from what core reserves for itself. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-intel.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h index 934612e81cc3..cc78c483518f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.h +++ b/drivers/pinctrl/intel/pinctrl-intel.h @@ -94,12 +94,12 @@ enum { * @ie_offset: Register offset of GPI_IE from @regs. * @features: Additional features supported by the hardware * @pin_base: Starting pin of pins in this community + * @npins: Number of pins in this community * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK, * HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL. * @gpp_num_padown_regs: Number of pad registers each pad group consumes at * minimum. Use %0 if the number of registers can be * determined by the size of the group. - * @npins: Number of pins in this community * @gpps: Pad groups if the controller has variable size pad groups * @ngpps: Number of pad groups in this community * @pad_map: Optional non-linear mapping of the pads @@ -121,12 +121,13 @@ struct intel_community { unsigned int ie_offset; unsigned int features; unsigned int pin_base; + size_t npins; unsigned int gpp_size; unsigned int gpp_num_padown_regs; - size_t npins; const struct intel_padgroup *gpps; size_t ngpps; const unsigned int *pad_map; + /* Reserved for the core driver */ void __iomem *regs; void __iomem *pad_regs; From 548e33205964d3a471a5aca259aee6685becfed8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Thu, 16 Apr 2020 23:19:06 -0700 Subject: [PATCH 34/72] dt-bindings: pinctrl: qcom: Add sm8250 pinctrl bindings Add device tree binding Documentation details for Qualcomm SM8250 pinctrl driver. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200417061907.1226490-2-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij --- .../bindings/pinctrl/qcom,sm8250-pinctrl.yaml | 147 ++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml new file mode 100644 index 000000000000..6dc3b52f47cd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm8250-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SM8250 TLMM block + +maintainers: + - Bjorn Andersson + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SM8250 platform. + +properties: + compatible: + const: qcom,sm8250-pinctrl + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: "west" + - const: "south" + - const: "north" + + interrupts: + description: Specifies the TLMM summary IRQ + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + description: + Specifies the PIN numbers and Flags, as defined in defined in + include/dt-bindings/interrupt-controller/irq.h + const: 2 + + gpio-controller: true + + '#gpio-cells': + description: Specifying the pin number and flags, as defined in + include/dt-bindings/gpio/gpio.h + const: 2 + + gpio-ranges: + maxItems: 1 + + wakeup-parent: + maxItems: 1 + +#PIN CONFIGURATION NODES +patternProperties: + '^.*$': + if: + type: object + then: + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$" + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c, + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1, + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio, + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0, + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1, + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset, + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3, + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14, + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6, + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41, + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1, + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data, + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en, + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ] + + drive-strength: + enum: [2, 4, 6, 8, 10, 12, 14, 16] + default: 2 + description: + Selects the drive strength for the specified pins, in mA. + + bias-pull-down: true + + bias-pull-up: true + + bias-disable: true + + output-high: true + + output-low: true + + required: + - pins + - function + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-controller + - '#interrupt-cells' + - gpio-controller + - '#gpio-cells' + - gpio-ranges + +additionalProperties: false + +examples: + - | + #include + pinctrl@1f00000 { + compatible = "qcom,sm8250-pinctrl"; + reg = <0x0f100000 0x300000>, + <0x0f500000 0x300000>, + <0x0f900000 0x300000>; + reg-names = "west", "south", "north"; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 180>; + wakeup-parent = <&pdc>; + }; From 4e3ec9e407ad5058003309072b37111f7b8c900a Mon Sep 17 00:00:00 2001 From: Venkata Narendra Kumar Gutta Date: Thu, 16 Apr 2020 23:19:07 -0700 Subject: [PATCH 35/72] pinctrl: qcom: Add sm8250 pinctrl driver. Add initial Qualcomm SM8250 pinctrl driver to support pin configuration with pinctrl framework for SM8250 SoC. Signed-off-by: Rishabh Bhatnagar Signed-off-by: Venkata Narendra Kumar Gutta Link: https://lore.kernel.org/r/1586477057-7636-2-git-send-email-vnkgutta@codeaurora.org [bjorn: Regrouped functions, upstream tiles implementation, dropped downstream-only features] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200417061907.1226490-3-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij --- drivers/pinctrl/qcom/Kconfig | 9 + drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sm8250.c | 1361 +++++++++++++++++++++++++ 3 files changed, 1371 insertions(+) create mode 100644 drivers/pinctrl/qcom/pinctrl-sm8250.c diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index c5d4428f1f94..ff1ee159dca2 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -216,4 +216,13 @@ config PINCTRL_SM8150 Qualcomm Technologies Inc TLMM block found on the Qualcomm Technologies Inc SM8150 platform. +config PINCTRL_SM8250 + tristate "Qualcomm Technologies Inc SM8250 pin controller driver" + depends on GPIOLIB && OF + select PINCTRL_MSM + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc TLMM block found on the Qualcomm + Technologies Inc SM8250 platform. + endif diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index d9e09045a776..061ec9fb659b 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -26,3 +26,4 @@ obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o +obj-$(CONFIG_PINCTRL_SM8250) += pinctrl-sm8250.o diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250.c b/drivers/pinctrl/qcom/pinctrl-sm8250.c new file mode 100644 index 000000000000..a660f1274b66 --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sm8250.c @@ -0,0 +1,1361 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include + +#include "pinctrl-msm.h" + +static const char * const sm8250_tiles[] = { + "west", + "south", + "north", +}; + +enum { + WEST, + SOUTH, + NORTH, +}; + +#define FUNCTION(fname) \ + [msm_mux_##fname] = { \ + .name = #fname, \ + .groups = fname##_groups, \ + .ngroups = ARRAY_SIZE(fname##_groups), \ + } + +#define REG_SIZE 0x1000 +#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ + { \ + .name = "gpio" #id, \ + .pins = gpio##id##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ + .funcs = (int[]){ \ + msm_mux_gpio, /* gpio mode */ \ + msm_mux_##f1, \ + msm_mux_##f2, \ + msm_mux_##f3, \ + msm_mux_##f4, \ + msm_mux_##f5, \ + msm_mux_##f6, \ + msm_mux_##f7, \ + msm_mux_##f8, \ + msm_mux_##f9 \ + }, \ + .nfuncs = 10, \ + .ctl_reg = REG_SIZE * id, \ + .io_reg = REG_SIZE * id + 0x4, \ + .intr_cfg_reg = REG_SIZE * id + 0x8, \ + .intr_status_reg = REG_SIZE * id + 0xc, \ + .intr_target_reg = REG_SIZE * id + 0x8, \ + .tile = _tile, \ + .mux_bit = 2, \ + .pull_bit = 0, \ + .drv_bit = 6, \ + .oe_bit = 9, \ + .in_bit = 0, \ + .out_bit = 1, \ + .intr_enable_bit = 0, \ + .intr_status_bit = 0, \ + .intr_target_bit = 5, \ + .intr_target_kpss_val = 3, \ + .intr_raw_status_bit = 4, \ + .intr_polarity_bit = 1, \ + .intr_detection_bit = 2, \ + .intr_detection_width = 2, \ + } + +#define SDC_PINGROUP(pg_name, ctl, pull, drv) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = ctl, \ + .io_reg = 0, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = NORTH, \ + .mux_bit = -1, \ + .pull_bit = pull, \ + .drv_bit = drv, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = -1, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +#define UFS_RESET(pg_name, offset) \ + { \ + .name = #pg_name, \ + .pins = pg_name##_pins, \ + .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \ + .ctl_reg = offset, \ + .io_reg = offset + 0x4, \ + .intr_cfg_reg = 0, \ + .intr_status_reg = 0, \ + .intr_target_reg = 0, \ + .tile = SOUTH, \ + .mux_bit = -1, \ + .pull_bit = 3, \ + .drv_bit = 0, \ + .oe_bit = -1, \ + .in_bit = -1, \ + .out_bit = 0, \ + .intr_enable_bit = -1, \ + .intr_status_bit = -1, \ + .intr_target_bit = -1, \ + .intr_raw_status_bit = -1, \ + .intr_polarity_bit = -1, \ + .intr_detection_bit = -1, \ + .intr_detection_width = -1, \ + } + +static const struct pinctrl_pin_desc sm8250_pins[] = { + PINCTRL_PIN(0, "GPIO_0"), + PINCTRL_PIN(1, "GPIO_1"), + PINCTRL_PIN(2, "GPIO_2"), + PINCTRL_PIN(3, "GPIO_3"), + PINCTRL_PIN(4, "GPIO_4"), + PINCTRL_PIN(5, "GPIO_5"), + PINCTRL_PIN(6, "GPIO_6"), + PINCTRL_PIN(7, "GPIO_7"), + PINCTRL_PIN(8, "GPIO_8"), + PINCTRL_PIN(9, "GPIO_9"), + PINCTRL_PIN(10, "GPIO_10"), + PINCTRL_PIN(11, "GPIO_11"), + PINCTRL_PIN(12, "GPIO_12"), + PINCTRL_PIN(13, "GPIO_13"), + PINCTRL_PIN(14, "GPIO_14"), + PINCTRL_PIN(15, "GPIO_15"), + PINCTRL_PIN(16, "GPIO_16"), + PINCTRL_PIN(17, "GPIO_17"), + PINCTRL_PIN(18, "GPIO_18"), + PINCTRL_PIN(19, "GPIO_19"), + PINCTRL_PIN(20, "GPIO_20"), + PINCTRL_PIN(21, "GPIO_21"), + PINCTRL_PIN(22, "GPIO_22"), + PINCTRL_PIN(23, "GPIO_23"), + PINCTRL_PIN(24, "GPIO_24"), + PINCTRL_PIN(25, "GPIO_25"), + PINCTRL_PIN(26, "GPIO_26"), + PINCTRL_PIN(27, "GPIO_27"), + PINCTRL_PIN(28, "GPIO_28"), + PINCTRL_PIN(29, "GPIO_29"), + PINCTRL_PIN(30, "GPIO_30"), + PINCTRL_PIN(31, "GPIO_31"), + PINCTRL_PIN(32, "GPIO_32"), + PINCTRL_PIN(33, "GPIO_33"), + PINCTRL_PIN(34, "GPIO_34"), + PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(36, "GPIO_36"), + PINCTRL_PIN(37, "GPIO_37"), + PINCTRL_PIN(38, "GPIO_38"), + PINCTRL_PIN(39, "GPIO_39"), + PINCTRL_PIN(40, "GPIO_40"), + PINCTRL_PIN(41, "GPIO_41"), + PINCTRL_PIN(42, "GPIO_42"), + PINCTRL_PIN(43, "GPIO_43"), + PINCTRL_PIN(44, "GPIO_44"), + PINCTRL_PIN(45, "GPIO_45"), + PINCTRL_PIN(46, "GPIO_46"), + PINCTRL_PIN(47, "GPIO_47"), + PINCTRL_PIN(48, "GPIO_48"), + PINCTRL_PIN(49, "GPIO_49"), + PINCTRL_PIN(50, "GPIO_50"), + PINCTRL_PIN(51, "GPIO_51"), + PINCTRL_PIN(52, "GPIO_52"), + PINCTRL_PIN(53, "GPIO_53"), + PINCTRL_PIN(54, "GPIO_54"), + PINCTRL_PIN(55, "GPIO_55"), + PINCTRL_PIN(56, "GPIO_56"), + PINCTRL_PIN(57, "GPIO_57"), + PINCTRL_PIN(58, "GPIO_58"), + PINCTRL_PIN(59, "GPIO_59"), + PINCTRL_PIN(60, "GPIO_60"), + PINCTRL_PIN(61, "GPIO_61"), + PINCTRL_PIN(62, "GPIO_62"), + PINCTRL_PIN(63, "GPIO_63"), + PINCTRL_PIN(64, "GPIO_64"), + PINCTRL_PIN(65, "GPIO_65"), + PINCTRL_PIN(66, "GPIO_66"), + PINCTRL_PIN(67, "GPIO_67"), + PINCTRL_PIN(68, "GPIO_68"), + PINCTRL_PIN(69, "GPIO_69"), + PINCTRL_PIN(70, "GPIO_70"), + PINCTRL_PIN(71, "GPIO_71"), + PINCTRL_PIN(72, "GPIO_72"), + PINCTRL_PIN(73, "GPIO_73"), + PINCTRL_PIN(74, "GPIO_74"), + PINCTRL_PIN(75, "GPIO_75"), + PINCTRL_PIN(76, "GPIO_76"), + PINCTRL_PIN(77, "GPIO_77"), + PINCTRL_PIN(78, "GPIO_78"), + PINCTRL_PIN(79, "GPIO_79"), + PINCTRL_PIN(80, "GPIO_80"), + PINCTRL_PIN(81, "GPIO_81"), + PINCTRL_PIN(82, "GPIO_82"), + PINCTRL_PIN(83, "GPIO_83"), + PINCTRL_PIN(84, "GPIO_84"), + PINCTRL_PIN(85, "GPIO_85"), + PINCTRL_PIN(86, "GPIO_86"), + PINCTRL_PIN(87, "GPIO_87"), + PINCTRL_PIN(88, "GPIO_88"), + PINCTRL_PIN(89, "GPIO_89"), + PINCTRL_PIN(90, "GPIO_90"), + PINCTRL_PIN(91, "GPIO_91"), + PINCTRL_PIN(92, "GPIO_92"), + PINCTRL_PIN(93, "GPIO_93"), + PINCTRL_PIN(94, "GPIO_94"), + PINCTRL_PIN(95, "GPIO_95"), + PINCTRL_PIN(96, "GPIO_96"), + PINCTRL_PIN(97, "GPIO_97"), + PINCTRL_PIN(98, "GPIO_98"), + PINCTRL_PIN(99, "GPIO_99"), + PINCTRL_PIN(100, "GPIO_100"), + PINCTRL_PIN(101, "GPIO_101"), + PINCTRL_PIN(102, "GPIO_102"), + PINCTRL_PIN(103, "GPIO_103"), + PINCTRL_PIN(104, "GPIO_104"), + PINCTRL_PIN(105, "GPIO_105"), + PINCTRL_PIN(106, "GPIO_106"), + PINCTRL_PIN(107, "GPIO_107"), + PINCTRL_PIN(108, "GPIO_108"), + PINCTRL_PIN(109, "GPIO_109"), + PINCTRL_PIN(110, "GPIO_110"), + PINCTRL_PIN(111, "GPIO_111"), + PINCTRL_PIN(112, "GPIO_112"), + PINCTRL_PIN(113, "GPIO_113"), + PINCTRL_PIN(114, "GPIO_114"), + PINCTRL_PIN(115, "GPIO_115"), + PINCTRL_PIN(116, "GPIO_116"), + PINCTRL_PIN(117, "GPIO_117"), + PINCTRL_PIN(118, "GPIO_118"), + PINCTRL_PIN(119, "GPIO_119"), + PINCTRL_PIN(120, "GPIO_120"), + PINCTRL_PIN(121, "GPIO_121"), + PINCTRL_PIN(122, "GPIO_122"), + PINCTRL_PIN(123, "GPIO_123"), + PINCTRL_PIN(124, "GPIO_124"), + PINCTRL_PIN(125, "GPIO_125"), + PINCTRL_PIN(126, "GPIO_126"), + PINCTRL_PIN(127, "GPIO_127"), + PINCTRL_PIN(128, "GPIO_128"), + PINCTRL_PIN(129, "GPIO_129"), + PINCTRL_PIN(130, "GPIO_130"), + PINCTRL_PIN(131, "GPIO_131"), + PINCTRL_PIN(132, "GPIO_132"), + PINCTRL_PIN(133, "GPIO_133"), + PINCTRL_PIN(134, "GPIO_134"), + PINCTRL_PIN(135, "GPIO_135"), + PINCTRL_PIN(136, "GPIO_136"), + PINCTRL_PIN(137, "GPIO_137"), + PINCTRL_PIN(138, "GPIO_138"), + PINCTRL_PIN(139, "GPIO_139"), + PINCTRL_PIN(140, "GPIO_140"), + PINCTRL_PIN(141, "GPIO_141"), + PINCTRL_PIN(142, "GPIO_142"), + PINCTRL_PIN(143, "GPIO_143"), + PINCTRL_PIN(144, "GPIO_144"), + PINCTRL_PIN(145, "GPIO_145"), + PINCTRL_PIN(146, "GPIO_146"), + PINCTRL_PIN(147, "GPIO_147"), + PINCTRL_PIN(148, "GPIO_148"), + PINCTRL_PIN(149, "GPIO_149"), + PINCTRL_PIN(150, "GPIO_150"), + PINCTRL_PIN(151, "GPIO_151"), + PINCTRL_PIN(152, "GPIO_152"), + PINCTRL_PIN(153, "GPIO_153"), + PINCTRL_PIN(154, "GPIO_154"), + PINCTRL_PIN(155, "GPIO_155"), + PINCTRL_PIN(156, "GPIO_156"), + PINCTRL_PIN(157, "GPIO_157"), + PINCTRL_PIN(158, "GPIO_158"), + PINCTRL_PIN(159, "GPIO_159"), + PINCTRL_PIN(160, "GPIO_160"), + PINCTRL_PIN(161, "GPIO_161"), + PINCTRL_PIN(162, "GPIO_162"), + PINCTRL_PIN(163, "GPIO_163"), + PINCTRL_PIN(164, "GPIO_164"), + PINCTRL_PIN(165, "GPIO_165"), + PINCTRL_PIN(166, "GPIO_166"), + PINCTRL_PIN(167, "GPIO_167"), + PINCTRL_PIN(168, "GPIO_168"), + PINCTRL_PIN(169, "GPIO_169"), + PINCTRL_PIN(170, "GPIO_170"), + PINCTRL_PIN(171, "GPIO_171"), + PINCTRL_PIN(172, "GPIO_172"), + PINCTRL_PIN(173, "GPIO_173"), + PINCTRL_PIN(174, "GPIO_174"), + PINCTRL_PIN(175, "GPIO_175"), + PINCTRL_PIN(176, "GPIO_176"), + PINCTRL_PIN(177, "GPIO_177"), + PINCTRL_PIN(178, "GPIO_178"), + PINCTRL_PIN(179, "GPIO_179"), + PINCTRL_PIN(180, "SDC2_CLK"), + PINCTRL_PIN(181, "SDC2_CMD"), + PINCTRL_PIN(182, "SDC2_DATA"), + PINCTRL_PIN(183, "UFS_RESET"), +}; + +#define DECLARE_MSM_GPIO_PINS(pin) \ + static const unsigned int gpio##pin##_pins[] = { pin } +DECLARE_MSM_GPIO_PINS(0); +DECLARE_MSM_GPIO_PINS(1); +DECLARE_MSM_GPIO_PINS(2); +DECLARE_MSM_GPIO_PINS(3); +DECLARE_MSM_GPIO_PINS(4); +DECLARE_MSM_GPIO_PINS(5); +DECLARE_MSM_GPIO_PINS(6); +DECLARE_MSM_GPIO_PINS(7); +DECLARE_MSM_GPIO_PINS(8); +DECLARE_MSM_GPIO_PINS(9); +DECLARE_MSM_GPIO_PINS(10); +DECLARE_MSM_GPIO_PINS(11); +DECLARE_MSM_GPIO_PINS(12); +DECLARE_MSM_GPIO_PINS(13); +DECLARE_MSM_GPIO_PINS(14); +DECLARE_MSM_GPIO_PINS(15); +DECLARE_MSM_GPIO_PINS(16); +DECLARE_MSM_GPIO_PINS(17); +DECLARE_MSM_GPIO_PINS(18); +DECLARE_MSM_GPIO_PINS(19); +DECLARE_MSM_GPIO_PINS(20); +DECLARE_MSM_GPIO_PINS(21); +DECLARE_MSM_GPIO_PINS(22); +DECLARE_MSM_GPIO_PINS(23); +DECLARE_MSM_GPIO_PINS(24); +DECLARE_MSM_GPIO_PINS(25); +DECLARE_MSM_GPIO_PINS(26); +DECLARE_MSM_GPIO_PINS(27); +DECLARE_MSM_GPIO_PINS(28); +DECLARE_MSM_GPIO_PINS(29); +DECLARE_MSM_GPIO_PINS(30); +DECLARE_MSM_GPIO_PINS(31); +DECLARE_MSM_GPIO_PINS(32); +DECLARE_MSM_GPIO_PINS(33); +DECLARE_MSM_GPIO_PINS(34); +DECLARE_MSM_GPIO_PINS(35); +DECLARE_MSM_GPIO_PINS(36); +DECLARE_MSM_GPIO_PINS(37); +DECLARE_MSM_GPIO_PINS(38); +DECLARE_MSM_GPIO_PINS(39); +DECLARE_MSM_GPIO_PINS(40); +DECLARE_MSM_GPIO_PINS(41); +DECLARE_MSM_GPIO_PINS(42); +DECLARE_MSM_GPIO_PINS(43); +DECLARE_MSM_GPIO_PINS(44); +DECLARE_MSM_GPIO_PINS(45); +DECLARE_MSM_GPIO_PINS(46); +DECLARE_MSM_GPIO_PINS(47); +DECLARE_MSM_GPIO_PINS(48); +DECLARE_MSM_GPIO_PINS(49); +DECLARE_MSM_GPIO_PINS(50); +DECLARE_MSM_GPIO_PINS(51); +DECLARE_MSM_GPIO_PINS(52); +DECLARE_MSM_GPIO_PINS(53); +DECLARE_MSM_GPIO_PINS(54); +DECLARE_MSM_GPIO_PINS(55); +DECLARE_MSM_GPIO_PINS(56); +DECLARE_MSM_GPIO_PINS(57); +DECLARE_MSM_GPIO_PINS(58); +DECLARE_MSM_GPIO_PINS(59); +DECLARE_MSM_GPIO_PINS(60); +DECLARE_MSM_GPIO_PINS(61); +DECLARE_MSM_GPIO_PINS(62); +DECLARE_MSM_GPIO_PINS(63); +DECLARE_MSM_GPIO_PINS(64); +DECLARE_MSM_GPIO_PINS(65); +DECLARE_MSM_GPIO_PINS(66); +DECLARE_MSM_GPIO_PINS(67); +DECLARE_MSM_GPIO_PINS(68); +DECLARE_MSM_GPIO_PINS(69); +DECLARE_MSM_GPIO_PINS(70); +DECLARE_MSM_GPIO_PINS(71); +DECLARE_MSM_GPIO_PINS(72); +DECLARE_MSM_GPIO_PINS(73); +DECLARE_MSM_GPIO_PINS(74); +DECLARE_MSM_GPIO_PINS(75); +DECLARE_MSM_GPIO_PINS(76); +DECLARE_MSM_GPIO_PINS(77); +DECLARE_MSM_GPIO_PINS(78); +DECLARE_MSM_GPIO_PINS(79); +DECLARE_MSM_GPIO_PINS(80); +DECLARE_MSM_GPIO_PINS(81); +DECLARE_MSM_GPIO_PINS(82); +DECLARE_MSM_GPIO_PINS(83); +DECLARE_MSM_GPIO_PINS(84); +DECLARE_MSM_GPIO_PINS(85); +DECLARE_MSM_GPIO_PINS(86); +DECLARE_MSM_GPIO_PINS(87); +DECLARE_MSM_GPIO_PINS(88); +DECLARE_MSM_GPIO_PINS(89); +DECLARE_MSM_GPIO_PINS(90); +DECLARE_MSM_GPIO_PINS(91); +DECLARE_MSM_GPIO_PINS(92); +DECLARE_MSM_GPIO_PINS(93); +DECLARE_MSM_GPIO_PINS(94); +DECLARE_MSM_GPIO_PINS(95); +DECLARE_MSM_GPIO_PINS(96); +DECLARE_MSM_GPIO_PINS(97); +DECLARE_MSM_GPIO_PINS(98); +DECLARE_MSM_GPIO_PINS(99); +DECLARE_MSM_GPIO_PINS(100); +DECLARE_MSM_GPIO_PINS(101); +DECLARE_MSM_GPIO_PINS(102); +DECLARE_MSM_GPIO_PINS(103); +DECLARE_MSM_GPIO_PINS(104); +DECLARE_MSM_GPIO_PINS(105); +DECLARE_MSM_GPIO_PINS(106); +DECLARE_MSM_GPIO_PINS(107); +DECLARE_MSM_GPIO_PINS(108); +DECLARE_MSM_GPIO_PINS(109); +DECLARE_MSM_GPIO_PINS(110); +DECLARE_MSM_GPIO_PINS(111); +DECLARE_MSM_GPIO_PINS(112); +DECLARE_MSM_GPIO_PINS(113); +DECLARE_MSM_GPIO_PINS(114); +DECLARE_MSM_GPIO_PINS(115); +DECLARE_MSM_GPIO_PINS(116); +DECLARE_MSM_GPIO_PINS(117); +DECLARE_MSM_GPIO_PINS(118); +DECLARE_MSM_GPIO_PINS(119); +DECLARE_MSM_GPIO_PINS(120); +DECLARE_MSM_GPIO_PINS(121); +DECLARE_MSM_GPIO_PINS(122); +DECLARE_MSM_GPIO_PINS(123); +DECLARE_MSM_GPIO_PINS(124); +DECLARE_MSM_GPIO_PINS(125); +DECLARE_MSM_GPIO_PINS(126); +DECLARE_MSM_GPIO_PINS(127); +DECLARE_MSM_GPIO_PINS(128); +DECLARE_MSM_GPIO_PINS(129); +DECLARE_MSM_GPIO_PINS(130); +DECLARE_MSM_GPIO_PINS(131); +DECLARE_MSM_GPIO_PINS(132); +DECLARE_MSM_GPIO_PINS(133); +DECLARE_MSM_GPIO_PINS(134); +DECLARE_MSM_GPIO_PINS(135); +DECLARE_MSM_GPIO_PINS(136); +DECLARE_MSM_GPIO_PINS(137); +DECLARE_MSM_GPIO_PINS(138); +DECLARE_MSM_GPIO_PINS(139); +DECLARE_MSM_GPIO_PINS(140); +DECLARE_MSM_GPIO_PINS(141); +DECLARE_MSM_GPIO_PINS(142); +DECLARE_MSM_GPIO_PINS(143); +DECLARE_MSM_GPIO_PINS(144); +DECLARE_MSM_GPIO_PINS(145); +DECLARE_MSM_GPIO_PINS(146); +DECLARE_MSM_GPIO_PINS(147); +DECLARE_MSM_GPIO_PINS(148); +DECLARE_MSM_GPIO_PINS(149); +DECLARE_MSM_GPIO_PINS(150); +DECLARE_MSM_GPIO_PINS(151); +DECLARE_MSM_GPIO_PINS(152); +DECLARE_MSM_GPIO_PINS(153); +DECLARE_MSM_GPIO_PINS(154); +DECLARE_MSM_GPIO_PINS(155); +DECLARE_MSM_GPIO_PINS(156); +DECLARE_MSM_GPIO_PINS(157); +DECLARE_MSM_GPIO_PINS(158); +DECLARE_MSM_GPIO_PINS(159); +DECLARE_MSM_GPIO_PINS(160); +DECLARE_MSM_GPIO_PINS(161); +DECLARE_MSM_GPIO_PINS(162); +DECLARE_MSM_GPIO_PINS(163); +DECLARE_MSM_GPIO_PINS(164); +DECLARE_MSM_GPIO_PINS(165); +DECLARE_MSM_GPIO_PINS(166); +DECLARE_MSM_GPIO_PINS(167); +DECLARE_MSM_GPIO_PINS(168); +DECLARE_MSM_GPIO_PINS(169); +DECLARE_MSM_GPIO_PINS(170); +DECLARE_MSM_GPIO_PINS(171); +DECLARE_MSM_GPIO_PINS(172); +DECLARE_MSM_GPIO_PINS(173); +DECLARE_MSM_GPIO_PINS(174); +DECLARE_MSM_GPIO_PINS(175); +DECLARE_MSM_GPIO_PINS(176); +DECLARE_MSM_GPIO_PINS(177); +DECLARE_MSM_GPIO_PINS(178); +DECLARE_MSM_GPIO_PINS(179); + +static const unsigned int ufs_reset_pins[] = { 180 }; +static const unsigned int sdc2_clk_pins[] = { 181 }; +static const unsigned int sdc2_cmd_pins[] = { 182 }; +static const unsigned int sdc2_data_pins[] = { 183 }; + +enum sm8250_functions { + msm_mux_aoss_cti, + msm_mux_atest, + msm_mux_audio_ref, + msm_mux_cam_mclk, + msm_mux_cci_async, + msm_mux_cci_i2c, + msm_mux_cci_timer0, + msm_mux_cci_timer1, + msm_mux_cci_timer2, + msm_mux_cci_timer3, + msm_mux_cci_timer4, + msm_mux_cri_trng, + msm_mux_cri_trng0, + msm_mux_cri_trng1, + msm_mux_dbg_out, + msm_mux_ddr_bist, + msm_mux_ddr_pxi0, + msm_mux_ddr_pxi1, + msm_mux_ddr_pxi2, + msm_mux_ddr_pxi3, + msm_mux_dp_hot, + msm_mux_dp_lcd, + msm_mux_gcc_gp1, + msm_mux_gcc_gp2, + msm_mux_gcc_gp3, + msm_mux_gpio, + msm_mux_ibi_i3c, + msm_mux_jitter_bist, + msm_mux_lpass_slimbus, + msm_mux_mdp_vsync, + msm_mux_mdp_vsync0, + msm_mux_mdp_vsync1, + msm_mux_mdp_vsync2, + msm_mux_mdp_vsync3, + msm_mux_mi2s0_data0, + msm_mux_mi2s0_data1, + msm_mux_mi2s0_sck, + msm_mux_mi2s0_ws, + msm_mux_mi2s1_data0, + msm_mux_mi2s1_data1, + msm_mux_mi2s1_sck, + msm_mux_mi2s1_ws, + msm_mux_mi2s2_data0, + msm_mux_mi2s2_data1, + msm_mux_mi2s2_sck, + msm_mux_mi2s2_ws, + msm_mux_pci_e0, + msm_mux_pci_e1, + msm_mux_pci_e2, + msm_mux_phase_flag, + msm_mux_pll_bist, + msm_mux_pll_bypassnl, + msm_mux_pll_clk, + msm_mux_pll_reset, + msm_mux_pri_mi2s, + msm_mux_prng_rosc, + msm_mux_qdss_cti, + msm_mux_qdss_gpio, + msm_mux_qspi0, + msm_mux_qspi1, + msm_mux_qspi2, + msm_mux_qspi3, + msm_mux_qspi_clk, + msm_mux_qspi_cs, + msm_mux_qup0, + msm_mux_qup1, + msm_mux_qup10, + msm_mux_qup11, + msm_mux_qup12, + msm_mux_qup13, + msm_mux_qup14, + msm_mux_qup15, + msm_mux_qup16, + msm_mux_qup17, + msm_mux_qup18, + msm_mux_qup19, + msm_mux_qup2, + msm_mux_qup3, + msm_mux_qup4, + msm_mux_qup5, + msm_mux_qup6, + msm_mux_qup7, + msm_mux_qup8, + msm_mux_qup9, + msm_mux_qup_l4, + msm_mux_qup_l5, + msm_mux_qup_l6, + msm_mux_sd_write, + msm_mux_sdc40, + msm_mux_sdc41, + msm_mux_sdc42, + msm_mux_sdc43, + msm_mux_sdc4_clk, + msm_mux_sdc4_cmd, + msm_mux_sec_mi2s, + msm_mux_sp_cmu, + msm_mux_tgu_ch0, + msm_mux_tgu_ch1, + msm_mux_tgu_ch2, + msm_mux_tgu_ch3, + msm_mux_tsense_pwm1, + msm_mux_tsense_pwm2, + msm_mux_tsif0_clk, + msm_mux_tsif0_data, + msm_mux_tsif0_en, + msm_mux_tsif0_error, + msm_mux_tsif0_sync, + msm_mux_tsif1_clk, + msm_mux_tsif1_data, + msm_mux_tsif1_en, + msm_mux_tsif1_error, + msm_mux_tsif1_sync, + msm_mux_usb2phy_ac, + msm_mux_usb_phy, + msm_mux_vsense_trigger, + msm_mux__, +}; + +static const char * const tsif1_data_groups[] = { + "gpio75", +}; +static const char * const sdc41_groups[] = { + "gpio75", +}; +static const char * const tsif1_sync_groups[] = { + "gpio76", +}; +static const char * const sdc40_groups[] = { + "gpio76", +}; +static const char * const aoss_cti_groups[] = { + "gpio77", +}; +static const char * const phase_flag_groups[] = { + "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51", + "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118", + "gpio119", "gpio120", "gpio122", "gpio124", "gpio125", +}; +static const char * const sd_write_groups[] = { + "gpio78", +}; +static const char * const pci_e0_groups[] = { + "gpio79", "gpio80", +}; +static const char * const pci_e1_groups[] = { + "gpio82", "gpio83", +}; +static const char * const pci_e2_groups[] = { + "gpio85", "gpio86", +}; +static const char * const tgu_ch0_groups[] = { + "gpio85", +}; +static const char * const atest_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34", + "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88", + "gpio89", +}; +static const char * const tgu_ch3_groups[] = { + "gpio86", +}; +static const char * const tsif1_error_groups[] = { + "gpio90", +}; +static const char * const tgu_ch1_groups[] = { + "gpio90", +}; +static const char * const tsif0_error_groups[] = { + "gpio91", +}; +static const char * const tgu_ch2_groups[] = { + "gpio91", +}; +static const char * const cam_mclk_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", +}; +static const char * const ddr_bist_groups[] = { + "gpio94", "gpio95", "gpio143", "gpio144", +}; +static const char * const pll_bypassnl_groups[] = { + "gpio96", +}; +static const char * const pll_reset_groups[] = { + "gpio97", +}; +static const char * const cci_i2c_groups[] = { + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", +}; +static const char * const qdss_gpio_groups[] = { + "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100", + "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106", + "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160", + "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166", + "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172", + "gpio173", "gpio174", "gpio175", "gpio176", "gpio177", +}; +static const char * const gcc_gp1_groups[] = { + "gpio106", "gpio136", +}; +static const char * const gcc_gp2_groups[] = { + "gpio107", "gpio137", +}; +static const char * const gcc_gp3_groups[] = { + "gpio108", "gpio138", +}; +static const char * const cci_timer0_groups[] = { + "gpio109", +}; +static const char * const cci_timer1_groups[] = { + "gpio110", +}; +static const char * const cci_timer2_groups[] = { + "gpio111", +}; +static const char * const cci_timer3_groups[] = { + "gpio112", +}; +static const char * const cci_async_groups[] = { + "gpio112", "gpio113", "gpio114", +}; +static const char * const cci_timer4_groups[] = { + "gpio113", +}; +static const char * const qup2_groups[] = { + "gpio115", "gpio116", "gpio117", "gpio118", +}; +static const char * const qup3_groups[] = { + "gpio119", "gpio120", "gpio121", "gpio122", +}; +static const char * const tsense_pwm1_groups[] = { + "gpio123", +}; +static const char * const tsense_pwm2_groups[] = { + "gpio123", +}; +static const char * const qup9_groups[] = { + "gpio125", "gpio126", "gpio127", "gpio128", +}; +static const char * const qup10_groups[] = { + "gpio129", "gpio130", "gpio131", "gpio132", +}; +static const char * const mi2s2_sck_groups[] = { + "gpio133", +}; +static const char * const mi2s2_data0_groups[] = { + "gpio134", +}; +static const char * const mi2s2_ws_groups[] = { + "gpio135", +}; +static const char * const pri_mi2s_groups[] = { + "gpio136", +}; +static const char * const sec_mi2s_groups[] = { + "gpio137", +}; +static const char * const audio_ref_groups[] = { + "gpio137", +}; +static const char * const mi2s2_data1_groups[] = { + "gpio137", +}; +static const char * const mi2s0_sck_groups[] = { + "gpio138", +}; +static const char * const mi2s0_data0_groups[] = { + "gpio139", +}; +static const char * const mi2s0_data1_groups[] = { + "gpio140", +}; +static const char * const mi2s0_ws_groups[] = { + "gpio141", +}; +static const char * const lpass_slimbus_groups[] = { + "gpio142", "gpio143", "gpio144", "gpio145", +}; +static const char * const mi2s1_sck_groups[] = { + "gpio142", +}; +static const char * const mi2s1_data0_groups[] = { + "gpio143", +}; +static const char * const mi2s1_data1_groups[] = { + "gpio144", +}; +static const char * const mi2s1_ws_groups[] = { + "gpio145", +}; +static const char * const cri_trng0_groups[] = { + "gpio159", +}; +static const char * const cri_trng1_groups[] = { + "gpio160", +}; +static const char * const cri_trng_groups[] = { + "gpio161", +}; +static const char * const sp_cmu_groups[] = { + "gpio162", +}; +static const char * const prng_rosc_groups[] = { + "gpio163", +}; +static const char * const qup19_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", +}; +static const char * const gpio_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", + "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", + "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", + "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", + "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", + "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", + "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", + "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56", + "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", + "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70", + "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77", + "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84", + "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91", + "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", + "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104", + "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110", + "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116", + "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122", + "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128", + "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134", + "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", + "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146", + "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152", + "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158", + "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164", + "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170", + "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176", + "gpio177", "gpio178", "gpio179", +}; +static const char * const qdss_cti_groups[] = { + "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92", + "gpio93", +}; +static const char * const qup1_groups[] = { + "gpio4", "gpio5", "gpio6", "gpio7", +}; +static const char * const ibi_i3c_groups[] = { + "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40", + "gpio41", +}; +static const char * const qup_l4_groups[] = { + "gpio6", "gpio14", "gpio46", "gpio123", +}; +static const char * const qup_l5_groups[] = { + "gpio7", "gpio15", "gpio47", "gpio124", +}; +static const char * const qup4_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11", +}; +static const char * const qup5_groups[] = { + "gpio12", "gpio13", "gpio14", "gpio15", +}; +static const char * const qup6_groups[] = { + "gpio16", "gpio17", "gpio18", "gpio19", +}; +static const char * const qup7_groups[] = { + "gpio20", "gpio21", "gpio22", "gpio23", +}; +static const char * const qup8_groups[] = { + "gpio24", "gpio25", "gpio26", "gpio27", +}; +static const char * const qup0_groups[] = { + "gpio28", "gpio29", "gpio30", "gpio31", +}; +static const char * const qup12_groups[] = { + "gpio32", "gpio33", "gpio34", "gpio35", +}; +static const char * const qup13_groups[] = { + "gpio36", "gpio37", "gpio38", "gpio39", +}; +static const char * const qup14_groups[] = { + "gpio40", "gpio41", "gpio42", "gpio43", +}; +static const char * const ddr_pxi3_groups[] = { + "gpio40", "gpio43", +}; +static const char * const ddr_pxi1_groups[] = { + "gpio41", "gpio42", +}; +static const char * const vsense_trigger_groups[] = { + "gpio42", +}; +static const char * const qup15_groups[] = { + "gpio44", "gpio45", "gpio46", "gpio47", +}; +static const char * const dbg_out_groups[] = { + "gpio44", +}; +static const char * const qup16_groups[] = { + "gpio48", "gpio49", "gpio50", "gpio51", +}; +static const char * const qup17_groups[] = { + "gpio52", "gpio53", "gpio54", "gpio55", +}; +static const char * const ddr_pxi0_groups[] = { + "gpio52", "gpio53", +}; +static const char * const jitter_bist_groups[] = { + "gpio54", +}; +static const char * const pll_bist_groups[] = { + "gpio55", +}; +static const char * const ddr_pxi2_groups[] = { + "gpio55", "gpio56", +}; +static const char * const qup18_groups[] = { + "gpio56", "gpio57", "gpio58", "gpio59", +}; +static const char * const qup11_groups[] = { + "gpio60", "gpio61", "gpio62", "gpio63", +}; +static const char * const usb2phy_ac_groups[] = { + "gpio64", "gpio90", +}; +static const char * const qup_l6_groups[] = { + "gpio64", "gpio77", "gpio92", "gpio93", +}; +static const char * const usb_phy_groups[] = { + "gpio65", +}; +static const char * const pll_clk_groups[] = { + "gpio65", +}; +static const char * const mdp_vsync_groups[] = { + "gpio66", "gpio67", "gpio68", "gpio122", "gpio124", +}; +static const char * const dp_lcd_groups[] = { + "gpio67", +}; +static const char * const dp_hot_groups[] = { + "gpio68", +}; +static const char * const qspi_cs_groups[] = { + "gpio69", "gpio75", +}; +static const char * const tsif0_clk_groups[] = { + "gpio69", +}; +static const char * const qspi0_groups[] = { + "gpio70", +}; +static const char * const tsif0_en_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync0_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync1_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync2_groups[] = { + "gpio70", +}; +static const char * const mdp_vsync3_groups[] = { + "gpio70", +}; +static const char * const qspi1_groups[] = { + "gpio71", +}; +static const char * const tsif0_data_groups[] = { + "gpio71", +}; +static const char * const sdc4_cmd_groups[] = { + "gpio71", +}; +static const char * const qspi2_groups[] = { + "gpio72", +}; +static const char * const tsif0_sync_groups[] = { + "gpio72", +}; +static const char * const sdc43_groups[] = { + "gpio72", +}; +static const char * const qspi_clk_groups[] = { + "gpio73", +}; +static const char * const tsif1_clk_groups[] = { + "gpio73", +}; +static const char * const sdc4_clk_groups[] = { + "gpio73", +}; +static const char * const qspi3_groups[] = { + "gpio74", +}; +static const char * const tsif1_en_groups[] = { + "gpio74", +}; +static const char * const sdc42_groups[] = { + "gpio74", +}; + +static const struct msm_function sm8250_functions[] = { + FUNCTION(aoss_cti), + FUNCTION(atest), + FUNCTION(audio_ref), + FUNCTION(cam_mclk), + FUNCTION(cci_async), + FUNCTION(cci_i2c), + FUNCTION(cci_timer0), + FUNCTION(cci_timer1), + FUNCTION(cci_timer2), + FUNCTION(cci_timer3), + FUNCTION(cci_timer4), + FUNCTION(cri_trng), + FUNCTION(cri_trng0), + FUNCTION(cri_trng1), + FUNCTION(dbg_out), + FUNCTION(ddr_bist), + FUNCTION(ddr_pxi0), + FUNCTION(ddr_pxi1), + FUNCTION(ddr_pxi2), + FUNCTION(ddr_pxi3), + FUNCTION(dp_hot), + FUNCTION(dp_lcd), + FUNCTION(gcc_gp1), + FUNCTION(gcc_gp2), + FUNCTION(gcc_gp3), + FUNCTION(gpio), + FUNCTION(ibi_i3c), + FUNCTION(jitter_bist), + FUNCTION(lpass_slimbus), + FUNCTION(mdp_vsync), + FUNCTION(mdp_vsync0), + FUNCTION(mdp_vsync1), + FUNCTION(mdp_vsync2), + FUNCTION(mdp_vsync3), + FUNCTION(mi2s0_data0), + FUNCTION(mi2s0_data1), + FUNCTION(mi2s0_sck), + FUNCTION(mi2s0_ws), + FUNCTION(mi2s1_data0), + FUNCTION(mi2s1_data1), + FUNCTION(mi2s1_sck), + FUNCTION(mi2s1_ws), + FUNCTION(mi2s2_data0), + FUNCTION(mi2s2_data1), + FUNCTION(mi2s2_sck), + FUNCTION(mi2s2_ws), + FUNCTION(pci_e0), + FUNCTION(pci_e1), + FUNCTION(pci_e2), + FUNCTION(phase_flag), + FUNCTION(pll_bist), + FUNCTION(pll_bypassnl), + FUNCTION(pll_clk), + FUNCTION(pll_reset), + FUNCTION(pri_mi2s), + FUNCTION(prng_rosc), + FUNCTION(qdss_cti), + FUNCTION(qdss_gpio), + FUNCTION(qspi0), + FUNCTION(qspi1), + FUNCTION(qspi2), + FUNCTION(qspi3), + FUNCTION(qspi_clk), + FUNCTION(qspi_cs), + FUNCTION(qup0), + FUNCTION(qup1), + FUNCTION(qup10), + FUNCTION(qup11), + FUNCTION(qup12), + FUNCTION(qup13), + FUNCTION(qup14), + FUNCTION(qup15), + FUNCTION(qup16), + FUNCTION(qup17), + FUNCTION(qup18), + FUNCTION(qup19), + FUNCTION(qup2), + FUNCTION(qup3), + FUNCTION(qup4), + FUNCTION(qup5), + FUNCTION(qup6), + FUNCTION(qup7), + FUNCTION(qup8), + FUNCTION(qup9), + FUNCTION(qup_l4), + FUNCTION(qup_l5), + FUNCTION(qup_l6), + FUNCTION(sd_write), + FUNCTION(sdc40), + FUNCTION(sdc41), + FUNCTION(sdc42), + FUNCTION(sdc43), + FUNCTION(sdc4_clk), + FUNCTION(sdc4_cmd), + FUNCTION(sec_mi2s), + FUNCTION(sp_cmu), + FUNCTION(tgu_ch0), + FUNCTION(tgu_ch1), + FUNCTION(tgu_ch2), + FUNCTION(tgu_ch3), + FUNCTION(tsense_pwm1), + FUNCTION(tsense_pwm2), + FUNCTION(tsif0_clk), + FUNCTION(tsif0_data), + FUNCTION(tsif0_en), + FUNCTION(tsif0_error), + FUNCTION(tsif0_sync), + FUNCTION(tsif1_clk), + FUNCTION(tsif1_data), + FUNCTION(tsif1_en), + FUNCTION(tsif1_error), + FUNCTION(tsif1_sync), + FUNCTION(usb2phy_ac), + FUNCTION(usb_phy), + FUNCTION(vsense_trigger), +}; + +/* Every pin is maintained as a single group, and missing or non-existing pin + * would be maintained as dummy group to synchronize pin group index with + * pin descriptor registered with pinctrl core. + * Clients would not be able to request these dummy pin groups. + */ +static const struct msm_pingroup sm8250_groups[] = { + [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _), + [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _), + [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _), + [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _), + [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _), + [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _), + [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _), + [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _), + [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _), + [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _), + [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _), + [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _), + [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _), + [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _), + [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _), + [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _), + [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _), + [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _), + [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _), + [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _), + [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _), + [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _), + [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _), + [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _), + [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _), + [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _), + [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _), + [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _), + [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _), + [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _), + [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _), + [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _), + [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _), + [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _), + [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _), + [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _), + [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _), + [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _), + [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _), + [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _), + [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _), + [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _), + [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _), + [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _), + [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _), + [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _), + [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _), + [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _), + [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _), + [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _), + [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _), + [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _), + [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _), + [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _), + [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _), + [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _), + [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _), + [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _), + [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _), + [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _), + [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _), + [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _), + [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _), + [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _), + [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _), + [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _), + [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _), + [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _), + [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _), + [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _), + [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _), + [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _), + [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _), + [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _), + [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _), + [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _), + [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _), + [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _), + [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _), + [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _), + [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _), + [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _), + [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _), + [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _), + [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _), + [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _), + [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _), + [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _), + [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _), + [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _), + [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _), + [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _), + [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _), + [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _), + [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _), + [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _), + [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _), + [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _), + [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _), + [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _), + [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _), + [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _), + [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _), + [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _), + [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _), + [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _), + [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _), + [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _), + [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _), + [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _), + [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _), + [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _), + [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _), + [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _), + [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _), + [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _), + [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _), + [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _), + [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _), + [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _), + [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _), + [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _), + [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _), + [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _), + [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _), + [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _), + [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _), + [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _), + [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _), + [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _), + [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _), + [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _), + [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _), + [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _), + [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _), + [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _), + [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _), + [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _), + [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _), + [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _), + [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _), + [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _), + [180] = UFS_RESET(ufs_reset, 0xb8000), + [181] = SDC_PINGROUP(sdc2_clk, 0x7000, 14, 6), + [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3), + [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0), +}; + +static const struct msm_pinctrl_soc_data sm8250_pinctrl = { + .pins = sm8250_pins, + .npins = ARRAY_SIZE(sm8250_pins), + .functions = sm8250_functions, + .nfunctions = ARRAY_SIZE(sm8250_functions), + .groups = sm8250_groups, + .ngroups = ARRAY_SIZE(sm8250_groups), + .ngpios = 181, + .tiles = sm8250_tiles, + .ntiles = ARRAY_SIZE(sm8250_tiles), +}; + +static int sm8250_pinctrl_probe(struct platform_device *pdev) +{ + return msm_pinctrl_probe(pdev, &sm8250_pinctrl); +} + +static const struct of_device_id sm8250_pinctrl_of_match[] = { + { .compatible = "qcom,sm8250-pinctrl", }, + { }, +}; + +static struct platform_driver sm8250_pinctrl_driver = { + .driver = { + .name = "sm8250-pinctrl", + .of_match_table = sm8250_pinctrl_of_match, + }, + .probe = sm8250_pinctrl_probe, + .remove = msm_pinctrl_remove, +}; + +static int __init sm8250_pinctrl_init(void) +{ + return platform_driver_register(&sm8250_pinctrl_driver); +} +arch_initcall(sm8250_pinctrl_init); + +static void __exit sm8250_pinctrl_exit(void) +{ + platform_driver_unregister(&sm8250_pinctrl_driver); +} +module_exit(sm8250_pinctrl_exit); + +MODULE_DESCRIPTION("QTI sm8250 pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match); From f354157a7d184db430c1a564c506434e33b1bec5 Mon Sep 17 00:00:00 2001 From: Jonathan Bakker Date: Sat, 25 Apr 2020 16:10:46 -0700 Subject: [PATCH 36/72] pinctrl: samsung: Save/restore eint_mask over suspend for EINT_TYPE GPIOs Currently, for EINT_TYPE GPIOs, the CON and FLTCON registers are saved and restored over a suspend/resume cycle. However, the EINT_MASK registers are not. On S5PV210 at the very least, these registers are not retained over suspend, leading to the interrupts remaining masked upon resume and therefore no interrupts being triggered for the device. There should be no effect on any SoCs that do retain these registers as theoretically we would just be re-writing what was already there. Fixes: 7ccbc60cd9c2 ("pinctrl: exynos: Handle suspend/resume of GPIO EINT registers") Cc: Signed-off-by: Jonathan Bakker Signed-off-by: Krzysztof Kozlowski --- drivers/pinctrl/samsung/pinctrl-exynos.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c index 5126a5a6d4c0..84501c785473 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -267,6 +267,7 @@ struct exynos_eint_gpio_save { u32 eint_con; u32 eint_fltcon0; u32 eint_fltcon1; + u32 eint_mask; }; /* @@ -633,10 +634,13 @@ static void exynos_pinctrl_suspend_bank( + 2 * bank->eint_offset); save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4); + save->eint_mask = readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) @@ -678,6 +682,9 @@ static void exynos_pinctrl_resume_bank( pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4), save->eint_fltcon1); + pr_debug("%s: mask %#010x => %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + bank->eint_offset); @@ -685,6 +692,8 @@ static void exynos_pinctrl_resume_bank( + 2 * bank->eint_offset); writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); } void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) From ef1d0bce38cf1b4293afe6088dbe9524bc5d434f Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 17 Apr 2020 20:33:48 +0200 Subject: [PATCH 37/72] pinctrl: meson: implement the gpio_chip get_direction callback Implement the get_direction callback so we read the direction from the actual GPIO controller register. This is recommended by the gpio_chip kernel doc. Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200417183349.1283092-2-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index bbc919bef2bf..291f3078e7c7 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -549,6 +549,18 @@ static const struct pinconf_ops meson_pinconf_ops = { .is_generic = true, }; +static int meson_gpio_get_direction(struct gpio_chip *chip, unsigned gpio) +{ + struct meson_pinctrl *pc = gpiochip_get_data(chip); + int ret; + + ret = meson_pinconf_get_output(pc, gpio); + if (ret < 0) + return ret; + + return ret ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; +} + static int meson_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) { return meson_pinconf_set_output(gpiochip_get_data(chip), gpio, false); @@ -591,6 +603,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.parent = pc->dev; pc->chip.request = gpiochip_generic_request; pc->chip.free = gpiochip_generic_free; + pc->chip.get_direction = meson_gpio_get_direction; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; pc->chip.get = meson_gpio_get; From f8f0aa00898f3348fa323ae27d83463aace72394 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 17 Apr 2020 20:33:49 +0200 Subject: [PATCH 38/72] pinctrl: meson: wire up the gpio_chip's set_config callback Use gpiochip_generic_config for the gpio_chip's set_config callback so GPIO flags like GPIO_PULL_UP or GPIO_PULL_DOWN can be used in the board .dts descriptions. This is required for some Meson8m2 boards where GPIO_BSD_EN provides the "MUTE" signal and requires enabling the internal pull-up resistor. Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20200417183349.1283092-3-martin.blumenstingl@googlemail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/meson/pinctrl-meson.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c index 291f3078e7c7..079f8ee8d353 100644 --- a/drivers/pinctrl/meson/pinctrl-meson.c +++ b/drivers/pinctrl/meson/pinctrl-meson.c @@ -603,6 +603,7 @@ static int meson_gpiolib_register(struct meson_pinctrl *pc) pc->chip.parent = pc->dev; pc->chip.request = gpiochip_generic_request; pc->chip.free = gpiochip_generic_free; + pc->chip.set_config = gpiochip_generic_config; pc->chip.get_direction = meson_gpio_get_direction; pc->chip.direction_input = meson_gpio_direction_input; pc->chip.direction_output = meson_gpio_direction_output; From d71ffeb9f250a89fe477d9b3645f49680dc6c685 Mon Sep 17 00:00:00 2001 From: Dejin Zheng Date: Tue, 21 Apr 2020 22:24:02 +0800 Subject: [PATCH 39/72] pinctrl: fix several typos use codespell to fix lots of typos over frontends. Signed-off-by: Dejin Zheng Reviewed-by: Geert Uytterhoeven Acked-by: Geert Uytterhoeven CC: Andy Shevchenko Link: https://lore.kernel.org/r/20200421142402.9524-1-zhengdejin5@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 2 +- drivers/pinctrl/pinctrl-lantiq.c | 2 +- drivers/pinctrl/pinctrl-sx150x.c | 2 +- drivers/pinctrl/sh-pfc/pfc-sh7269.c | 5 +++-- drivers/pinctrl/tegra/pinctrl-tegra-xusb.c | 2 +- drivers/pinctrl/zte/pinctrl-zx.c | 2 +- 6 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index c00d0022d311..0c1c0e72fa8e 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -60,7 +60,7 @@ struct imx1_pinctrl { /* * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX - * control register are seperated into function, output configuration, input + * control registers are separated into function, output configuration, input * configuration A, input configuration B, GPIO in use and data direction. * * Those controls that are represented by 1 bit have a direct mapping between diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c index aa92f141b865..626e02d7a1ba 100644 --- a/drivers/pinctrl/pinctrl-lantiq.c +++ b/drivers/pinctrl/pinctrl-lantiq.c @@ -221,7 +221,7 @@ static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) return i; } -/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */ +/* don't assume .mfp is linearly mapped. find the mfp with the correct .pin */ static int match_mfp(const struct ltq_pinmux_info *info, int pin) { int i; diff --git a/drivers/pinctrl/pinctrl-sx150x.c b/drivers/pinctrl/pinctrl-sx150x.c index 6e74bd87d959..708bc91862fe 100644 --- a/drivers/pinctrl/pinctrl-sx150x.c +++ b/drivers/pinctrl/pinctrl-sx150x.c @@ -988,7 +988,7 @@ static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, /* * In order to mask the differences between 16 and 8 bit expander * devices we set up a sligthly ficticious regmap that pretends to be - * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh + * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh * pair/quartet) registers and transparently reconstructs those * registers via multiple I2C/SMBus reads * diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c index d20974a55d93..e2916aaa8304 100644 --- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c +++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c @@ -1963,8 +1963,9 @@ static const struct pinmux_func pinmux_func_gpios[] = { static const struct pinmux_cfg_reg pinmux_config_regs[] = { /* "name" addr register_size Field_Width */ - /* where Field_Width is 1 for single mode registers or 4 for upto 16 - mode registers and modes are described in assending order [0..16] */ + /* where Field_Width is 1 for single mode registers or 4 for up to 16 + * mode registers and modes are described in assending order [0..15] + */ { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1, GROUP( 0, 0, 0, 0, 0, 0, 0, 0, diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c index 6f7b3767f453..43922ab81666 100644 --- a/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c +++ b/drivers/pinctrl/tegra/pinctrl-tegra-xusb.c @@ -123,7 +123,7 @@ static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl, unsigned *num_pins) { /* - * For the tegra-xusb pad controller groups are synonomous + * For the tegra-xusb pad controller groups are synonymous * with lanes/pins and there is always one lane/pin per group. */ *pins = &pinctrl->desc->pins[group].number; diff --git a/drivers/pinctrl/zte/pinctrl-zx.c b/drivers/pinctrl/zte/pinctrl-zx.c index 786bf89487d6..80d00ab8c110 100644 --- a/drivers/pinctrl/zte/pinctrl-zx.c +++ b/drivers/pinctrl/zte/pinctrl-zx.c @@ -94,7 +94,7 @@ static int zx_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector, if (data->aon_pin) { /* * It's an AON pin, whose mux register offset and bit position - * can be caluculated from pin number. Each register covers 16 + * can be calculated from pin number. Each register covers 16 * pins, and each pin occupies 2 bits. */ u16 aoffset = pindesc->number / 16 * 4; From 36126f5309b5054c2a57f7c603a6f8da1f4800d4 Mon Sep 17 00:00:00 2001 From: Amelie Delaunay Date: Wed, 22 Apr 2020 09:25:13 +0200 Subject: [PATCH 40/72] pinctrl: stmfx: stmfx_pinconf_set doesn't require to get direction anymore Pin direction is not used to set pin configuration. Fixes: a502b343ebd0 ("pinctrl: stmfx: update pinconf settings") Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20200422072513.8352-1-amelie.delaunay@st.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-stmfx.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pinctrl/pinctrl-stmfx.c b/drivers/pinctrl/pinctrl-stmfx.c index 60100b45f5e5..1aae803c12cd 100644 --- a/drivers/pinctrl/pinctrl-stmfx.c +++ b/drivers/pinctrl/pinctrl-stmfx.c @@ -288,7 +288,7 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, struct pinctrl_gpio_range *range; enum pin_config_param param; u32 arg; - int dir, i, ret; + int i, ret; range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); if (!range) { @@ -296,10 +296,6 @@ static int stmfx_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, return -EINVAL; } - dir = stmfx_gpio_get_direction(&pctl->gpio_chip, pin); - if (dir < 0) - return dir; - for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); From 0320d260a7e730f1a85c49764ad8d8c41a8512ec Mon Sep 17 00:00:00 2001 From: Jason Yan Date: Tue, 28 Apr 2020 19:55:43 +0800 Subject: [PATCH 41/72] pinctrl: bm1880: add pwm37 to bm1880_pctrl_groups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The 'pwm37' is not added to bm1880_pctrl_groups, which triggers a gcc build warning: drivers/pinctrl/pinctrl-bm1880.c:263:27: warning: ‘pwm37_pins’ defined but not used [-Wunused-const-variable=] static const unsigned int pwm37_pins[] = { 110 }; Signed-off-by: Jason Yan Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20200428115543.33379-1-yanaijie@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-bm1880.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/pinctrl-bm1880.c b/drivers/pinctrl/pinctrl-bm1880.c index f7dff4f14101..d1a7d9836787 100644 --- a/drivers/pinctrl/pinctrl-bm1880.c +++ b/drivers/pinctrl/pinctrl-bm1880.c @@ -408,6 +408,7 @@ static const struct bm1880_pctrl_group bm1880_pctrl_groups[] = { BM1880_PINCTRL_GRP(pwm34), BM1880_PINCTRL_GRP(pwm35), BM1880_PINCTRL_GRP(pwm36), + BM1880_PINCTRL_GRP(pwm37), BM1880_PINCTRL_GRP(i2c0), BM1880_PINCTRL_GRP(i2c1), BM1880_PINCTRL_GRP(i2c2), From 767972b9b4edf3f8386cfe05b798b291ff438613 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 28 Apr 2020 11:38:12 +0200 Subject: [PATCH 42/72] pinctrl: ab8505: Define group for GPIO pin 50 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Hulk robot reports an usused varible: drivers/pinctrl/nomadik/pinctrl-ab8505.c:137:23: warning: ‘gpio50_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned gpio50_a_1_pins[] = { AB8505_PIN_L4 }; ^~~~~~~~~~~~~~~ This variable actually should be used. Probably an oversight by the driver author. Cc: Patrice Chotard Reported-by: Hulk Robot Reported-by: Jason Yan Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-ab8505.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/nomadik/pinctrl-ab8505.c b/drivers/pinctrl/nomadik/pinctrl-ab8505.c index 5e6e7d28390a..b93af1fb37f0 100644 --- a/drivers/pinctrl/nomadik/pinctrl-ab8505.c +++ b/drivers/pinctrl/nomadik/pinctrl-ab8505.c @@ -178,6 +178,7 @@ static const struct abx500_pingroup ab8505_groups[] = { AB8505_PIN_GROUP(gpio40_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio41_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(uartrxdata_a_1, ABX500_ALT_A), + AB8505_PIN_GROUP(gpio50_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio52_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(gpio53_a_1, ABX500_ALT_A), AB8505_PIN_GROUP(pdmdata_b_1, ABX500_ALT_B), From 32c8a94660e8f00fb81849de8f109951118532aa Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Tue, 28 Apr 2020 11:53:31 +0200 Subject: [PATCH 43/72] pinctrl: db8500: Fix some old bugs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Hulk robot reports these build warnings: drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:899:20: warning: ‘sbag_groups’ defined but not used [-Wunused-const-variable=] DB8500_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc4_1"); ^ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:570:23: warning: ‘ipgpio6_c_2_pins’ defined but not used [-Wunused-const-variable=] static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; ^~~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:472:23: warning: ‘mc1dir_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, ^~~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:453:23: warning: ‘modem_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, ^~~~~~~~~~~~~~ drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c:430:23: warning: ‘kpskaskb_a_1_pins’ defined but not used [-Wunused-const-variable=] static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; ^~~~~~~~~~~~~~~~~ They are just very old bugs in seldomly used pin groups. Fix the problem by using the pins and referencing the function. Reported-by: Hulk Robot Reported-by: Jason Yan Signed-off-by: Linus Walleij --- drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c index b9246e0b4fe2..acad3887cc74 100644 --- a/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c +++ b/drivers/pinctrl/nomadik/pinctrl-nomadik-db8500.c @@ -691,18 +691,21 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(kpskaskb_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(modem_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(kp_a_2, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A), + DB8500_PIN_GROUP(mc1dir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A), @@ -760,7 +763,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = { DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), - DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), + DB8500_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), @@ -955,6 +958,7 @@ static const struct nmk_function nmk_db8500_functions[] = { FUNCTION(spi0), FUNCTION(spi2), FUNCTION(remap), + FUNCTION(sbag), FUNCTION(ptm), FUNCTION(rf), FUNCTION(hx), From 8068071c09e546e6c13e728da0531b56917802e7 Mon Sep 17 00:00:00 2001 From: Rikard Falkeborn Date: Sat, 25 Apr 2020 22:38:13 +0200 Subject: [PATCH 44/72] pinctrl: rk805: Constify rk805_gpio_cfgs Mark pin_cfg as const, allowing the compiler to put the struct in .rodata instead of .data. Signed-off-by: Rikard Falkeborn Link: https://lore.kernel.org/r/20200425203813.6442-1-rikard.falkeborn@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rk805.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c index cccbe072274e..c6f4229eb106 100644 --- a/drivers/pinctrl/pinctrl-rk805.c +++ b/drivers/pinctrl/pinctrl-rk805.c @@ -73,7 +73,7 @@ struct rk805_pctrl_info { int num_pin_groups; const struct pinctrl_pin_desc *pins; unsigned int num_pins; - struct rk805_pin_config *pin_cfg; + const struct rk805_pin_config *pin_cfg; }; enum rk805_pinmux_option { @@ -121,7 +121,7 @@ static const struct rk805_pin_group rk805_pin_groups[] = { #define RK805_GPIO0_VAL_MSK BIT(0) #define RK805_GPIO1_VAL_MSK BIT(1) -static struct rk805_pin_config rk805_gpio_cfgs[] = { +static const struct rk805_pin_config rk805_gpio_cfgs[] = { { .reg = RK805_OUT_REG, .val_msk = RK805_GPIO0_VAL_MSK, From 9a0f1341df7d555eb50a826d1f6f4191a78eabea Mon Sep 17 00:00:00 2001 From: Paul Cercueil Date: Sun, 3 May 2020 18:45:49 +0200 Subject: [PATCH 45/72] pinctrl: ingenic: Add irq_{request,release}_resources callbacks These are called when a GPIO is to be used as IRQ. Without these custom callbacks, when an interrupt is requested directly and not through gpiod_to_irq(), the request fails because the GPIO is not necesarily in input mode. These callbacks simply enforce that the requested GPIO is in input mode. Signed-off-by: Paul Cercueil Link: https://lore.kernel.org/r/20200503164549.163884-1-paul@crapouillou.net Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ingenic.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index e5dcf77fe43d..6a8d44504f94 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -1977,6 +1977,25 @@ static const struct pinctrl_ops ingenic_pctlops = { .dt_free_map = pinconf_generic_dt_free_map, }; +static int ingenic_gpio_irq_request(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + int ret; + + ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq); + if (ret) + return ret; + + return gpiochip_reqres_irq(gpio_chip, data->hwirq); +} + +static void ingenic_gpio_irq_release(struct irq_data *data) +{ + struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data); + + return gpiochip_relres_irq(gpio_chip, data->hwirq); +} + static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc, int pin, int func) { @@ -2338,6 +2357,8 @@ static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc, jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack; jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type; jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake; + jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request; + jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release; jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; girq = &jzgc->gc.irq; From c7acd6fe8a2881771f2cb374b36d17b5109abbde Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Tue, 5 May 2020 16:08:40 +0200 Subject: [PATCH 46/72] pinctrl: mediatek: add pinctrl-mtk-common-v2 module license Kbuild warns when this file is built as a loadable module: WARNING: modpost: missing MODULE_LICENSE() in drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.o see include/linux/module.h for more information Add the missing license/author/description tags. Fixes: 8174a8512e3e ("pinctrl: mediatek: make MediaTek pinctrl v2 driver ready for buidling loadable module") Signed-off-by: Arnd Bergmann Link: https://lore.kernel.org/r/20200505140848.554957-1-arnd@arndb.de Signed-off-by: Linus Walleij --- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c index 6ea40b501328..b77b18fe5adc 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c @@ -993,3 +993,7 @@ int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, return 0; } EXPORT_SYMBOL_GPL(mtk_pinconf_adv_drive_get); + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Sean Wang "); +MODULE_DESCRIPTION("Pin configuration library module for mediatek SoCs"); From c4f333b758ab4d8d4bc643e8bddac96082e0c379 Mon Sep 17 00:00:00 2001 From: Dafna Hirschfeld Date: Wed, 6 May 2020 12:14:24 +0200 Subject: [PATCH 47/72] pinctrl: rockchip: return ENOMEM instead of EINVAL if allocation fails The function rockchip_pinctrl_parse_dt returns -EINVAL if allocation fails. Change the return error to -ENOMEM Signed-off-by: Dafna Hirschfeld Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20200506101424.15691-1-dafna.hirschfeld@collabora.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 098951346339..a9299f0bd21e 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -2940,14 +2940,14 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, sizeof(struct rockchip_pmx_func), GFP_KERNEL); if (!info->functions) - return -EINVAL; + return -ENOMEM; info->groups = devm_kcalloc(dev, info->ngroups, sizeof(struct rockchip_pin_group), GFP_KERNEL); if (!info->groups) - return -EINVAL; + return -ENOMEM; i = 0; From d7faa8ffb6be57bf8233a4b5a636d76b83c51ce7 Mon Sep 17 00:00:00 2001 From: Dafna Hirschfeld Date: Wed, 6 May 2020 12:09:03 +0200 Subject: [PATCH 48/72] pinctrl: rockchip: fix memleak in rockchip_dt_node_to_map In function rockchip_dt_node_to_map, a new_map variable is allocated by: new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), GFP_KERNEL); This uses devres and attaches new_map to the pinctrl driver. This cause a leak since new_map is not released when the probed driver is removed. Fix it by using kcalloc to allocate new_map and free it in `rockchip_dt_free_map` Signed-off-by: Dafna Hirschfeld Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20200506100903.15420-1-dafna.hirschfeld@collabora.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-rockchip.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index a9299f0bd21e..c07324d1f265 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -508,8 +508,8 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, } map_num += grp->npins; - new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), - GFP_KERNEL); + + new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL); if (!new_map) return -ENOMEM; @@ -519,7 +519,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, /* create mux map */ parent = of_get_parent(np); if (!parent) { - devm_kfree(pctldev->dev, new_map); + kfree(new_map); return -EINVAL; } new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; @@ -546,6 +546,7 @@ static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, struct pinctrl_map *map, unsigned num_maps) { + kfree(map); } static const struct pinctrl_ops rockchip_pctrl_ops = { From baf674bf717f8224f33e453e1df92a96c4d6ce48 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 3 May 2020 22:46:45 +0100 Subject: [PATCH 49/72] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support Document PFC support for the RZ/G1H (R8A7742) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Acked-by: Rob Herring Link: https://lore.kernel.org/r/1588542414-14826-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt index 6eada23eaa31..b68613188c19 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt @@ -13,6 +13,7 @@ Required Properties: - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. + - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. From 4ecc7ff82ecfdf44997ed2a1016945fc8f6fca3e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 3 May 2020 22:46:46 +0100 Subject: [PATCH 50/72] pinctrl: sh-pfc: r8a7790: Add r8a7742 PFC support Renesas RZ/G1H (R8A7742) is pin compatible with R-Car H2 (R8A7790), however it doesn't have several automotive specific peripherals. Add automotive-specific pin groups/functions along with common pin groups/functions for supporting both r8a7790 and r8a7742 SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1588542414-14826-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 4 + drivers/pinctrl/sh-pfc/Makefile | 1 + drivers/pinctrl/sh-pfc/core.c | 6 + drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 744 ++++++++++++++------------- drivers/pinctrl/sh-pfc/sh_pfc.h | 1 + 5 files changed, 404 insertions(+), 352 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 9552851b96f1..c461a2f1927a 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -12,6 +12,7 @@ config PINCTRL_SH_PFC select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 + select PINCTRL_PFC_R8A7742 if ARCH_R8A7742 select PINCTRL_PFC_R8A7743 if ARCH_R8A7743 select PINCTRL_PFC_R8A7744 if ARCH_R8A7744 select PINCTRL_PFC_R8A7745 if ARCH_R8A7745 @@ -74,6 +75,9 @@ config PINCTRL_PFC_R8A7740 bool "R-Mobile A1 pin control support" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7742 + bool "RZ/G1H pin control support" if COMPILE_TEST + config PINCTRL_PFC_R8A7743 bool "RZ/G1M pin control support" if COMPILE_TEST diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 9ebe321d24c4..3855d82069c9 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o +obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o obj-$(CONFIG_PINCTRL_PFC_R8A7743) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7744) += pfc-r8a7791.o obj-$(CONFIG_PINCTRL_PFC_R8A7745) += pfc-r8a7794.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c index a2e19efa26e3..f368383cba61 100644 --- a/drivers/pinctrl/sh-pfc/core.c +++ b/drivers/pinctrl/sh-pfc/core.c @@ -485,6 +485,12 @@ static const struct of_device_id sh_pfc_of_table[] = { .data = &r8a7740_pinmux_info, }, #endif +#ifdef CONFIG_PINCTRL_PFC_R8A7742 + { + .compatible = "renesas,pfc-r8a7742", + .data = &r8a7742_pinmux_info, + }, +#endif #ifdef CONFIG_PINCTRL_PFC_R8A7743 { .compatible = "renesas,pfc-r8a7743", diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 3366ed561cce..f524401fec5f 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3938,297 +3938,304 @@ static const unsigned int vin3_clk_mux[] = { VI3_CLK_MARK, }; -static const struct sh_pfc_pin_group pinmux_groups[] = { - SH_PFC_PIN_GROUP(audio_clk_a), - SH_PFC_PIN_GROUP(audio_clk_b), - SH_PFC_PIN_GROUP(audio_clk_c), - SH_PFC_PIN_GROUP(audio_clkout), - SH_PFC_PIN_GROUP(audio_clkout_b), - SH_PFC_PIN_GROUP(audio_clkout_c), - SH_PFC_PIN_GROUP(audio_clkout_d), - SH_PFC_PIN_GROUP(avb_link), - SH_PFC_PIN_GROUP(avb_magic), - SH_PFC_PIN_GROUP(avb_phy_int), - SH_PFC_PIN_GROUP(avb_mdio), - SH_PFC_PIN_GROUP(avb_mii), - SH_PFC_PIN_GROUP(avb_gmii), - SH_PFC_PIN_GROUP(du_rgb666), - SH_PFC_PIN_GROUP(du_rgb888), - SH_PFC_PIN_GROUP(du_clk_out_0), - SH_PFC_PIN_GROUP(du_clk_out_1), - SH_PFC_PIN_GROUP(du_sync_0), - SH_PFC_PIN_GROUP(du_sync_1), - SH_PFC_PIN_GROUP(du_cde), - SH_PFC_PIN_GROUP(du0_clk_in), - SH_PFC_PIN_GROUP(du1_clk_in), - SH_PFC_PIN_GROUP(du2_clk_in), - SH_PFC_PIN_GROUP(eth_link), - SH_PFC_PIN_GROUP(eth_magic), - SH_PFC_PIN_GROUP(eth_mdio), - SH_PFC_PIN_GROUP(eth_rmii), - SH_PFC_PIN_GROUP(hscif0_data), - SH_PFC_PIN_GROUP(hscif0_clk), - SH_PFC_PIN_GROUP(hscif0_ctrl), - SH_PFC_PIN_GROUP(hscif0_data_b), - SH_PFC_PIN_GROUP(hscif0_ctrl_b), - SH_PFC_PIN_GROUP(hscif0_data_c), - SH_PFC_PIN_GROUP(hscif0_ctrl_c), - SH_PFC_PIN_GROUP(hscif0_data_d), - SH_PFC_PIN_GROUP(hscif0_ctrl_d), - SH_PFC_PIN_GROUP(hscif0_data_e), - SH_PFC_PIN_GROUP(hscif0_ctrl_e), - SH_PFC_PIN_GROUP(hscif0_data_f), - SH_PFC_PIN_GROUP(hscif0_ctrl_f), - SH_PFC_PIN_GROUP(hscif1_data), - SH_PFC_PIN_GROUP(hscif1_clk), - SH_PFC_PIN_GROUP(hscif1_ctrl), - SH_PFC_PIN_GROUP(hscif1_data_b), - SH_PFC_PIN_GROUP(hscif1_clk_b), - SH_PFC_PIN_GROUP(hscif1_ctrl_b), - SH_PFC_PIN_GROUP(i2c0), - SH_PFC_PIN_GROUP(i2c1), - SH_PFC_PIN_GROUP(i2c1_b), - SH_PFC_PIN_GROUP(i2c1_c), - SH_PFC_PIN_GROUP(i2c2), - SH_PFC_PIN_GROUP(i2c2_b), - SH_PFC_PIN_GROUP(i2c2_c), - SH_PFC_PIN_GROUP(i2c2_d), - SH_PFC_PIN_GROUP(i2c2_e), - SH_PFC_PIN_GROUP(i2c3), - SH_PFC_PIN_GROUP(iic0), - SH_PFC_PIN_GROUP(iic1), - SH_PFC_PIN_GROUP(iic1_b), - SH_PFC_PIN_GROUP(iic1_c), - SH_PFC_PIN_GROUP(iic2), - SH_PFC_PIN_GROUP(iic2_b), - SH_PFC_PIN_GROUP(iic2_c), - SH_PFC_PIN_GROUP(iic2_d), - SH_PFC_PIN_GROUP(iic2_e), - SH_PFC_PIN_GROUP(iic3), - SH_PFC_PIN_GROUP(intc_irq0), - SH_PFC_PIN_GROUP(intc_irq1), - SH_PFC_PIN_GROUP(intc_irq2), - SH_PFC_PIN_GROUP(intc_irq3), - SH_PFC_PIN_GROUP(mlb_3pin), - SH_PFC_PIN_GROUP(mmc0_data1), - SH_PFC_PIN_GROUP(mmc0_data4), - SH_PFC_PIN_GROUP(mmc0_data8), - SH_PFC_PIN_GROUP(mmc0_ctrl), - SH_PFC_PIN_GROUP(mmc1_data1), - SH_PFC_PIN_GROUP(mmc1_data4), - SH_PFC_PIN_GROUP(mmc1_data8), - SH_PFC_PIN_GROUP(mmc1_ctrl), - SH_PFC_PIN_GROUP(msiof0_clk), - SH_PFC_PIN_GROUP(msiof0_sync), - SH_PFC_PIN_GROUP(msiof0_ss1), - SH_PFC_PIN_GROUP(msiof0_ss2), - SH_PFC_PIN_GROUP(msiof0_rx), - SH_PFC_PIN_GROUP(msiof0_tx), - SH_PFC_PIN_GROUP(msiof0_clk_b), - SH_PFC_PIN_GROUP(msiof0_ss1_b), - SH_PFC_PIN_GROUP(msiof0_ss2_b), - SH_PFC_PIN_GROUP(msiof0_rx_b), - SH_PFC_PIN_GROUP(msiof0_tx_b), - SH_PFC_PIN_GROUP(msiof1_clk), - SH_PFC_PIN_GROUP(msiof1_sync), - SH_PFC_PIN_GROUP(msiof1_ss1), - SH_PFC_PIN_GROUP(msiof1_ss2), - SH_PFC_PIN_GROUP(msiof1_rx), - SH_PFC_PIN_GROUP(msiof1_tx), - SH_PFC_PIN_GROUP(msiof1_clk_b), - SH_PFC_PIN_GROUP(msiof1_ss1_b), - SH_PFC_PIN_GROUP(msiof1_ss2_b), - SH_PFC_PIN_GROUP(msiof1_rx_b), - SH_PFC_PIN_GROUP(msiof1_tx_b), - SH_PFC_PIN_GROUP(msiof2_clk), - SH_PFC_PIN_GROUP(msiof2_sync), - SH_PFC_PIN_GROUP(msiof2_ss1), - SH_PFC_PIN_GROUP(msiof2_ss2), - SH_PFC_PIN_GROUP(msiof2_rx), - SH_PFC_PIN_GROUP(msiof2_tx), - SH_PFC_PIN_GROUP(msiof3_clk), - SH_PFC_PIN_GROUP(msiof3_sync), - SH_PFC_PIN_GROUP(msiof3_ss1), - SH_PFC_PIN_GROUP(msiof3_ss2), - SH_PFC_PIN_GROUP(msiof3_rx), - SH_PFC_PIN_GROUP(msiof3_tx), - SH_PFC_PIN_GROUP(msiof3_clk_b), - SH_PFC_PIN_GROUP(msiof3_sync_b), - SH_PFC_PIN_GROUP(msiof3_rx_b), - SH_PFC_PIN_GROUP(msiof3_tx_b), - SH_PFC_PIN_GROUP(pwm0), - SH_PFC_PIN_GROUP(pwm0_b), - SH_PFC_PIN_GROUP(pwm1), - SH_PFC_PIN_GROUP(pwm1_b), - SH_PFC_PIN_GROUP(pwm2), - SH_PFC_PIN_GROUP(pwm3), - SH_PFC_PIN_GROUP(pwm4), - SH_PFC_PIN_GROUP(pwm5), - SH_PFC_PIN_GROUP(pwm6), - SH_PFC_PIN_GROUP(qspi_ctrl), - SH_PFC_PIN_GROUP(qspi_data2), - SH_PFC_PIN_GROUP(qspi_data4), - SH_PFC_PIN_GROUP(scif0_data), - SH_PFC_PIN_GROUP(scif0_clk), - SH_PFC_PIN_GROUP(scif0_ctrl), - SH_PFC_PIN_GROUP(scif0_data_b), - SH_PFC_PIN_GROUP(scif1_data), - SH_PFC_PIN_GROUP(scif1_clk), - SH_PFC_PIN_GROUP(scif1_ctrl), - SH_PFC_PIN_GROUP(scif1_data_b), - SH_PFC_PIN_GROUP(scif1_data_c), - SH_PFC_PIN_GROUP(scif1_data_d), - SH_PFC_PIN_GROUP(scif1_clk_d), - SH_PFC_PIN_GROUP(scif1_data_e), - SH_PFC_PIN_GROUP(scif1_clk_e), - SH_PFC_PIN_GROUP(scif2_data), - SH_PFC_PIN_GROUP(scif2_clk), - SH_PFC_PIN_GROUP(scif2_data_b), - SH_PFC_PIN_GROUP(scifa0_data), - SH_PFC_PIN_GROUP(scifa0_clk), - SH_PFC_PIN_GROUP(scifa0_ctrl), - SH_PFC_PIN_GROUP(scifa0_data_b), - SH_PFC_PIN_GROUP(scifa0_clk_b), - SH_PFC_PIN_GROUP(scifa0_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data), - SH_PFC_PIN_GROUP(scifa1_clk), - SH_PFC_PIN_GROUP(scifa1_ctrl), - SH_PFC_PIN_GROUP(scifa1_data_b), - SH_PFC_PIN_GROUP(scifa1_clk_b), - SH_PFC_PIN_GROUP(scifa1_ctrl_b), - SH_PFC_PIN_GROUP(scifa1_data_c), - SH_PFC_PIN_GROUP(scifa1_clk_c), - SH_PFC_PIN_GROUP(scifa1_ctrl_c), - SH_PFC_PIN_GROUP(scifa1_data_d), - SH_PFC_PIN_GROUP(scifa1_clk_d), - SH_PFC_PIN_GROUP(scifa1_ctrl_d), - SH_PFC_PIN_GROUP(scifa2_data), - SH_PFC_PIN_GROUP(scifa2_clk), - SH_PFC_PIN_GROUP(scifa2_ctrl), - SH_PFC_PIN_GROUP(scifa2_data_b), - SH_PFC_PIN_GROUP(scifa2_data_c), - SH_PFC_PIN_GROUP(scifa2_clk_c), - SH_PFC_PIN_GROUP(scifb0_data), - SH_PFC_PIN_GROUP(scifb0_clk), - SH_PFC_PIN_GROUP(scifb0_ctrl), - SH_PFC_PIN_GROUP(scifb0_data_b), - SH_PFC_PIN_GROUP(scifb0_clk_b), - SH_PFC_PIN_GROUP(scifb0_ctrl_b), - SH_PFC_PIN_GROUP(scifb0_data_c), - SH_PFC_PIN_GROUP(scifb1_data), - SH_PFC_PIN_GROUP(scifb1_clk), - SH_PFC_PIN_GROUP(scifb1_ctrl), - SH_PFC_PIN_GROUP(scifb1_data_b), - SH_PFC_PIN_GROUP(scifb1_clk_b), - SH_PFC_PIN_GROUP(scifb1_ctrl_b), - SH_PFC_PIN_GROUP(scifb1_data_c), - SH_PFC_PIN_GROUP(scifb1_data_d), - SH_PFC_PIN_GROUP(scifb1_data_e), - SH_PFC_PIN_GROUP(scifb1_clk_e), - SH_PFC_PIN_GROUP(scifb1_data_f), - SH_PFC_PIN_GROUP(scifb1_data_g), - SH_PFC_PIN_GROUP(scifb1_clk_g), - SH_PFC_PIN_GROUP(scifb2_data), - SH_PFC_PIN_GROUP(scifb2_clk), - SH_PFC_PIN_GROUP(scifb2_ctrl), - SH_PFC_PIN_GROUP(scifb2_data_b), - SH_PFC_PIN_GROUP(scifb2_clk_b), - SH_PFC_PIN_GROUP(scifb2_ctrl_b), - SH_PFC_PIN_GROUP(scifb2_data_c), - SH_PFC_PIN_GROUP(scif_clk), - SH_PFC_PIN_GROUP(scif_clk_b), - SH_PFC_PIN_GROUP(sdhi0_data1), - SH_PFC_PIN_GROUP(sdhi0_data4), - SH_PFC_PIN_GROUP(sdhi0_ctrl), - SH_PFC_PIN_GROUP(sdhi0_cd), - SH_PFC_PIN_GROUP(sdhi0_wp), - SH_PFC_PIN_GROUP(sdhi1_data1), - SH_PFC_PIN_GROUP(sdhi1_data4), - SH_PFC_PIN_GROUP(sdhi1_ctrl), - SH_PFC_PIN_GROUP(sdhi1_cd), - SH_PFC_PIN_GROUP(sdhi1_wp), - SH_PFC_PIN_GROUP(sdhi2_data1), - SH_PFC_PIN_GROUP(sdhi2_data4), - SH_PFC_PIN_GROUP(sdhi2_ctrl), - SH_PFC_PIN_GROUP(sdhi2_cd), - SH_PFC_PIN_GROUP(sdhi2_wp), - SH_PFC_PIN_GROUP(sdhi3_data1), - SH_PFC_PIN_GROUP(sdhi3_data4), - SH_PFC_PIN_GROUP(sdhi3_ctrl), - SH_PFC_PIN_GROUP(sdhi3_cd), - SH_PFC_PIN_GROUP(sdhi3_wp), - SH_PFC_PIN_GROUP(ssi0_data), - SH_PFC_PIN_GROUP(ssi0129_ctrl), - SH_PFC_PIN_GROUP(ssi1_data), - SH_PFC_PIN_GROUP(ssi1_ctrl), - SH_PFC_PIN_GROUP(ssi2_data), - SH_PFC_PIN_GROUP(ssi2_ctrl), - SH_PFC_PIN_GROUP(ssi3_data), - SH_PFC_PIN_GROUP(ssi34_ctrl), - SH_PFC_PIN_GROUP(ssi4_data), - SH_PFC_PIN_GROUP(ssi4_ctrl), - SH_PFC_PIN_GROUP(ssi5), - SH_PFC_PIN_GROUP(ssi5_b), - SH_PFC_PIN_GROUP(ssi5_c), - SH_PFC_PIN_GROUP(ssi6), - SH_PFC_PIN_GROUP(ssi6_b), - SH_PFC_PIN_GROUP(ssi7_data), - SH_PFC_PIN_GROUP(ssi7_b_data), - SH_PFC_PIN_GROUP(ssi7_c_data), - SH_PFC_PIN_GROUP(ssi78_ctrl), - SH_PFC_PIN_GROUP(ssi78_b_ctrl), - SH_PFC_PIN_GROUP(ssi78_c_ctrl), - SH_PFC_PIN_GROUP(ssi8_data), - SH_PFC_PIN_GROUP(ssi8_b_data), - SH_PFC_PIN_GROUP(ssi8_c_data), - SH_PFC_PIN_GROUP(ssi9_data), - SH_PFC_PIN_GROUP(ssi9_ctrl), - SH_PFC_PIN_GROUP(tpu0_to0), - SH_PFC_PIN_GROUP(tpu0_to1), - SH_PFC_PIN_GROUP(tpu0_to2), - SH_PFC_PIN_GROUP(tpu0_to3), - SH_PFC_PIN_GROUP(usb0), - SH_PFC_PIN_GROUP(usb0_ovc_vbus), - SH_PFC_PIN_GROUP(usb1), - SH_PFC_PIN_GROUP(usb2), - VIN_DATA_PIN_GROUP(vin0_data, 24), - VIN_DATA_PIN_GROUP(vin0_data, 20), - SH_PFC_PIN_GROUP(vin0_data18), - VIN_DATA_PIN_GROUP(vin0_data, 16), - VIN_DATA_PIN_GROUP(vin0_data, 12), - VIN_DATA_PIN_GROUP(vin0_data, 10), - VIN_DATA_PIN_GROUP(vin0_data, 8), - VIN_DATA_PIN_GROUP(vin0_data, 4), - SH_PFC_PIN_GROUP(vin0_sync), - SH_PFC_PIN_GROUP(vin0_field), - SH_PFC_PIN_GROUP(vin0_clkenb), - SH_PFC_PIN_GROUP(vin0_clk), - VIN_DATA_PIN_GROUP(vin1_data, 24), - VIN_DATA_PIN_GROUP(vin1_data, 20), - SH_PFC_PIN_GROUP(vin1_data18), - VIN_DATA_PIN_GROUP(vin1_data, 16), - VIN_DATA_PIN_GROUP(vin1_data, 12), - VIN_DATA_PIN_GROUP(vin1_data, 10), - VIN_DATA_PIN_GROUP(vin1_data, 8), - VIN_DATA_PIN_GROUP(vin1_data, 4), - SH_PFC_PIN_GROUP(vin1_sync), - SH_PFC_PIN_GROUP(vin1_field), - SH_PFC_PIN_GROUP(vin1_clkenb), - SH_PFC_PIN_GROUP(vin1_clk), - VIN_DATA_PIN_GROUP(vin2_data, 24), - SH_PFC_PIN_GROUP(vin2_data18), - VIN_DATA_PIN_GROUP(vin2_data, 16), - VIN_DATA_PIN_GROUP(vin2_data, 8), - VIN_DATA_PIN_GROUP(vin2_data, 4), - SH_PFC_PIN_GROUP(vin2_sync), - SH_PFC_PIN_GROUP(vin2_field), - SH_PFC_PIN_GROUP(vin2_clkenb), - SH_PFC_PIN_GROUP(vin2_clk), - SH_PFC_PIN_GROUP(vin3_data8), - SH_PFC_PIN_GROUP(vin3_sync), - SH_PFC_PIN_GROUP(vin3_field), - SH_PFC_PIN_GROUP(vin3_clkenb), - SH_PFC_PIN_GROUP(vin3_clk), +static const struct { + struct sh_pfc_pin_group common[289]; + struct sh_pfc_pin_group automotive[1]; +} pinmux_groups = { + .common = { + SH_PFC_PIN_GROUP(audio_clk_a), + SH_PFC_PIN_GROUP(audio_clk_b), + SH_PFC_PIN_GROUP(audio_clk_c), + SH_PFC_PIN_GROUP(audio_clkout), + SH_PFC_PIN_GROUP(audio_clkout_b), + SH_PFC_PIN_GROUP(audio_clkout_c), + SH_PFC_PIN_GROUP(audio_clkout_d), + SH_PFC_PIN_GROUP(avb_link), + SH_PFC_PIN_GROUP(avb_magic), + SH_PFC_PIN_GROUP(avb_phy_int), + SH_PFC_PIN_GROUP(avb_mdio), + SH_PFC_PIN_GROUP(avb_mii), + SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(du_rgb666), + SH_PFC_PIN_GROUP(du_rgb888), + SH_PFC_PIN_GROUP(du_clk_out_0), + SH_PFC_PIN_GROUP(du_clk_out_1), + SH_PFC_PIN_GROUP(du_sync_0), + SH_PFC_PIN_GROUP(du_sync_1), + SH_PFC_PIN_GROUP(du_cde), + SH_PFC_PIN_GROUP(du0_clk_in), + SH_PFC_PIN_GROUP(du1_clk_in), + SH_PFC_PIN_GROUP(du2_clk_in), + SH_PFC_PIN_GROUP(eth_link), + SH_PFC_PIN_GROUP(eth_magic), + SH_PFC_PIN_GROUP(eth_mdio), + SH_PFC_PIN_GROUP(eth_rmii), + SH_PFC_PIN_GROUP(hscif0_data), + SH_PFC_PIN_GROUP(hscif0_clk), + SH_PFC_PIN_GROUP(hscif0_ctrl), + SH_PFC_PIN_GROUP(hscif0_data_b), + SH_PFC_PIN_GROUP(hscif0_ctrl_b), + SH_PFC_PIN_GROUP(hscif0_data_c), + SH_PFC_PIN_GROUP(hscif0_ctrl_c), + SH_PFC_PIN_GROUP(hscif0_data_d), + SH_PFC_PIN_GROUP(hscif0_ctrl_d), + SH_PFC_PIN_GROUP(hscif0_data_e), + SH_PFC_PIN_GROUP(hscif0_ctrl_e), + SH_PFC_PIN_GROUP(hscif0_data_f), + SH_PFC_PIN_GROUP(hscif0_ctrl_f), + SH_PFC_PIN_GROUP(hscif1_data), + SH_PFC_PIN_GROUP(hscif1_clk), + SH_PFC_PIN_GROUP(hscif1_ctrl), + SH_PFC_PIN_GROUP(hscif1_data_b), + SH_PFC_PIN_GROUP(hscif1_clk_b), + SH_PFC_PIN_GROUP(hscif1_ctrl_b), + SH_PFC_PIN_GROUP(i2c0), + SH_PFC_PIN_GROUP(i2c1), + SH_PFC_PIN_GROUP(i2c1_b), + SH_PFC_PIN_GROUP(i2c1_c), + SH_PFC_PIN_GROUP(i2c2), + SH_PFC_PIN_GROUP(i2c2_b), + SH_PFC_PIN_GROUP(i2c2_c), + SH_PFC_PIN_GROUP(i2c2_d), + SH_PFC_PIN_GROUP(i2c2_e), + SH_PFC_PIN_GROUP(i2c3), + SH_PFC_PIN_GROUP(iic0), + SH_PFC_PIN_GROUP(iic1), + SH_PFC_PIN_GROUP(iic1_b), + SH_PFC_PIN_GROUP(iic1_c), + SH_PFC_PIN_GROUP(iic2), + SH_PFC_PIN_GROUP(iic2_b), + SH_PFC_PIN_GROUP(iic2_c), + SH_PFC_PIN_GROUP(iic2_d), + SH_PFC_PIN_GROUP(iic2_e), + SH_PFC_PIN_GROUP(iic3), + SH_PFC_PIN_GROUP(intc_irq0), + SH_PFC_PIN_GROUP(intc_irq1), + SH_PFC_PIN_GROUP(intc_irq2), + SH_PFC_PIN_GROUP(intc_irq3), + SH_PFC_PIN_GROUP(mmc0_data1), + SH_PFC_PIN_GROUP(mmc0_data4), + SH_PFC_PIN_GROUP(mmc0_data8), + SH_PFC_PIN_GROUP(mmc0_ctrl), + SH_PFC_PIN_GROUP(mmc1_data1), + SH_PFC_PIN_GROUP(mmc1_data4), + SH_PFC_PIN_GROUP(mmc1_data8), + SH_PFC_PIN_GROUP(mmc1_ctrl), + SH_PFC_PIN_GROUP(msiof0_clk), + SH_PFC_PIN_GROUP(msiof0_sync), + SH_PFC_PIN_GROUP(msiof0_ss1), + SH_PFC_PIN_GROUP(msiof0_ss2), + SH_PFC_PIN_GROUP(msiof0_rx), + SH_PFC_PIN_GROUP(msiof0_tx), + SH_PFC_PIN_GROUP(msiof0_clk_b), + SH_PFC_PIN_GROUP(msiof0_ss1_b), + SH_PFC_PIN_GROUP(msiof0_ss2_b), + SH_PFC_PIN_GROUP(msiof0_rx_b), + SH_PFC_PIN_GROUP(msiof0_tx_b), + SH_PFC_PIN_GROUP(msiof1_clk), + SH_PFC_PIN_GROUP(msiof1_sync), + SH_PFC_PIN_GROUP(msiof1_ss1), + SH_PFC_PIN_GROUP(msiof1_ss2), + SH_PFC_PIN_GROUP(msiof1_rx), + SH_PFC_PIN_GROUP(msiof1_tx), + SH_PFC_PIN_GROUP(msiof1_clk_b), + SH_PFC_PIN_GROUP(msiof1_ss1_b), + SH_PFC_PIN_GROUP(msiof1_ss2_b), + SH_PFC_PIN_GROUP(msiof1_rx_b), + SH_PFC_PIN_GROUP(msiof1_tx_b), + SH_PFC_PIN_GROUP(msiof2_clk), + SH_PFC_PIN_GROUP(msiof2_sync), + SH_PFC_PIN_GROUP(msiof2_ss1), + SH_PFC_PIN_GROUP(msiof2_ss2), + SH_PFC_PIN_GROUP(msiof2_rx), + SH_PFC_PIN_GROUP(msiof2_tx), + SH_PFC_PIN_GROUP(msiof3_clk), + SH_PFC_PIN_GROUP(msiof3_sync), + SH_PFC_PIN_GROUP(msiof3_ss1), + SH_PFC_PIN_GROUP(msiof3_ss2), + SH_PFC_PIN_GROUP(msiof3_rx), + SH_PFC_PIN_GROUP(msiof3_tx), + SH_PFC_PIN_GROUP(msiof3_clk_b), + SH_PFC_PIN_GROUP(msiof3_sync_b), + SH_PFC_PIN_GROUP(msiof3_rx_b), + SH_PFC_PIN_GROUP(msiof3_tx_b), + SH_PFC_PIN_GROUP(pwm0), + SH_PFC_PIN_GROUP(pwm0_b), + SH_PFC_PIN_GROUP(pwm1), + SH_PFC_PIN_GROUP(pwm1_b), + SH_PFC_PIN_GROUP(pwm2), + SH_PFC_PIN_GROUP(pwm3), + SH_PFC_PIN_GROUP(pwm4), + SH_PFC_PIN_GROUP(pwm5), + SH_PFC_PIN_GROUP(pwm6), + SH_PFC_PIN_GROUP(qspi_ctrl), + SH_PFC_PIN_GROUP(qspi_data2), + SH_PFC_PIN_GROUP(qspi_data4), + SH_PFC_PIN_GROUP(scif0_data), + SH_PFC_PIN_GROUP(scif0_clk), + SH_PFC_PIN_GROUP(scif0_ctrl), + SH_PFC_PIN_GROUP(scif0_data_b), + SH_PFC_PIN_GROUP(scif1_data), + SH_PFC_PIN_GROUP(scif1_clk), + SH_PFC_PIN_GROUP(scif1_ctrl), + SH_PFC_PIN_GROUP(scif1_data_b), + SH_PFC_PIN_GROUP(scif1_data_c), + SH_PFC_PIN_GROUP(scif1_data_d), + SH_PFC_PIN_GROUP(scif1_clk_d), + SH_PFC_PIN_GROUP(scif1_data_e), + SH_PFC_PIN_GROUP(scif1_clk_e), + SH_PFC_PIN_GROUP(scif2_data), + SH_PFC_PIN_GROUP(scif2_clk), + SH_PFC_PIN_GROUP(scif2_data_b), + SH_PFC_PIN_GROUP(scifa0_data), + SH_PFC_PIN_GROUP(scifa0_clk), + SH_PFC_PIN_GROUP(scifa0_ctrl), + SH_PFC_PIN_GROUP(scifa0_data_b), + SH_PFC_PIN_GROUP(scifa0_clk_b), + SH_PFC_PIN_GROUP(scifa0_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data), + SH_PFC_PIN_GROUP(scifa1_clk), + SH_PFC_PIN_GROUP(scifa1_ctrl), + SH_PFC_PIN_GROUP(scifa1_data_b), + SH_PFC_PIN_GROUP(scifa1_clk_b), + SH_PFC_PIN_GROUP(scifa1_ctrl_b), + SH_PFC_PIN_GROUP(scifa1_data_c), + SH_PFC_PIN_GROUP(scifa1_clk_c), + SH_PFC_PIN_GROUP(scifa1_ctrl_c), + SH_PFC_PIN_GROUP(scifa1_data_d), + SH_PFC_PIN_GROUP(scifa1_clk_d), + SH_PFC_PIN_GROUP(scifa1_ctrl_d), + SH_PFC_PIN_GROUP(scifa2_data), + SH_PFC_PIN_GROUP(scifa2_clk), + SH_PFC_PIN_GROUP(scifa2_ctrl), + SH_PFC_PIN_GROUP(scifa2_data_b), + SH_PFC_PIN_GROUP(scifa2_data_c), + SH_PFC_PIN_GROUP(scifa2_clk_c), + SH_PFC_PIN_GROUP(scifb0_data), + SH_PFC_PIN_GROUP(scifb0_clk), + SH_PFC_PIN_GROUP(scifb0_ctrl), + SH_PFC_PIN_GROUP(scifb0_data_b), + SH_PFC_PIN_GROUP(scifb0_clk_b), + SH_PFC_PIN_GROUP(scifb0_ctrl_b), + SH_PFC_PIN_GROUP(scifb0_data_c), + SH_PFC_PIN_GROUP(scifb1_data), + SH_PFC_PIN_GROUP(scifb1_clk), + SH_PFC_PIN_GROUP(scifb1_ctrl), + SH_PFC_PIN_GROUP(scifb1_data_b), + SH_PFC_PIN_GROUP(scifb1_clk_b), + SH_PFC_PIN_GROUP(scifb1_ctrl_b), + SH_PFC_PIN_GROUP(scifb1_data_c), + SH_PFC_PIN_GROUP(scifb1_data_d), + SH_PFC_PIN_GROUP(scifb1_data_e), + SH_PFC_PIN_GROUP(scifb1_clk_e), + SH_PFC_PIN_GROUP(scifb1_data_f), + SH_PFC_PIN_GROUP(scifb1_data_g), + SH_PFC_PIN_GROUP(scifb1_clk_g), + SH_PFC_PIN_GROUP(scifb2_data), + SH_PFC_PIN_GROUP(scifb2_clk), + SH_PFC_PIN_GROUP(scifb2_ctrl), + SH_PFC_PIN_GROUP(scifb2_data_b), + SH_PFC_PIN_GROUP(scifb2_clk_b), + SH_PFC_PIN_GROUP(scifb2_ctrl_b), + SH_PFC_PIN_GROUP(scifb2_data_c), + SH_PFC_PIN_GROUP(scif_clk), + SH_PFC_PIN_GROUP(scif_clk_b), + SH_PFC_PIN_GROUP(sdhi0_data1), + SH_PFC_PIN_GROUP(sdhi0_data4), + SH_PFC_PIN_GROUP(sdhi0_ctrl), + SH_PFC_PIN_GROUP(sdhi0_cd), + SH_PFC_PIN_GROUP(sdhi0_wp), + SH_PFC_PIN_GROUP(sdhi1_data1), + SH_PFC_PIN_GROUP(sdhi1_data4), + SH_PFC_PIN_GROUP(sdhi1_ctrl), + SH_PFC_PIN_GROUP(sdhi1_cd), + SH_PFC_PIN_GROUP(sdhi1_wp), + SH_PFC_PIN_GROUP(sdhi2_data1), + SH_PFC_PIN_GROUP(sdhi2_data4), + SH_PFC_PIN_GROUP(sdhi2_ctrl), + SH_PFC_PIN_GROUP(sdhi2_cd), + SH_PFC_PIN_GROUP(sdhi2_wp), + SH_PFC_PIN_GROUP(sdhi3_data1), + SH_PFC_PIN_GROUP(sdhi3_data4), + SH_PFC_PIN_GROUP(sdhi3_ctrl), + SH_PFC_PIN_GROUP(sdhi3_cd), + SH_PFC_PIN_GROUP(sdhi3_wp), + SH_PFC_PIN_GROUP(ssi0_data), + SH_PFC_PIN_GROUP(ssi0129_ctrl), + SH_PFC_PIN_GROUP(ssi1_data), + SH_PFC_PIN_GROUP(ssi1_ctrl), + SH_PFC_PIN_GROUP(ssi2_data), + SH_PFC_PIN_GROUP(ssi2_ctrl), + SH_PFC_PIN_GROUP(ssi3_data), + SH_PFC_PIN_GROUP(ssi34_ctrl), + SH_PFC_PIN_GROUP(ssi4_data), + SH_PFC_PIN_GROUP(ssi4_ctrl), + SH_PFC_PIN_GROUP(ssi5), + SH_PFC_PIN_GROUP(ssi5_b), + SH_PFC_PIN_GROUP(ssi5_c), + SH_PFC_PIN_GROUP(ssi6), + SH_PFC_PIN_GROUP(ssi6_b), + SH_PFC_PIN_GROUP(ssi7_data), + SH_PFC_PIN_GROUP(ssi7_b_data), + SH_PFC_PIN_GROUP(ssi7_c_data), + SH_PFC_PIN_GROUP(ssi78_ctrl), + SH_PFC_PIN_GROUP(ssi78_b_ctrl), + SH_PFC_PIN_GROUP(ssi78_c_ctrl), + SH_PFC_PIN_GROUP(ssi8_data), + SH_PFC_PIN_GROUP(ssi8_b_data), + SH_PFC_PIN_GROUP(ssi8_c_data), + SH_PFC_PIN_GROUP(ssi9_data), + SH_PFC_PIN_GROUP(ssi9_ctrl), + SH_PFC_PIN_GROUP(tpu0_to0), + SH_PFC_PIN_GROUP(tpu0_to1), + SH_PFC_PIN_GROUP(tpu0_to2), + SH_PFC_PIN_GROUP(tpu0_to3), + SH_PFC_PIN_GROUP(usb0), + SH_PFC_PIN_GROUP(usb0_ovc_vbus), + SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb2), + VIN_DATA_PIN_GROUP(vin0_data, 24), + VIN_DATA_PIN_GROUP(vin0_data, 20), + SH_PFC_PIN_GROUP(vin0_data18), + VIN_DATA_PIN_GROUP(vin0_data, 16), + VIN_DATA_PIN_GROUP(vin0_data, 12), + VIN_DATA_PIN_GROUP(vin0_data, 10), + VIN_DATA_PIN_GROUP(vin0_data, 8), + VIN_DATA_PIN_GROUP(vin0_data, 4), + SH_PFC_PIN_GROUP(vin0_sync), + SH_PFC_PIN_GROUP(vin0_field), + SH_PFC_PIN_GROUP(vin0_clkenb), + SH_PFC_PIN_GROUP(vin0_clk), + VIN_DATA_PIN_GROUP(vin1_data, 24), + VIN_DATA_PIN_GROUP(vin1_data, 20), + SH_PFC_PIN_GROUP(vin1_data18), + VIN_DATA_PIN_GROUP(vin1_data, 16), + VIN_DATA_PIN_GROUP(vin1_data, 12), + VIN_DATA_PIN_GROUP(vin1_data, 10), + VIN_DATA_PIN_GROUP(vin1_data, 8), + VIN_DATA_PIN_GROUP(vin1_data, 4), + SH_PFC_PIN_GROUP(vin1_sync), + SH_PFC_PIN_GROUP(vin1_field), + SH_PFC_PIN_GROUP(vin1_clkenb), + SH_PFC_PIN_GROUP(vin1_clk), + VIN_DATA_PIN_GROUP(vin2_data, 24), + SH_PFC_PIN_GROUP(vin2_data18), + VIN_DATA_PIN_GROUP(vin2_data, 16), + VIN_DATA_PIN_GROUP(vin2_data, 8), + VIN_DATA_PIN_GROUP(vin2_data, 4), + SH_PFC_PIN_GROUP(vin2_sync), + SH_PFC_PIN_GROUP(vin2_field), + SH_PFC_PIN_GROUP(vin2_clkenb), + SH_PFC_PIN_GROUP(vin2_clk), + SH_PFC_PIN_GROUP(vin3_data8), + SH_PFC_PIN_GROUP(vin3_sync), + SH_PFC_PIN_GROUP(vin3_field), + SH_PFC_PIN_GROUP(vin3_clkenb), + SH_PFC_PIN_GROUP(vin3_clk), + }, + .automotive = { + SH_PFC_PIN_GROUP(mlb_3pin), + } }; static const char * const audio_clk_groups[] = { @@ -4689,63 +4696,70 @@ static const char * const vin3_groups[] = { "vin3_clk", }; -static const struct sh_pfc_function pinmux_functions[] = { - SH_PFC_FUNCTION(audio_clk), - SH_PFC_FUNCTION(avb), - SH_PFC_FUNCTION(du), - SH_PFC_FUNCTION(du0), - SH_PFC_FUNCTION(du1), - SH_PFC_FUNCTION(du2), - SH_PFC_FUNCTION(eth), - SH_PFC_FUNCTION(hscif0), - SH_PFC_FUNCTION(hscif1), - SH_PFC_FUNCTION(i2c0), - SH_PFC_FUNCTION(i2c1), - SH_PFC_FUNCTION(i2c2), - SH_PFC_FUNCTION(i2c3), - SH_PFC_FUNCTION(iic0), - SH_PFC_FUNCTION(iic1), - SH_PFC_FUNCTION(iic2), - SH_PFC_FUNCTION(iic3), - SH_PFC_FUNCTION(intc), - SH_PFC_FUNCTION(mlb), - SH_PFC_FUNCTION(mmc0), - SH_PFC_FUNCTION(mmc1), - SH_PFC_FUNCTION(msiof0), - SH_PFC_FUNCTION(msiof1), - SH_PFC_FUNCTION(msiof2), - SH_PFC_FUNCTION(msiof3), - SH_PFC_FUNCTION(pwm0), - SH_PFC_FUNCTION(pwm1), - SH_PFC_FUNCTION(pwm2), - SH_PFC_FUNCTION(pwm3), - SH_PFC_FUNCTION(pwm4), - SH_PFC_FUNCTION(pwm5), - SH_PFC_FUNCTION(pwm6), - SH_PFC_FUNCTION(qspi), - SH_PFC_FUNCTION(scif0), - SH_PFC_FUNCTION(scif1), - SH_PFC_FUNCTION(scif2), - SH_PFC_FUNCTION(scifa0), - SH_PFC_FUNCTION(scifa1), - SH_PFC_FUNCTION(scifa2), - SH_PFC_FUNCTION(scifb0), - SH_PFC_FUNCTION(scifb1), - SH_PFC_FUNCTION(scifb2), - SH_PFC_FUNCTION(scif_clk), - SH_PFC_FUNCTION(sdhi0), - SH_PFC_FUNCTION(sdhi1), - SH_PFC_FUNCTION(sdhi2), - SH_PFC_FUNCTION(sdhi3), - SH_PFC_FUNCTION(ssi), - SH_PFC_FUNCTION(tpu0), - SH_PFC_FUNCTION(usb0), - SH_PFC_FUNCTION(usb1), - SH_PFC_FUNCTION(usb2), - SH_PFC_FUNCTION(vin0), - SH_PFC_FUNCTION(vin1), - SH_PFC_FUNCTION(vin2), - SH_PFC_FUNCTION(vin3), +static const struct { + struct sh_pfc_function common[55]; + struct sh_pfc_function automotive[1]; +} pinmux_functions = { + .common = { + SH_PFC_FUNCTION(audio_clk), + SH_PFC_FUNCTION(avb), + SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(du0), + SH_PFC_FUNCTION(du1), + SH_PFC_FUNCTION(du2), + SH_PFC_FUNCTION(eth), + SH_PFC_FUNCTION(hscif0), + SH_PFC_FUNCTION(hscif1), + SH_PFC_FUNCTION(i2c0), + SH_PFC_FUNCTION(i2c1), + SH_PFC_FUNCTION(i2c2), + SH_PFC_FUNCTION(i2c3), + SH_PFC_FUNCTION(iic0), + SH_PFC_FUNCTION(iic1), + SH_PFC_FUNCTION(iic2), + SH_PFC_FUNCTION(iic3), + SH_PFC_FUNCTION(intc), + SH_PFC_FUNCTION(mmc0), + SH_PFC_FUNCTION(mmc1), + SH_PFC_FUNCTION(msiof0), + SH_PFC_FUNCTION(msiof1), + SH_PFC_FUNCTION(msiof2), + SH_PFC_FUNCTION(msiof3), + SH_PFC_FUNCTION(pwm0), + SH_PFC_FUNCTION(pwm1), + SH_PFC_FUNCTION(pwm2), + SH_PFC_FUNCTION(pwm3), + SH_PFC_FUNCTION(pwm4), + SH_PFC_FUNCTION(pwm5), + SH_PFC_FUNCTION(pwm6), + SH_PFC_FUNCTION(qspi), + SH_PFC_FUNCTION(scif0), + SH_PFC_FUNCTION(scif1), + SH_PFC_FUNCTION(scif2), + SH_PFC_FUNCTION(scifa0), + SH_PFC_FUNCTION(scifa1), + SH_PFC_FUNCTION(scifa2), + SH_PFC_FUNCTION(scifb0), + SH_PFC_FUNCTION(scifb1), + SH_PFC_FUNCTION(scifb2), + SH_PFC_FUNCTION(scif_clk), + SH_PFC_FUNCTION(sdhi0), + SH_PFC_FUNCTION(sdhi1), + SH_PFC_FUNCTION(sdhi2), + SH_PFC_FUNCTION(sdhi3), + SH_PFC_FUNCTION(ssi), + SH_PFC_FUNCTION(tpu0), + SH_PFC_FUNCTION(usb0), + SH_PFC_FUNCTION(usb1), + SH_PFC_FUNCTION(usb2), + SH_PFC_FUNCTION(vin0), + SH_PFC_FUNCTION(vin1), + SH_PFC_FUNCTION(vin2), + SH_PFC_FUNCTION(vin3), + }, + .automotive = { + SH_PFC_FUNCTION(mlb), + } }; static const struct pinmux_cfg_reg pinmux_config_regs[] = { @@ -5736,6 +5750,29 @@ static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = { .pin_to_pocctrl = r8a7790_pin_to_pocctrl, }; +#ifdef CONFIG_PINCTRL_PFC_R8A7742 +const struct sh_pfc_soc_info r8a7742_pinmux_info = { + .name = "r8a77420_pfc", + .ops = &r8a7790_pinmux_ops, + .unlock_reg = 0xe6060000, /* PMMR */ + + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .pins = pinmux_pins, + .nr_pins = ARRAY_SIZE(pinmux_pins), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common), + + .cfg_regs = pinmux_config_regs, + + .pinmux_data = pinmux_data, + .pinmux_data_size = ARRAY_SIZE(pinmux_data), +}; +#endif + +#ifdef CONFIG_PINCTRL_PFC_R8A7790 const struct sh_pfc_soc_info r8a7790_pinmux_info = { .name = "r8a77900_pfc", .ops = &r8a7790_pinmux_ops, @@ -5745,13 +5782,16 @@ const struct sh_pfc_soc_info r8a7790_pinmux_info = { .pins = pinmux_pins, .nr_pins = ARRAY_SIZE(pinmux_pins), - .groups = pinmux_groups, - .nr_groups = ARRAY_SIZE(pinmux_groups), - .functions = pinmux_functions, - .nr_functions = ARRAY_SIZE(pinmux_functions), + .groups = pinmux_groups.common, + .nr_groups = ARRAY_SIZE(pinmux_groups.common) + + ARRAY_SIZE(pinmux_groups.automotive), + .functions = pinmux_functions.common, + .nr_functions = ARRAY_SIZE(pinmux_functions.common) + + ARRAY_SIZE(pinmux_functions.automotive), .cfg_regs = pinmux_config_regs, .pinmux_data = pinmux_data, .pinmux_data_size = ARRAY_SIZE(pinmux_data), }; +#endif diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h index d57e633e99c0..0f013827baf9 100644 --- a/drivers/pinctrl/sh-pfc/sh_pfc.h +++ b/drivers/pinctrl/sh-pfc/sh_pfc.h @@ -304,6 +304,7 @@ struct sh_pfc_soc_info { extern const struct sh_pfc_soc_info emev2_pinmux_info; extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; extern const struct sh_pfc_soc_info r8a7740_pinmux_info; +extern const struct sh_pfc_soc_info r8a7742_pinmux_info; extern const struct sh_pfc_soc_info r8a7743_pinmux_info; extern const struct sh_pfc_soc_info r8a7744_pinmux_info; extern const struct sh_pfc_soc_info r8a7745_pinmux_info; From 7227797a4e66a1b70a3745ad56d36937732c625c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 May 2020 09:45:16 +0200 Subject: [PATCH 51/72] pinctrl: rza1: Fix flag name in comment rza1_swio_pin relates to the swio flag instead of the bidir flag. Signed-off-by: Geert Uytterhoeven Acked-by: Jacopo Mondi Link: https://lore.kernel.org/r/20200507074516.29903-1-geert+renesas@glider.be --- drivers/pinctrl/pinctrl-rza1.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/pinctrl-rza1.c index ff4a7fb518bb..38a14bbced5f 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/pinctrl-rza1.c @@ -93,7 +93,7 @@ struct rza1_bidir_entry { }; /** - * rza1_swio_pin - describe a single pin that needs bidir flag applied. + * rza1_swio_pin - describe a single pin that needs swio flag applied. */ struct rza1_swio_pin { u16 pin: 4; From 80691a8ac7a43434ed2ecff15d560a9e5d90f613 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 May 2020 13:36:25 +0200 Subject: [PATCH 52/72] pinctrl: equilibrium: Add architecture dependency The Equilibrium pin controller is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PINCTRL_EQUILIBRIUM config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200507113626.24026-2-geert+renesas@glider.be Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f646f070d98f..85030123a17e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -442,6 +442,7 @@ config PINCTRL_TB10X config PINCTRL_EQUILIBRIUM tristate "Generic pinctrl and GPIO driver for Intel Lightning Mountain SoC" depends on OF && HAS_IOMEM + depends on X86 || COMPILE_TEST select PINMUX select PINCONF select GPIOLIB From 47fa5c971bbce2d97efb82da709deff60aaf7b3d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 7 May 2020 13:37:51 +0200 Subject: [PATCH 53/72] pinctrl: amd: Add ACPI dependency Currently the AMD pin controller driver supports ACPI platform only. Make the PINCTRL_AMD config symbol depend on ACPI, to avoid asking the user about it when configuring a kernel without ACPI support. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200507113751.24213-1-geert+renesas@glider.be Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 85030123a17e..ae4922b07d1d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -95,6 +95,7 @@ config PINCTRL_AT91PIO4 config PINCTRL_AMD tristate "AMD GPIO pin control" depends on HAS_IOMEM + depends on ACPI || COMPILE_TEST select GPIOLIB select GPIOLIB_IRQCHIP select PINMUX From 5d590738521e25b183172c32aab6ee71b9366dca Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 12 May 2020 22:35:23 +0200 Subject: [PATCH 54/72] dt-bindings: pinctrl: rockchip: update example The Rockchip dtsi and dts files have been bulk-converted for the remaining raw gpio numbers into their descriptive counterparts and also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x mappings, so update the example as well. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20200512203524.7317-2-jbx6244@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt index 2113cfaa26e6..d3eae61a340d 100644 --- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt @@ -110,8 +110,8 @@ pinctrl@20008000 { uart2 { uart2_xfer: uart2-xfer { - rockchip,pins = , - ; + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, + <1 RK_PB1 1 &pcfg_pull_default>; }; }; }; From 550713e33f4338c8596776828a936fd1e3bf35de Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 13 May 2020 14:55:19 +0200 Subject: [PATCH 55/72] pinctrl: ocelot: Always register GPIO driver This fixes the situation where the GPIO controller is not used as an interrupt controller as well. Previously, the driver would silently fail to register even the GPIO's. With this change, the driver will only register as an interrupt controller if a parent interrupt is provided. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200513125532.24585-2-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index ed8eac6c1494..d4ac65b1efc0 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -751,21 +751,21 @@ static int ocelot_gpiochip_register(struct platform_device *pdev, gc->of_node = info->dev->of_node; gc->label = "ocelot-gpio"; - irq = irq_of_parse_and_map(pdev->dev.of_node, 0); - if (irq <= 0) - return irq; - - girq = &gc->irq; - girq->chip = &ocelot_irqchip; - girq->parent_handler = ocelot_irq_handler; - girq->num_parents = 1; - girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), - GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; - girq->parents[0] = irq; - girq->default_type = IRQ_TYPE_NONE; - girq->handler = handle_edge_irq; + irq = irq_of_parse_and_map(gc->of_node, 0); + if (irq) { + girq = &gc->irq; + girq->chip = &ocelot_irqchip; + girq->parent_handler = ocelot_irq_handler; + girq->num_parents = 1; + girq->parents = devm_kcalloc(&pdev->dev, 1, + sizeof(*girq->parents), + GFP_KERNEL); + if (!girq->parents) + return -ENOMEM; + girq->parents[0] = irq; + girq->default_type = IRQ_TYPE_NONE; + girq->handler = handle_edge_irq; + } ret = devm_gpiochip_add_data(&pdev->dev, gc, info); if (ret) From edc7254664abdcd087e49849f0ba6489c1f19b49 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 13 May 2020 14:55:20 +0200 Subject: [PATCH 56/72] pinctrl: ocelot: Remove instance number from pin functions This patch removes the instance number from the "miim", "reco_clk" and "sfp" pin function. The change needed is to prepare the driver for adding new platforms with more of these instances. The instance number is also redundant, as this is implicit for each pin. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200513125532.24585-3-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 94 ++++++++++---------------------- 1 file changed, 30 insertions(+), 64 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index d4ac65b1efc0..375f3ea3b80c 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -46,32 +46,15 @@ enum { FUNC_IRQ0_OUT, FUNC_IRQ1_IN, FUNC_IRQ1_OUT, - FUNC_MIIM1, - FUNC_MIIM2, + FUNC_MIIM, FUNC_PCI_WAKE, FUNC_PTP0, FUNC_PTP1, FUNC_PTP2, FUNC_PTP3, FUNC_PWM, - FUNC_RECO_CLK0, - FUNC_RECO_CLK1, - FUNC_SFP0, - FUNC_SFP1, - FUNC_SFP2, - FUNC_SFP3, - FUNC_SFP4, - FUNC_SFP5, - FUNC_SFP6, - FUNC_SFP7, - FUNC_SFP8, - FUNC_SFP9, - FUNC_SFP10, - FUNC_SFP11, - FUNC_SFP12, - FUNC_SFP13, - FUNC_SFP14, - FUNC_SFP15, + FUNC_RECO_CLK, + FUNC_SFP, FUNC_SG0, FUNC_SG1, FUNC_SG2, @@ -92,32 +75,15 @@ static const char *const ocelot_function_names[] = { [FUNC_IRQ0_OUT] = "irq0_out", [FUNC_IRQ1_IN] = "irq1_in", [FUNC_IRQ1_OUT] = "irq1_out", - [FUNC_MIIM1] = "miim1", - [FUNC_MIIM2] = "miim2", + [FUNC_MIIM] = "miim", [FUNC_PCI_WAKE] = "pci_wake", [FUNC_PTP0] = "ptp0", [FUNC_PTP1] = "ptp1", [FUNC_PTP2] = "ptp2", [FUNC_PTP3] = "ptp3", [FUNC_PWM] = "pwm", - [FUNC_RECO_CLK0] = "reco_clk0", - [FUNC_RECO_CLK1] = "reco_clk1", - [FUNC_SFP0] = "sfp0", - [FUNC_SFP1] = "sfp1", - [FUNC_SFP2] = "sfp2", - [FUNC_SFP3] = "sfp3", - [FUNC_SFP4] = "sfp4", - [FUNC_SFP5] = "sfp5", - [FUNC_SFP6] = "sfp6", - [FUNC_SFP7] = "sfp7", - [FUNC_SFP8] = "sfp8", - [FUNC_SFP9] = "sfp9", - [FUNC_SFP10] = "sfp10", - [FUNC_SFP11] = "sfp11", - [FUNC_SFP12] = "sfp12", - [FUNC_SFP13] = "sfp13", - [FUNC_SFP14] = "sfp14", - [FUNC_SFP15] = "sfp15", + [FUNC_RECO_CLK] = "reco_clk", + [FUNC_SFP] = "sfp", [FUNC_SG0] = "sg0", [FUNC_SG1] = "sg1", [FUNC_SG2] = "sg2", @@ -168,18 +134,18 @@ OCELOT_P(6, UART, TWI_SCL_M, NONE); OCELOT_P(7, UART, TWI_SCL_M, NONE); OCELOT_P(8, SI, TWI_SCL_M, IRQ0_OUT); OCELOT_P(9, SI, TWI_SCL_M, IRQ1_OUT); -OCELOT_P(10, PTP2, TWI_SCL_M, SFP0); -OCELOT_P(11, PTP3, TWI_SCL_M, SFP1); -OCELOT_P(12, UART2, TWI_SCL_M, SFP2); -OCELOT_P(13, UART2, TWI_SCL_M, SFP3); -OCELOT_P(14, MIIM1, TWI_SCL_M, SFP4); -OCELOT_P(15, MIIM1, TWI_SCL_M, SFP5); +OCELOT_P(10, PTP2, TWI_SCL_M, SFP); +OCELOT_P(11, PTP3, TWI_SCL_M, SFP); +OCELOT_P(12, UART2, TWI_SCL_M, SFP); +OCELOT_P(13, UART2, TWI_SCL_M, SFP); +OCELOT_P(14, MIIM, TWI_SCL_M, SFP); +OCELOT_P(15, MIIM, TWI_SCL_M, SFP); OCELOT_P(16, TWI, NONE, SI); OCELOT_P(17, TWI, TWI_SCL_M, SI); OCELOT_P(18, PTP0, TWI_SCL_M, NONE); OCELOT_P(19, PTP1, TWI_SCL_M, NONE); -OCELOT_P(20, RECO_CLK0, TACHO, NONE); -OCELOT_P(21, RECO_CLK1, PWM, NONE); +OCELOT_P(20, RECO_CLK, TACHO, TWI_SCL_M); +OCELOT_P(21, RECO_CLK, PWM, TWI_SCL_M); #define OCELOT_PIN(n) { \ .number = n, \ @@ -264,22 +230,22 @@ JAGUAR2_P(40, NONE, TWI_SCL_M); JAGUAR2_P(41, NONE, TWI_SCL_M); JAGUAR2_P(42, NONE, TWI_SCL_M); JAGUAR2_P(43, NONE, TWI_SCL_M); -JAGUAR2_P(44, NONE, SFP8); -JAGUAR2_P(45, NONE, SFP9); -JAGUAR2_P(46, NONE, SFP10); -JAGUAR2_P(47, NONE, SFP11); -JAGUAR2_P(48, SFP0, NONE); -JAGUAR2_P(49, SFP1, SI); -JAGUAR2_P(50, SFP2, SI); -JAGUAR2_P(51, SFP3, SI); -JAGUAR2_P(52, SFP4, NONE); -JAGUAR2_P(53, SFP5, NONE); -JAGUAR2_P(54, SFP6, NONE); -JAGUAR2_P(55, SFP7, NONE); -JAGUAR2_P(56, MIIM1, SFP12); -JAGUAR2_P(57, MIIM1, SFP13); -JAGUAR2_P(58, MIIM2, SFP14); -JAGUAR2_P(59, MIIM2, SFP15); +JAGUAR2_P(44, NONE, SFP); +JAGUAR2_P(45, NONE, SFP); +JAGUAR2_P(46, NONE, SFP); +JAGUAR2_P(47, NONE, SFP); +JAGUAR2_P(48, SFP, NONE); +JAGUAR2_P(49, SFP, SI); +JAGUAR2_P(50, SFP, SI); +JAGUAR2_P(51, SFP, SI); +JAGUAR2_P(52, SFP, NONE); +JAGUAR2_P(53, SFP, NONE); +JAGUAR2_P(54, SFP, NONE); +JAGUAR2_P(55, SFP, NONE); +JAGUAR2_P(56, MIIM, SFP); +JAGUAR2_P(57, MIIM, SFP); +JAGUAR2_P(58, MIIM, SFP); +JAGUAR2_P(59, MIIM, SFP); JAGUAR2_P(60, NONE, NONE); JAGUAR2_P(61, NONE, NONE); JAGUAR2_P(62, NONE, NONE); From 0b47afc65453a70bc521e251138418056f65793f Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 13 May 2020 14:55:21 +0200 Subject: [PATCH 57/72] pinctrl: ocelot: Fix GPIO interrupt decoding on Jaguar2 This fixes a problem with using the GPIO as an interrupt on Jaguar2 (and similar), as the register layout of the platforms with 64 GPIO's are pairwise, such that the original offset must be multiplied with the platform stride. Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support. Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200513125532.24585-4-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- drivers/pinctrl/pinctrl-ocelot.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 375f3ea3b80c..95c225bc7572 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -680,11 +680,12 @@ static void ocelot_irq_handler(struct irq_desc *desc) struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; unsigned int reg = 0, irq, i; unsigned long irqs; for (i = 0; i < info->stride; i++) { - regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); + regmap_read(info->map, id_reg + 4 * i, ®); if (!reg) continue; From e695dea067fca398b7eb0f0977f4692986b483f7 Mon Sep 17 00:00:00 2001 From: Lars Povlsen Date: Wed, 13 May 2020 14:55:25 +0200 Subject: [PATCH 58/72] dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support This adds documentation for the "compatible" value designated for Sparx5 Reviewed-by: Alexandre Belloni Signed-off-by: Lars Povlsen Link: https://lore.kernel.org/r/20200513125532.24585-8-lars.povlsen@microchip.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 32a8a8fa7805..00912449237b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,8 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" or - "mscc,jaguar2-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl", + "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. From dfae0422de12265ae7c9bf57b34990200dea0c83 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 18 May 2020 10:18:36 +0200 Subject: [PATCH 59/72] MAINTAINERS: Renesas Pin Controllers are supported Change "PIN CONTROLLER - RENESAS" section from Maintained to Supported. This brings it in line with my other "+renesas" entries. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200518081836.23890-1-geert+renesas@glider.be --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index edeb025d9187..5a2f604c3b63 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13344,7 +13344,7 @@ F: drivers/pinctrl/qcom/ PIN CONTROLLER - RENESAS M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org -S: Maintained +S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc F: Documentation/devicetree/bindings/pinctrl/renesas,* F: drivers/pinctrl/pinctrl-rz* From b5d9ff10dca49f4d4b7846c3751c6bec50d07375 Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Sat, 23 May 2020 19:45:25 +0800 Subject: [PATCH 60/72] pinctrl: Fix return value about devm_platform_ioremap_resource() When call function devm_platform_ioremap_resource(), we should use IS_ERR() to check the return value and return PTR_ERR() if failed. Fixes: 4b024225c4a8 ("pinctrl: use devm_platform_ioremap_resource() to simplify code") Signed-off-by: Tiezhu Yang Link: https://lore.kernel.org/r/1590234326-2194-1-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm281xx.c | 2 +- drivers/pinctrl/pinctrl-at91-pio4.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c index f690fc5cd688..71e666178300 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm281xx.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c @@ -1406,7 +1406,7 @@ static int __init bcm281xx_pinctrl_probe(struct platform_device *pdev) pdata->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pdata->reg_base)) { dev_err(&pdev->dev, "Failed to ioremap MEM resource\n"); - return -ENODEV; + return PTR_ERR(pdata->reg_base); } /* Initialize the dynamic part of pinctrl_desc */ diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c index 694912409fd9..54222ccddfb1 100644 --- a/drivers/pinctrl/pinctrl-at91-pio4.c +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -1019,7 +1019,7 @@ static int atmel_pinctrl_probe(struct platform_device *pdev) atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(atmel_pioctrl->reg_base)) - return -EINVAL; + return PTR_ERR(atmel_pioctrl->reg_base); atmel_pioctrl->clk = devm_clk_get(dev, NULL); if (IS_ERR(atmel_pioctrl->clk)) { From e682fcc769709e563ab2ebea5a2af62bcbd7f8cc Mon Sep 17 00:00:00 2001 From: Tiezhu Yang Date: Sat, 23 May 2020 19:45:26 +0800 Subject: [PATCH 61/72] pinctrl: at91-pio4: Add COMPILE_TEST support Add COMPILE_TEST support to the AT91 PIO4 pinctrl driver for better compile testing coverage. Signed-off-by: Tiezhu Yang Link: https://lore.kernel.org/r/1590234326-2194-2-git-send-email-yangtiezhu@loongson.cn Signed-off-by: Linus Walleij --- drivers/pinctrl/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ae4922b07d1d..8828613c4e0e 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -82,7 +82,7 @@ config PINCTRL_AT91 config PINCTRL_AT91PIO4 bool "AT91 PIO4 pinctrl driver" depends on OF - depends on ARCH_AT91 + depends on ARCH_AT91 || COMPILE_TEST select PINMUX select GENERIC_PINCONF select GPIOLIB From a45c0ec26d4ae1c8ae679a978fc8b3d35dd836b0 Mon Sep 17 00:00:00 2001 From: Benjamin Gaignard Date: Wed, 13 May 2020 16:59:34 +0200 Subject: [PATCH 62/72] dt-bindings: pinctrl: stm32: Add missing interrupts property Driver use interrupt-parent field so update the bindings to allow it. Signed-off-by: Benjamin Gaignard Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200513145935.22493-15-benjamin.gaignard@st.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml index 46a0478cb924..5abdabafb8a0 100644 --- a/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml @@ -36,6 +36,9 @@ properties: pins-are-numbered: true hwlocks: true + interrupts: + maxItems: 1 + st,syscfg: allOf: - $ref: "/schemas/types.yaml#/definitions/phandle-array" From 879c93f7062ff15c8712c660f24b79796100c10e Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 30 May 2020 17:10:58 -0700 Subject: [PATCH 63/72] dt-bindings: pinctrl: Document 7211 compatible for brcm, bcm2835-gpio.txt Document the brcm,bcm7211-gpio compatible string in the brcm,bcm2835-gpio.txt document. Signed-off-by: Florian Fainelli Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200531001101.24945-2-f.fainelli@gmail.com Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt index 3cab7336a326..dfc67b90591c 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -9,6 +9,7 @@ Required properties: "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl + "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl - reg: Should contain the physical address of the GPIO module's registers. - gpio-controller: Marks the device node as a GPIO controller. - #gpio-cells : Should be two. The first cell is the pin number and the From d4f2b12e6d8e6be860f6b9e23e964cab607987ac Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 30 May 2020 17:10:59 -0700 Subject: [PATCH 64/72] dt-bindings: pinctrl: Document optional BCM7211 wake-up interrupts BCM7211 supports wake-up interrupts in the form of optional interrupt lines, one per bank, plus the "all banks" interrupt line. Signed-off-by: Florian Fainelli Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200531001101.24945-3-f.fainelli@gmail.com Signed-off-by: Linus Walleij --- .../devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt index dfc67b90591c..5682b2010e50 100644 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt @@ -16,7 +16,9 @@ Required properties: second cell is used to specify optional parameters: - bit 0 specifies polarity (0 for normal, 1 for inverted) - interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. + individual bank followed by the "all banks" interrupt. For BCM7211, an + additional set of per-bank interrupt line and an "all banks" wake-up + interrupt may be specified. - interrupt-controller: Marks the device node as an interrupt controller. - #interrupt-cells : Should be 2. The first cell is the GPIO number. From 562c856f96d22ef1204b0a314bc52e85617199b4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 30 May 2020 17:11:00 -0700 Subject: [PATCH 65/72] pinctrl: bcm2835: Match BCM7211 compatible string The BCM7211 SoC uses the same pinconf_ops as the ones defined for the BCM2711 SoC, match the compatible string and use the correct set of options. Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20200531001101.24945-4-f.fainelli@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 06bd2b70af3c..1b00d93aa66e 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1137,6 +1137,10 @@ static const struct of_device_id bcm2835_pinctrl_match[] = { .compatible = "brcm,bcm2711-gpio", .data = &bcm2711_plat_data, }, + { + .compatible = "brcm,bcm7211-gpio", + .data = &bcm2711_plat_data, + }, {} }; From 920fecc1aa4591da27ef9dcb338fc5da86b404d7 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Sat, 30 May 2020 17:11:01 -0700 Subject: [PATCH 66/72] pinctrl: bcm2835: Add support for wake-up interrupts Leverage the IRQCHIP_MASK_ON_SUSPEND flag in order to avoid having to specifically treat the GPIO interrupts during suspend and resume, and simply implement an irq_set_wake() callback that is responsible for enabling the parent wake-up interrupt as a wake-up interrupt. To avoid allocating unnecessary resources for other chips, the wake-up interrupts are only initialized if we have a brcm,bcm7211-gpio compatibility string. Signed-off-by: Florian Fainelli Link: https://lore.kernel.org/r/20200531001101.24945-5-f.fainelli@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/bcm/pinctrl-bcm2835.c | 76 ++++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 1b00d93aa66e..1d21129f7751 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -76,6 +77,7 @@ struct bcm2835_pinctrl { struct device *dev; void __iomem *base; + int *wake_irq; /* note: locking assumes each bank will have its own unsigned long */ unsigned long enabled_irq_map[BCM2835_NUM_BANKS]; @@ -435,6 +437,11 @@ static void bcm2835_gpio_irq_handler(struct irq_desc *desc) chained_irq_exit(host_chip, desc); } +static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc, unsigned reg, unsigned offset, bool enable) { @@ -634,6 +641,34 @@ static void bcm2835_gpio_irq_ack(struct irq_data *data) bcm2835_gpio_set_bit(pc, GPEDS0, gpio); } +static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) +{ + struct gpio_chip *chip = irq_data_get_irq_chip_data(data); + struct bcm2835_pinctrl *pc = gpiochip_get_data(chip); + unsigned gpio = irqd_to_hwirq(data); + unsigned int irqgroup; + int ret = -EINVAL; + + if (!pc->wake_irq) + return ret; + + if (gpio <= 27) + irqgroup = 0; + else if (gpio >= 28 && gpio <= 45) + irqgroup = 1; + else if (gpio >= 46 && gpio <= 57) + irqgroup = 2; + else + return ret; + + if (on) + ret = enable_irq_wake(pc->wake_irq[irqgroup]); + else + ret = disable_irq_wake(pc->wake_irq[irqgroup]); + + return ret; +} + static struct irq_chip bcm2835_gpio_irq_chip = { .name = MODULE_NAME, .irq_enable = bcm2835_gpio_irq_enable, @@ -642,6 +677,8 @@ static struct irq_chip bcm2835_gpio_irq_chip = { .irq_ack = bcm2835_gpio_irq_ack, .irq_mask = bcm2835_gpio_irq_disable, .irq_unmask = bcm2835_gpio_irq_enable, + .irq_set_wake = bcm2835_gpio_irq_set_wake, + .flags = IRQCHIP_MASK_ON_SUSPEND, }; static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) @@ -1154,6 +1191,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) struct resource iomem; int err, i; const struct of_device_id *match; + int is_7211 = 0; BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS); BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS); @@ -1180,6 +1218,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) return -EINVAL; pdata = match->data; + is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio"); pc->gpio_chip = *pdata->gpio_chip; pc->gpio_chip.parent = dev; @@ -1214,6 +1253,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) GFP_KERNEL); if (!girq->parents) return -ENOMEM; + + if (is_7211) { + pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS, + sizeof(*pc->wake_irq), + GFP_KERNEL); + if (!pc->wake_irq) + return -ENOMEM; + } + /* * Use the same handler for all groups: this is necessary * since we use one gpiochip to cover all lines - the @@ -1221,8 +1269,34 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) * bank that was firing the IRQ and look up the per-group * and bank data. */ - for (i = 0; i < BCM2835_NUM_IRQS; i++) + for (i = 0; i < BCM2835_NUM_IRQS; i++) { + int len; + char *name; + girq->parents[i] = irq_of_parse_and_map(np, i); + if (!is_7211) + continue; + + /* Skip over the all banks interrupts */ + pc->wake_irq[i] = irq_of_parse_and_map(np, i + + BCM2835_NUM_IRQS + 1); + + len = strlen(dev_name(pc->dev)) + 16; + name = devm_kzalloc(pc->dev, len, GFP_KERNEL); + if (!name) + return -ENOMEM; + + snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i); + + /* These are optional interrupts */ + err = devm_request_irq(dev, pc->wake_irq[i], + bcm2835_gpio_wake_irq_handler, + IRQF_SHARED, name, pc); + if (err) + dev_warn(dev, "unable to request wake IRQ %d\n", + pc->wake_irq[i]); + } + girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; From 9eb728321286c4b31e964d2377fca2368526d408 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 30 May 2020 22:19:52 +0200 Subject: [PATCH 67/72] pinctrl: imxl: Fix an error handling path in 'imx1_pinctrl_core_probe()' When 'pinctrl_register()' has been turned into 'devm_pinctrl_register()', an error handling path has not been updated. Axe a now unneeded 'pinctrl_unregister()'. Fixes: e55e025d1687 ("pinctrl: imxl: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Christophe JAILLET Link: https://lore.kernel.org/r/20200530201952.585798-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx1-core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx1-core.c b/drivers/pinctrl/freescale/pinctrl-imx1-core.c index 0c1c0e72fa8e..08d110078c43 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx1-core.c +++ b/drivers/pinctrl/freescale/pinctrl-imx1-core.c @@ -638,7 +638,6 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev, ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); if (ret) { - pinctrl_unregister(ipctl->pctl); dev_err(&pdev->dev, "Failed to populate subdevices\n"); return ret; } From 66339f2fba3fa05b0507e1887e4c6abcfc6228a3 Mon Sep 17 00:00:00 2001 From: yu kuai Date: Wed, 3 Jun 2020 09:35:32 +0800 Subject: [PATCH 68/72] pinctrl: sirf: add missing put_device() call in sirfsoc_gpio_probe() A coccicheck run provided information like the following: drivers/pinctrl/sirf/pinctrl-sirf.c:798:2-8: ERROR: missing put_device; call of_find_device_by_node on line 792, but without a corresponding object release within this function. Generated by: scripts/coccinelle/free/put_device.cocci Thus add a jump target to fix the exception handling for this function implementation. Fixes: 5130216265f6 ("PINCTRL: SiRF: add GPIO and GPIO irq support in CSR SiRFprimaII") Signed-off-by: yu kuai Link: https://lore.kernel.org/r/20200603013532.755220-1-yukuai3@huawei.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sirf/pinctrl-sirf.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c index 1ebcb957c654..63a287d5795f 100644 --- a/drivers/pinctrl/sirf/pinctrl-sirf.c +++ b/drivers/pinctrl/sirf/pinctrl-sirf.c @@ -794,13 +794,17 @@ static int sirfsoc_gpio_probe(struct device_node *np) return -ENODEV; sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); - if (!sgpio) - return -ENOMEM; + if (!sgpio) { + err = -ENOMEM; + goto out_put_device; + } spin_lock_init(&sgpio->lock); regs = of_iomap(np, 0); - if (!regs) - return -ENOMEM; + if (!regs) { + err = -ENOMEM; + goto out_put_device; + } sgpio->chip.gc.request = sirfsoc_gpio_request; sgpio->chip.gc.free = sirfsoc_gpio_free; @@ -824,8 +828,10 @@ static int sirfsoc_gpio_probe(struct device_node *np) girq->parents = devm_kcalloc(&pdev->dev, SIRFSOC_GPIO_NO_OF_BANKS, sizeof(*girq->parents), GFP_KERNEL); - if (!girq->parents) - return -ENOMEM; + if (!girq->parents) { + err = -ENOMEM; + goto out_put_device; + } for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { bank = &sgpio->sgpio_bank[i]; spin_lock_init(&bank->lock); @@ -868,6 +874,8 @@ static int sirfsoc_gpio_probe(struct device_node *np) gpiochip_remove(&sgpio->chip.gc); out: iounmap(regs); +out_put_device: + put_device(&pdev->dev); return err; } From 11d8da5cabf7c6c3263ba2cd9c00260395867048 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sat, 30 May 2020 22:49:55 +0200 Subject: [PATCH 69/72] pinctrl: freescale: imx: Fix an error handling path in 'imx_pinctrl_probe()' 'pinctrl_unregister()' should not be called to undo 'devm_pinctrl_register_and_init()', it is already handled by the framework. This simplifies the error handling paths of the probe function. The 'imx_free_resources()' can be removed as well. Fixes: a51c158bf0f7 ("pinctrl: imx: use radix trees for groups and functions") Signed-off-by: Christophe JAILLET Reviewed-by: Dong Aisheng Link: https://lore.kernel.org/r/20200530204955.588962-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 9f42036c5fbb..1f81569c7ae3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -774,16 +774,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev, return 0; } -/* - * imx_free_resources() - free memory used by this driver - * @info: info driver instance - */ -static void imx_free_resources(struct imx_pinctrl *ipctl) -{ - if (ipctl->pctl) - pinctrl_unregister(ipctl->pctl); -} - int imx_pinctrl_probe(struct platform_device *pdev, const struct imx_pinctrl_soc_info *info) { @@ -874,23 +864,18 @@ int imx_pinctrl_probe(struct platform_device *pdev, &ipctl->pctl); if (ret) { dev_err(&pdev->dev, "could not register IMX pinctrl driver\n"); - goto free; + return ret; } ret = imx_pinctrl_probe_dt(pdev, ipctl); if (ret) { dev_err(&pdev->dev, "fail to probe dt properties\n"); - goto free; + return ret; } dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); return pinctrl_enable(ipctl->pctl); - -free: - imx_free_resources(ipctl); - - return ret; } static int __maybe_unused imx_pinctrl_suspend(struct device *dev) From ba403242615c2c99e27af7984b1650771a2cc2c9 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Tue, 2 Jun 2020 22:06:26 +0200 Subject: [PATCH 70/72] pinctrl: freescale: imx: Use 'devm_of_iomap()' to avoid a resource leak in case of error in 'imx_pinctrl_probe()' Use 'devm_of_iomap()' instead 'of_iomap()' to avoid a resource leak in case of error. Update the error handling code accordingly. Fixes: 26d8cde5260b ("pinctrl: freescale: imx: add shared input select reg support") Suggested-by: Dan Carpenter Signed-off-by: Christophe JAILLET Reviewed-by: Dan Carpenter Link: https://lore.kernel.org/r/20200602200626.677981-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/freescale/pinctrl-imx.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index 1f81569c7ae3..cb7e0f08d2cf 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -824,12 +824,13 @@ int imx_pinctrl_probe(struct platform_device *pdev, return -EINVAL; } - ipctl->input_sel_base = of_iomap(np, 0); + ipctl->input_sel_base = devm_of_iomap(&pdev->dev, np, + 0, NULL); of_node_put(np); - if (!ipctl->input_sel_base) { + if (IS_ERR(ipctl->input_sel_base)) { dev_err(&pdev->dev, "iomuxc input select base address not found\n"); - return -ENOMEM; + return PTR_ERR(ipctl->input_sel_base); } } } From 08acc963190a3a0eb491efa9cc466b2c18d59f22 Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Sun, 31 May 2020 09:37:16 +0200 Subject: [PATCH 71/72] pinctrl: pxa: pxa2xx: Remove 'pxa2xx_pinctrl_exit()' which is unused and broken Commit 6d33ee7a0534 ("pinctrl: pxa: Use devm_pinctrl_register() for pinctrl registration") has turned a 'pinctrl_register()' into 'devm_pinctrl_register()' in 'pxa2xx_pinctrl_init()'. However, the corresponding 'pinctrl_unregister()' call in 'pxa2xx_pinctrl_exit()' has not been removed. This is not an issue, because 'pxa2xx_pinctrl_exit()' is unused. Remove it now to avoid some wondering in the future and save a few LoC. Fixes: 6d33ee7a0534 ("pinctrl: pxa: Use devm_pinctrl_register() for pinctrl registration") Signed-off-by: Christophe JAILLET Acked-by: Robert Jarzmik Link: https://lore.kernel.org/r/20200531073716.593343-1-christophe.jaillet@wanadoo.fr Signed-off-by: Linus Walleij --- drivers/pinctrl/pxa/pinctrl-pxa2xx.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c index bddf2c5dd3bf..eab029a21643 100644 --- a/drivers/pinctrl/pxa/pinctrl-pxa2xx.c +++ b/drivers/pinctrl/pxa/pinctrl-pxa2xx.c @@ -425,15 +425,6 @@ int pxa2xx_pinctrl_init(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init); -int pxa2xx_pinctrl_exit(struct platform_device *pdev) -{ - struct pxa_pinctrl *pctl = platform_get_drvdata(pdev); - - pinctrl_unregister(pctl->pctl_dev); - return 0; -} -EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_exit); - MODULE_AUTHOR("Robert Jarzmik "); MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver"); MODULE_LICENSE("GPL v2"); From 94873f6b46f8c103759c28adc121a58022972d01 Mon Sep 17 00:00:00 2001 From: Baolin Wang Date: Thu, 7 May 2020 11:47:25 +0800 Subject: [PATCH 72/72] pinctrl: sprd: Fix the incorrect pull-up definition The bits of pull up resistor selection were defined mistakenly, thus fix them. Fixes: 41d32cfce1ae ("pinctrl: sprd: Add Spreadtrum pin control driver") Signed-off-by: Baolin Wang Link: https://lore.kernel.org/r/e973f8f194ce4cb2639121572e8621b5efa5bfbe.1588823152.git.baolin.wang7@gmail.com Signed-off-by: Linus Walleij --- drivers/pinctrl/sprd/pinctrl-sprd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sprd/pinctrl-sprd.c b/drivers/pinctrl/sprd/pinctrl-sprd.c index 48cbf2a2837f..08dc1931b358 100644 --- a/drivers/pinctrl/sprd/pinctrl-sprd.c +++ b/drivers/pinctrl/sprd/pinctrl-sprd.c @@ -68,8 +68,8 @@ #define SLEEP_PULL_UP_MASK 0x1 #define SLEEP_PULL_UP_SHIFT 3 -#define PULL_UP_20K (BIT(12) | BIT(7)) -#define PULL_UP_4_7K BIT(12) +#define PULL_UP_4_7K (BIT(12) | BIT(7)) +#define PULL_UP_20K BIT(7) #define PULL_UP_MASK 0x21 #define PULL_UP_SHIFT 7