forked from luck/tmp_suning_uos_patched
Texas Instruments K3 SoC DT updates for v5.9
- Add platforms chipid nodes for am65x and j721e - Update latest data sheet values for MMC on am65x - Add serdes and usb3 support for j721e - Add analog audio support for j721e - Add SD card support for am65x - Rename DT nodes for gic-its/smmu to their standard counterparts am65x/j721e - HTTP links replaced with HTTPS ones -----BEGIN PGP SIGNATURE----- iQJEBAABCgAuFiEEtQ6szHmfiBT7fujkyvq9MXlQGhEFAl8aj4cQHHQta3Jpc3Rv QHRpLmNvbQAKCRDK+r0xeVAaEfxHD/4kE90nx+EyiSGQ5ZCNfoXs/0JB95KAGGcv 23PGvjYBfD/GFGvbL+4F7GTptqEJrkJXMcfCIR2Nv5fjhA+OjjPMzj73octytasN iRc+ESXLgD07bLdTWEvGvMqBaslfLOajs2PSu7LOMGK6NihRiqCGR5urk6e8h0Jt gY4gb1EFN01VIYB7n3xy7CgpHx/G6g0VJ1TjpEZVyM5G3K50/qrKzJmxX9MIiVBm o9E85dveFe3yxvI6BepwQpfrrVg5j6xlJCHrQ0xepPiKAjCzlTaxOdTm2omGemES h7DQ2CAD23SJ+SnF4bCltoNw/1GOfw1CoslB9X4FdvSBknp61VjrfeGp9PKZHxFI EvEV1tmpAFAhxSlY4zcyhmpMcBiKzGojGExK0COt5hHm7ssbTIaDKNTTJByzI1cJ FkHr609ktYmSyfg9JVejiCPa9D/8etYqkgy/9edM4iYLss4TkPGHHD+C0iqMQaCA mcOsquOaTnbiATQuqAaoLzZbUKSO4R57DgXAO7+XzOgaQutBRJ5VMgREM8apNYUa baE779XQfCMiOpgEpEpwQMVVgt6S/PUXis6yZy2BpP3npbKVKI53f0wpZc0FvM8e 9J5cpWBLX1qK0lO8KinGRfW09+EcSlbWe2Byh1EKfqogRsfJlsPYyAuEg3BwDr1o XMQS/p1aPQ== =0bPs -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt Texas Instruments K3 SoC DT updates for v5.9 - Add platforms chipid nodes for am65x and j721e - Update latest data sheet values for MMC on am65x - Add serdes and usb3 support for j721e - Add analog audio support for j721e - Add SD card support for am65x - Rename DT nodes for gic-its/smmu to their standard counterparts am65x/j721e - HTTP links replaced with HTTPS ones * tag 'ti-k3-dt-for-v5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX arm64: dts: ti: k3-j721e-main: Add system controller node and SERDES lane mux arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes dt-bindings: mfd: ti,j721e-system-controller.yaml: Add J721e system controller arm64: dts: ti: k3-am65/j721e-main: rename gic-its node to msi-controller arm64: dts: ti: k3-j721e-main: rename smmu node to iommu arm64: dts: ti: k3-*: Replace HTTP links with HTTPS ones arm64: dts: ti: k3-am654-base-board: Add support for SD card arm64: dts: ti: k3-am65-main: Add support for sdhci1 arm64: dts: ti: j721e-common-proc-board: Analog audio support arm64: dts: ti: k3-j721e-common-proc-board: Remove duplicated main_i2c1_exp4_pins_default arm64: dts: ti: k3-am654-main: Update otap-del-sel values arm64: dts: ti: k3-j721e-mcu-wakeup: add k3 platforms chipid module node arm64: dts: ti: k3-am65-wakeup: add k3 platforms chipid module node Link: https://lore.kernel.org/r/3b3b9214-769d-ba1b-db5e-44414a8c5756@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
cf8182fc9d
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@ -0,0 +1,74 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mfd/ti,j721e-system-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI J721e System Controller Registers R/W Device Tree Bindings
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description: |
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This represents the Control Module registers (CTRL_MMR0) on the SoC.
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System controller node represents a register region containing a set
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of miscellaneous registers. The registers are not cohesive enough to
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represent as any specific type of device. The typical use-case is
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for some other node's driver, or platform-specific code, to acquire
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a reference to the syscon node (e.g. by phandle, node path, or
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search using a specific compatible value), interrogate the node (or
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associated OS driver) to determine the location of the registers,
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and access the registers directly.
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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- Roger Quadros <rogerq@ti.com
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properties:
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compatible:
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anyOf:
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- items:
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- enum:
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- ti,j721e-system-controller
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- const: syscon
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- const: simple-mfd
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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# Optional children
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"^serdes-ln-ctrl@[0-9a-f]+$":
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type: object
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description: |
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This is the SERDES lane control mux. It should follow the bindings
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specified in
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Documentation/devicetree/bindings/mux/reg-mux.txt
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- ranges
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unevaluatedProperties: false
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examples:
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- |
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scm_conf: scm-conf@100000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00100000 0x1c000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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serdes_ln_ctrl: serdes-ln-ctrl@4080 {
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compatible = "mmio-mux";
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reg = <0x00004080 0x50>;
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};
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};
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...
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@ -3,7 +3,7 @@
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# Make file to build device tree binaries for boards based on
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# Texas Instruments Inc processors
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#
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# Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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# Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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#
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dtb-$(CONFIG_ARCH_K3_AM6_SOC) += k3-am654-base-board.dtb
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/phy/phy-am654-serdes.h>
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@ -42,7 +42,7 @@ gic500: interrupt-controller@1800000 {
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*/
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@1820000 {
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gic_its: msi-controller@1820000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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@ -244,9 +244,43 @@ sdhci0: sdhci@4f80000 {
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interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x5>;
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ti,otap-del-sel-ddr52 = <0x5>;
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ti,otap-del-sel-hs200 = <0x5>;
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ti,otap-del-sel-hs400 = <0x0>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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};
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sdhci1: sdhci@4fa0000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
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clock-names = "clk_ahb", "clk_xin";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0x0>;
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ti,otap-del-sel-sdr25 = <0x0>;
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ti,otap-del-sel-sdr50 = <0x8>;
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ti,otap-del-sel-sdr104 = <0x7>;
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ti,otap-del-sel-ddr50 = <0x4>;
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ti,otap-del-sel-ddr52 = <0x4>;
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ti,otap-del-sel-hs200 = <0x7>;
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ti,clkbuf-sel = <0x7>;
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ti,otap-del-sel = <0x2>;
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ti,trm-icp = <0x8>;
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dma-coherent;
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no-1-8-v;
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};
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scm_conf: scm_conf@100000 {
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|
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC Family MCU Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu {
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC Family Wakeup Domain peripherals
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_wakeup {
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@ -34,6 +34,11 @@ k3_reset: reset-controller {
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};
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};
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chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x43000014 0x4>;
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};
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wkup_pmx0: pinmux@4301c000 {
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compatible = "pinctrl-single";
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reg = <0x4301c000 0x118>;
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|
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC Family
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <dt-bindings/gpio/gpio.h>
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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@ -167,6 +167,19 @@ AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */
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AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */
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AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */
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AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */
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AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */
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AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */
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AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */
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AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
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>;
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};
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usb1_pins_default: usb1_pins_default {
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pinctrl-single,pins = <
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AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */
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@ -300,6 +313,18 @@ &sdhci0 {
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disable-wp;
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};
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/*
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* Because of erratas i2025 and i2026 for silicon revision 1.0, the
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* SD card interface might fail. Boards with sr1.0 are recommended to
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* disable sdhci1
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*/
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&sdhci1 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_mmc1_pins_default>;
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ti,driver-strength-ohm = <50>;
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disable-wp;
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};
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&dwc3_1 {
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status = "okay";
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};
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|
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for AM6 SoC family in Quad core configuration
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*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include "k3-am65.dtsi"
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|
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
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* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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@ -34,6 +34,55 @@ sw11: sw11 {
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gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
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};
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};
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evm_12v0: fixedregulator-evm12v0 {
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/* main supply */
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compatible = "regulator-fixed";
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regulator-name = "evm_12v0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_3v3: fixedregulator-vsys3v3 {
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/* Output of LMS140 */
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compatible = "regulator-fixed";
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regulator-name = "vsys_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_5v0: fixedregulator-vsys5v0 {
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/* Output of LM5140 */
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compatible = "regulator-fixed";
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regulator-name = "vsys_5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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sound0: sound@0 {
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compatible = "ti,j721e-cpb-audio";
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model = "j721e-cpb";
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ti,cpb-mcasp = <&mcasp10>;
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ti,cpb-codec = <&pcm3168a_1>;
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clocks = <&k3_clks 184 1>,
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<&k3_clks 184 2>, <&k3_clks 184 4>,
|
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<&k3_clks 157 371>,
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<&k3_clks 157 400>, <&k3_clks 157 401>;
|
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clock-names = "cpb-mcasp-auxclk",
|
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"cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
|
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"cpb-codec-scki",
|
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"cpb-codec-scki-48000", "cpb-codec-scki-44100";
|
||||
};
|
||||
};
|
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&main_pmx0 {
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||||
|
|
@ -60,6 +109,7 @@ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
|
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main_usbss0_pins_default: main_usbss0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
||||
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
|
||||
>;
|
||||
};
|
||||
|
||||
|
|
@ -103,10 +153,24 @@ J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
|
|||
>;
|
||||
};
|
||||
|
||||
main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
|
||||
mcasp10_pins_default: mcasp10_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
|
||||
>;
|
||||
J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
|
||||
J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
|
||||
J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
|
||||
J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
|
||||
J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
|
||||
J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
|
||||
J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
|
||||
J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
|
||||
J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
|
||||
>;
|
||||
};
|
||||
|
||||
audi_ext_refclk2_pins_default: audi_ext_refclk2_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -335,16 +399,44 @@ &main_sdhci2 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&usb_serdes_mux {
|
||||
idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
|
||||
};
|
||||
|
||||
&serdes_ln_ctrl {
|
||||
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
|
||||
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
|
||||
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
|
||||
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
|
||||
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
|
||||
};
|
||||
|
||||
&serdes_wiz3 {
|
||||
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
|
||||
typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
|
||||
};
|
||||
|
||||
&serdes3 {
|
||||
serdes3_usb_link: link@0 {
|
||||
reg = <0>;
|
||||
cdns,num-lanes = <2>;
|
||||
#phy-cells = <0>;
|
||||
cdns,phy-type = <PHY_TYPE_USB3>;
|
||||
resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
|
||||
};
|
||||
};
|
||||
|
||||
&usbss0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_usbss0_pins_default>;
|
||||
ti,usb2-only;
|
||||
ti,vbus-divider;
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
maximum-speed = "super-speed";
|
||||
phys = <&serdes3_usb_link>;
|
||||
phy-names = "cdns3,usb3-phy";
|
||||
};
|
||||
|
||||
&usbss1 {
|
||||
|
|
@ -407,6 +499,22 @@ exp2: gpio@22 {
|
|||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
p09 {
|
||||
/* P11 - MCASP/TRACE_MUX_S0 */
|
||||
gpio-hog;
|
||||
gpios = <9 GPIO_ACTIVE_HIGH>;
|
||||
output-low;
|
||||
line-name = "MCASP/TRACE_MUX_S0";
|
||||
};
|
||||
|
||||
p10 {
|
||||
/* P12 - MCASP/TRACE_MUX_S1 */
|
||||
gpio-hog;
|
||||
gpios = <10 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
line-name = "MCASP/TRACE_MUX_S1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -429,6 +537,12 @@ exp4: gpio@20 {
|
|||
};
|
||||
};
|
||||
|
||||
&k3_clks {
|
||||
/* Confiure AUDIO_EXT_REFCLK2 pin as output */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audi_ext_refclk2_pins_default>;
|
||||
};
|
||||
|
||||
&main_i2c3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c3_pins_default>;
|
||||
|
|
@ -440,6 +554,31 @@ exp3: gpio@20 {
|
|||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
pcm3168a_1: audio-codec@44 {
|
||||
compatible = "ti,pcm3168a";
|
||||
reg = <0x44>;
|
||||
|
||||
#sound-dai-cells = <1>;
|
||||
|
||||
reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
|
||||
|
||||
/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
|
||||
clocks = <&k3_clks 157 371>;
|
||||
clock-names = "scki";
|
||||
|
||||
/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
|
||||
assigned-clocks = <&k3_clks 157 371>;
|
||||
assigned-clock-parents = <&k3_clks 157 400>;
|
||||
assigned-clock-rates = <24576000>; /* for 48KHz */
|
||||
|
||||
VDD1-supply = <&vsys_3v3>;
|
||||
VDD2-supply = <&vsys_3v3>;
|
||||
VCCAD1-supply = <&vsys_5v0>;
|
||||
VCCAD2-supply = <&vsys_5v0>;
|
||||
VCCDA1-supply = <&vsys_5v0>;
|
||||
VCCDA2-supply = <&vsys_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&main_i2c6 {
|
||||
|
|
@ -492,3 +631,23 @@ &dss {
|
|||
<&k3_clks 152 11>, /* PLL18_HSDIV0 */
|
||||
<&k3_clks 152 18>; /* PLL23_HSDIV0 */
|
||||
};
|
||||
|
||||
&mcasp10 {
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcasp10_pins_default>;
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
auxclk-fs-ratio = <256>;
|
||||
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
1 1 1 1
|
||||
2 2 2 0
|
||||
>;
|
||||
tx-num-evt = <0>;
|
||||
rx-num-evt = <0>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,8 +2,11 @@
|
|||
/*
|
||||
* Device Tree Source for J721E SoC Family Main Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
#include <dt-bindings/mux/mux.h>
|
||||
#include <dt-bindings/mux/mux-j721e-wiz.h>
|
||||
|
||||
&cbass_main {
|
||||
msmc_ram: sram@70000000 {
|
||||
|
|
@ -18,6 +21,38 @@ atf-sram@0 {
|
|||
};
|
||||
};
|
||||
|
||||
scm_conf: scm-conf@100000 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
||||
|
||||
serdes_ln_ctrl: serdes-ln-ctrl@4080 {
|
||||
compatible = "mmio-mux";
|
||||
reg = <0x00004080 0x50>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
|
||||
<0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
|
||||
<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
|
||||
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
|
||||
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
|
||||
/* SERDES4 lane0/1/2/3 select */
|
||||
idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
|
||||
<SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
|
||||
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
|
||||
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
|
||||
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
|
||||
};
|
||||
|
||||
usb_serdes_mux: mux-controller@4000 {
|
||||
compatible = "mmio-mux";
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
|
||||
<0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
|
||||
};
|
||||
};
|
||||
|
||||
gic500: interrupt-controller@1800000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#address-cells = <2>;
|
||||
|
|
@ -31,7 +66,7 @@ gic500: interrupt-controller@1800000 {
|
|||
/* vcpumntirq: virtual CPU interface maintenance interrupt */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gic_its: gic-its@1820000 {
|
||||
gic_its: msi-controller@1820000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
reg = <0x00 0x01820000 0x00 0x10000>;
|
||||
socionext,synquacer-pre-its = <0x1000000 0x400000>;
|
||||
|
|
@ -95,7 +130,7 @@ secure_proxy_main: mailbox@32c00000 {
|
|||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
smmu0: smmu@36600000 {
|
||||
smmu0: iommu@36600000 {
|
||||
compatible = "arm,smmu-v3";
|
||||
reg = <0x0 0x36600000 0x0 0x100000>;
|
||||
interrupt-parent = <&gic500>;
|
||||
|
|
@ -277,6 +312,246 @@ main_pmx0: pinmux@11c000 {
|
|||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk: dummy-cmn-refclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
dummy_cmn_refclk1: dummy-cmn-refclk1 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
serdes_wiz0: wiz@5000000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
|
||||
assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
|
||||
num-lanes = <2>;
|
||||
#reset-cells = <1>;
|
||||
ranges = <0x5000000 0x0 0x5000000 0x10000>;
|
||||
|
||||
wiz0_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
};
|
||||
|
||||
wiz0_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 292 0>;
|
||||
};
|
||||
|
||||
wiz0_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz0_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 292 11>;
|
||||
};
|
||||
|
||||
wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
|
||||
clocks = <&wiz0_refclk_dig>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
|
||||
clocks = <&wiz0_pll1_refclk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
serdes0: serdes@5000000 {
|
||||
compatible = "ti,sierra-phy-t0";
|
||||
reg-names = "serdes";
|
||||
reg = <0x5000000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&serdes_wiz0 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz1: wiz@5010000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
|
||||
assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
|
||||
num-lanes = <2>;
|
||||
#reset-cells = <1>;
|
||||
ranges = <0x5010000 0x0 0x5010000 0x10000>;
|
||||
|
||||
wiz1_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
};
|
||||
|
||||
wiz1_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 293 0>;
|
||||
};
|
||||
|
||||
wiz1_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz1_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 293 13>;
|
||||
};
|
||||
|
||||
wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
|
||||
clocks = <&wiz1_refclk_dig>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
|
||||
clocks = <&wiz1_pll1_refclk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
serdes1: serdes@5010000 {
|
||||
compatible = "ti,sierra-phy-t0";
|
||||
reg-names = "serdes";
|
||||
reg = <0x5010000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&serdes_wiz1 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz2: wiz@5020000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
|
||||
assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
|
||||
num-lanes = <2>;
|
||||
#reset-cells = <1>;
|
||||
ranges = <0x5020000 0x0 0x5020000 0x10000>;
|
||||
|
||||
wiz2_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
};
|
||||
|
||||
wiz2_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 294 0>;
|
||||
};
|
||||
|
||||
wiz2_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz2_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 294 11>;
|
||||
};
|
||||
|
||||
wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
|
||||
clocks = <&wiz2_refclk_dig>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
|
||||
clocks = <&wiz2_pll1_refclk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
serdes2: serdes@5020000 {
|
||||
compatible = "ti,sierra-phy-t0";
|
||||
reg-names = "serdes";
|
||||
reg = <0x5020000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&serdes_wiz2 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
};
|
||||
};
|
||||
|
||||
serdes_wiz3: wiz@5030000 {
|
||||
compatible = "ti,j721e-wiz-16g";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
clock-names = "fck", "core_ref_clk", "ext_ref_clk";
|
||||
assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
|
||||
assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
|
||||
num-lanes = <2>;
|
||||
#reset-cells = <1>;
|
||||
ranges = <0x5030000 0x0 0x5030000 0x10000>;
|
||||
|
||||
wiz3_pll0_refclk: pll0-refclk {
|
||||
clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll0_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
};
|
||||
|
||||
wiz3_pll1_refclk: pll1-refclk {
|
||||
clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_pll1_refclk>;
|
||||
assigned-clock-parents = <&k3_clks 295 0>;
|
||||
};
|
||||
|
||||
wiz3_refclk_dig: refclk-dig {
|
||||
clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
|
||||
#clock-cells = <0>;
|
||||
assigned-clocks = <&wiz3_refclk_dig>;
|
||||
assigned-clock-parents = <&k3_clks 295 9>;
|
||||
};
|
||||
|
||||
wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
|
||||
clocks = <&wiz3_refclk_dig>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
|
||||
clocks = <&wiz3_pll1_refclk>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
serdes3: serdes@5030000 {
|
||||
compatible = "ti,sierra-phy-t0";
|
||||
reg-names = "serdes";
|
||||
reg = <0x5030000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
resets = <&serdes_wiz3 0>;
|
||||
reset-names = "sierra_reset";
|
||||
clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
|
||||
clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
|
||||
};
|
||||
};
|
||||
|
||||
main_uart0: serial@2800000 {
|
||||
compatible = "ti,j721e-uart", "ti,am654-uart";
|
||||
reg = <0x00 0x02800000 0x00 0x100>;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for J721E SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
|
|
@ -48,6 +48,11 @@ phy_gmii_sel: phy@4040 {
|
|||
};
|
||||
};
|
||||
|
||||
chipid@43000014 {
|
||||
compatible = "ti,am654-chipid";
|
||||
reg = <0x0 0x43000014 0x0 0x4>;
|
||||
};
|
||||
|
||||
wkup_pmx0: pinmux@4301c000 {
|
||||
compatible = "pinctrl-single";
|
||||
/* Proxy 0 addressing */
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for J721E SoC Family
|
||||
*
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
|
|
|||
53
include/dt-bindings/mux/mux-j721e-wiz.h
Normal file
53
include/dt-bindings/mux/mux-j721e-wiz.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* This header provides constants for J721E WIZ.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_J721E_WIZ
|
||||
#define _DT_BINDINGS_J721E_WIZ
|
||||
|
||||
#define SERDES0_LANE0_QSGMII_LANE1 0x0
|
||||
#define SERDES0_LANE0_PCIE0_LANE0 0x1
|
||||
#define SERDES0_LANE0_USB3_0_SWAP 0x2
|
||||
|
||||
#define SERDES0_LANE1_QSGMII_LANE2 0x0
|
||||
#define SERDES0_LANE1_PCIE0_LANE1 0x1
|
||||
#define SERDES0_LANE1_USB3_0 0x2
|
||||
|
||||
#define SERDES1_LANE0_QSGMII_LANE3 0x0
|
||||
#define SERDES1_LANE0_PCIE1_LANE0 0x1
|
||||
#define SERDES1_LANE0_USB3_1_SWAP 0x2
|
||||
#define SERDES1_LANE0_SGMII_LANE0 0x3
|
||||
|
||||
#define SERDES1_LANE1_QSGMII_LANE4 0x0
|
||||
#define SERDES1_LANE1_PCIE1_LANE1 0x1
|
||||
#define SERDES1_LANE1_USB3_1 0x2
|
||||
#define SERDES1_LANE1_SGMII_LANE1 0x3
|
||||
|
||||
#define SERDES2_LANE0_PCIE2_LANE0 0x1
|
||||
#define SERDES2_LANE0_SGMII_LANE0 0x3
|
||||
#define SERDES2_LANE0_USB3_1_SWAP 0x2
|
||||
|
||||
#define SERDES2_LANE1_PCIE2_LANE1 0x1
|
||||
#define SERDES2_LANE1_USB3_1 0x2
|
||||
#define SERDES2_LANE1_SGMII_LANE1 0x3
|
||||
|
||||
#define SERDES3_LANE0_PCIE3_LANE0 0x1
|
||||
#define SERDES3_LANE0_USB3_0_SWAP 0x2
|
||||
|
||||
#define SERDES3_LANE1_PCIE3_LANE1 0x1
|
||||
#define SERDES3_LANE1_USB3_0 0x2
|
||||
|
||||
#define SERDES4_LANE0_EDP_LANE0 0x0
|
||||
#define SERDES4_LANE0_QSGMII_LANE5 0x2
|
||||
|
||||
#define SERDES4_LANE1_EDP_LANE1 0x0
|
||||
#define SERDES4_LANE1_QSGMII_LANE6 0x2
|
||||
|
||||
#define SERDES4_LANE2_EDP_LANE2 0x0
|
||||
#define SERDES4_LANE2_QSGMII_LANE7 0x2
|
||||
|
||||
#define SERDES4_LANE3_EDP_LANE3 0x0
|
||||
#define SERDES4_LANE3_QSGMII_LANE8 0x2
|
||||
|
||||
#endif /* _DT_BINDINGS_J721E_WIZ */
|
||||
|
|
@ -3,7 +3,7 @@
|
|||
* This header provides constants for pinctrl bindings for TI's K3 SoC
|
||||
* family.
|
||||
*
|
||||
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_H
|
||||
#define _DT_BINDINGS_PINCTRL_TI_K3_H
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user