forked from luck/tmp_suning_uos_patched
[POWERPC] Improve resource setup of PowerMac G5 HT bridge
The device node for the HT bridge on G5s doesn't contain useful ranges. We used to give it a bunch of the known PCI space and then punch a "hole" in it based on where the AGP or PCIe region was. This reworks it to use the actual register in the bridge that controls the decoding instead. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
444532d44a
commit
d0264ce796
@ -40,8 +40,6 @@
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static int has_uninorth;
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#ifdef CONFIG_PPC64
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static struct pci_controller *u3_agp;
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static struct pci_controller *u4_pcie;
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static struct pci_controller *u3_ht;
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#else
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static int has_second_ohare;
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#endif /* CONFIG_PPC64 */
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@ -779,16 +777,50 @@ static void __init setup_u4_pcie(struct pci_controller* hose)
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*/
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hose->first_busno = 0x00;
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hose->last_busno = 0xff;
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u4_pcie = hose;
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}
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static void __init parse_region_decode(struct pci_controller *hose,
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u32 decode)
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{
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unsigned long base, end, next = -1;
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int i, cur = -1;
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/* Iterate through all bits. We ignore the last bit as this region is
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* reserved for the ROM among other niceties
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*/
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for (i = 0; i < 31; i++) {
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if ((decode & (0x80000000 >> i)) == 0)
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continue;
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if (i < 16) {
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base = 0xf0000000 | (((u32)i) << 24);
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end = base + 0x00ffffff;
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} else {
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base = ((u32)i-16) << 28;
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end = base + 0x0fffffff;
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}
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if (base != next) {
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if (++cur >= 3) {
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printk(KERN_WARNING "PCI: Too many ranges !\n");
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break;
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}
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hose->mem_resources[cur].flags = IORESOURCE_MEM;
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hose->mem_resources[cur].name = hose->dn->full_name;
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hose->mem_resources[cur].start = base;
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hose->mem_resources[cur].end = end;
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DBG(" %d: 0x%08lx-0x%08lx\n", cur, base, end);
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} else {
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DBG(" : -0x%08lx\n", end);
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hose->mem_resources[cur].end = end;
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}
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next = end + 1;
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}
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}
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static void __init setup_u3_ht(struct pci_controller* hose)
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{
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struct device_node *np = hose->dn;
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struct pci_controller *other = NULL;
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struct resource cfg_res, self_res;
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int i, cur;
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u32 decode;
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hose->ops = &u3_ht_pci_ops;
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@ -808,12 +840,9 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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self_res.end - self_res.start + 1);
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/*
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* /ht node doesn't expose a "ranges" property, so we "remove"
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* regions that have been allocated to AGP. So far, this version of
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* the code doesn't assign any of the 0xfxxxxxxx "fine" memory regions
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* to /ht. We need to fix that sooner or later by either parsing all
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* child "ranges" properties or figuring out the U3 address space
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* decoding logic and then read its configuration register (if any).
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* /ht node doesn't expose a "ranges" property, we read the register
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* that controls the decoding logic and use that for memory regions.
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* The IO region is hard coded since it is fixed in HW as well.
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*/
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hose->io_base_phys = 0xf4000000;
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hose->pci_io_size = 0x00400000;
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@ -824,76 +853,33 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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hose->pci_mem_offset = 0;
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hose->first_busno = 0;
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hose->last_busno = 0xef;
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hose->mem_resources[0].name = np->full_name;
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hose->mem_resources[0].start = 0x80000000;
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hose->mem_resources[0].end = 0xefffffff;
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hose->mem_resources[0].flags = IORESOURCE_MEM;
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u3_ht = hose;
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/* Note: fix offset when cfg_addr becomes a void * */
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decode = in_be32(hose->cfg_addr + 0x80);
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if (u3_agp != NULL)
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other = u3_agp;
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else if (u4_pcie != NULL)
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other = u4_pcie;
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DBG("PCI: Apple HT bridge decode register: 0x%08x\n", decode);
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if (other == NULL) {
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DBG("U3/4 has no AGP/PCIE, using full resource range\n");
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return;
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}
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/* Fixup bus range vs. PCIE */
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if (u4_pcie)
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hose->last_busno = u4_pcie->first_busno - 1;
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/* We "remove" the AGP resources from the resources allocated to HT,
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* that is we create "holes". However, that code does assumptions
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* that so far happen to be true (cross fingers...), typically that
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* resources in the AGP node are properly ordered
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/* NOTE: The decode register setup is a bit weird... region
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* 0xf8000000 for example is marked as enabled in there while it's
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& actually the memory controller registers.
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* That means that we are incorrectly attributing it to HT.
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*
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* In a similar vein, region 0xf4000000 is actually the HT IO space but
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* also marked as enabled in here and 0xf9000000 is used by some other
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* internal bits of the northbridge.
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*
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* Unfortunately, we can't just mask out those bit as we would end
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* up with more regions than we can cope (linux can only cope with
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* 3 memory regions for a PHB at this stage).
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*
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* So for now, we just do a little hack. We happen to -know- that
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* Apple firmware doesn't assign things below 0xfa000000 for that
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* bridge anyway so we mask out all bits we don't want.
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*/
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cur = 0;
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for (i=0; i<3; i++) {
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struct resource *res = &other->mem_resources[i];
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if (res->flags != IORESOURCE_MEM)
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continue;
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/* We don't care about "fine" resources */
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if (res->start >= 0xf0000000)
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continue;
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/* Check if it's just a matter of "shrinking" us in one
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* direction
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*/
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if (hose->mem_resources[cur].start == res->start) {
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DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
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cur, hose->mem_resources[cur].start,
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res->end + 1);
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hose->mem_resources[cur].start = res->end + 1;
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continue;
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}
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if (hose->mem_resources[cur].end == res->end) {
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DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
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cur, hose->mem_resources[cur].end,
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res->start - 1);
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hose->mem_resources[cur].end = res->start - 1;
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continue;
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}
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/* No, it's not the case, we need a hole */
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if (cur == 2) {
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/* not enough resources for a hole, we drop part
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* of the range
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*/
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printk(KERN_WARNING "Running out of resources"
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" for /ht host !\n");
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hose->mem_resources[cur].end = res->start - 1;
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continue;
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}
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cur++;
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DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
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cur-1, res->start - 1, cur, res->end + 1);
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hose->mem_resources[cur].name = np->full_name;
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hose->mem_resources[cur].flags = IORESOURCE_MEM;
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hose->mem_resources[cur].start = res->end + 1;
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hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
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hose->mem_resources[cur-1].end = res->start - 1;
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}
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decode &= 0x003fffff;
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/* Now parse the resulting bits and build resources */
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parse_region_decode(hose, decode);
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}
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#endif /* CONFIG_PPC64 */
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