AcoSail/kernel_optimize_test
8
0
Fork 0
forked from luck/tmp_suning_uos_patched
Code Pull Requests Activity

MIPS: lantiq: add GPHY clock gate bits

Browse Source 
Explicitly enable the clock gate of the internal GPHYs found on xrx200.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4816/
This commit is contained in:
John Crispin 2013-01-19 08:54:25 +00:00
parent 740c606e8e
commit d0c550dc36
2 changed files with 10 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/mips/lantiq/xway/reset.c
View File

@ -78,10 +78,19 @@ static struct ltq_xrx200_gphy_reset {
/* reset and boot a gphy. these phys only exist on xrx200 SoC */
int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
{
struct clk *clk;
if (!of_device_is_compatible(ltq_rcu_np, "lantiq,rcu-xrx200")) {
dev_err(dev, "this SoC has no GPHY\n");
return -EINVAL;
}
clk = clk_get_sys("1f203000.rcu", "gphy");
if (IS_ERR(clk))
return PTR_ERR(clk);
clk_enable(clk);
if (id > 1) {
dev_err(dev, "%u is an invalid gphy id\n", id);
return -EINVAL;

1
arch/mips/lantiq/xway/sysctrl.c
View File

@ -376,6 +376,7 @@ void __init ltq_soc_init(void)
PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
PMU_PPE_QSB | PMU_PPE_TOP);
clkdev_add_pmu("1f203000.rcu", "gphy", 0, PMU_GPHY);
} else if (of_machine_is_compatible("lantiq,ar9")) {
clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
ltq_ar9_fpi_hz(), CLOCK_250M);