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m68knommu: remove per device interrupt mask setting for ColdFire 520x

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With general interrupt controller code in place we don't need specific
unmasking code for the internal ColdFire 520x UARTs or ethernet (FEC).

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
This commit is contained in:
Greg Ungerer 2009-04-27 15:15:01 +10:00
parent cd3dd4068d
commit d0d77c26cb
1 changed files with 0 additions and 21 deletions
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21
arch/m68knommu/platform/520x/config.c
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@ -85,16 +85,11 @@ static struct platform_device *m520x_devices[] __initdata = {
static void __init m520x_uart_init_line(int line, int irq)
{
u32 imr;
u16 par;
u8 par2;
writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
imr = readl(INTC0 + MCFINTC_IMRL);
imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
writel(imr, INTC0 + MCFINTC_IMRL);
switch (line) {
case 0:
par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
@ -131,7 +126,6 @@ static void __init m520x_uarts_init(void)
static void __init m520x_fec_init(void)
{
u32 imr;
u8 v;
/* Unmask FEC interrupts at ColdFire interrupt controller */
@ -139,10 +133,6 @@ static void __init m520x_fec_init(void)
writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
imr &= ~0x0001FFF0;
writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
/* Set multi-function pins to ethernet mode */
v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
@ -153,17 +143,6 @@ static void __init m520x_fec_init(void)
/***************************************************************************/
/*
* Program the vector to be an auto-vectored.
*/
void mcf_autovector(unsigned int vec)
{
/* Everything is auto-vectored on the 520x devices */
}
/***************************************************************************/
static void m520x_cpu_reset(void)
{
local_irq_disable();