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MIPS: cleanup fixup_bigphys_addr handling

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fixup_bigphys_addr is only provided by the alchemy platform.  Remove
all the stubs, and ensure we only call it if it is actually implemented.

Also don't bother implementing io_remap_pfn_range if we don't have to,
and move the remaining implementation to alchemy platform code.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Christoph Hellwig 2020-04-16 17:00:07 +02:00 committed by Thomas Bogendoerfer
parent b604d4973a
commit d399157283
10 changed files with 27 additions and 93 deletions
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4
arch/mips/Kconfig
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@ -92,6 +92,9 @@ config MIPS
select SYSCTL_EXCEPTION_TRACE select SYSCTL_EXCEPTION_TRACE
select VIRT_TO_BUS select VIRT_TO_BUS
config MIPS_FIXUP_BIGPHYS_ADDR
bool
menu "Machine selection" menu "Machine selection"
choice choice
@ -157,6 +160,7 @@ config MIPS_ALCHEMY
select CSRC_R4K select CSRC_R4K
select IRQ_MIPS_CPU select IRQ_MIPS_CPU
select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is select DMA_MAYBE_COHERENT # Au1000,1500,1100 aren't, rest is
select MIPS_FIXUP_BIGPHYS_ADDR if PCI
select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_APM_EMULATION select SYS_SUPPORTS_APM_EMULATION

16
arch/mips/alchemy/common/setup.c
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@ -72,9 +72,9 @@ void __init plat_mem_setup(void)
iomem_resource.end = IOMEM_RESOURCE_END; iomem_resource.end = IOMEM_RESOURCE_END;
} }
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI) #ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
/* This routine should be valid for all Au1x based boards */ /* This routine should be valid for all Au1x based boards */
phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size) phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{ {
unsigned long start = ALCHEMY_PCI_MEMWIN_START; unsigned long start = ALCHEMY_PCI_MEMWIN_START;
unsigned long end = ALCHEMY_PCI_MEMWIN_END; unsigned long end = ALCHEMY_PCI_MEMWIN_END;
@ -90,5 +90,13 @@ phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
/* default nop */ /* default nop */
return phys_addr; return phys_addr;
} }
EXPORT_SYMBOL(__fixup_bigphys_addr);
#endif int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
unsigned long pfn, unsigned long size, pgprot_t prot)
{
phys_addr_t phys_addr = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, phys_addr >> PAGE_SHIFT, size, prot);
}
EXPORT_SYMBOL(io_remap_pfn_range);
#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */

38
arch/mips/include/asm/mach-au1x00/ioremap.h
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@ -1,38 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/asm-mips/mach-au1x00/ioremap.h
*/
#ifndef __ASM_MACH_AU1X00_IOREMAP_H
#define __ASM_MACH_AU1X00_IOREMAP_H
#include <linux/types.h>
#if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_PCI)
extern phys_addr_t __fixup_bigphys_addr(phys_addr_t, phys_addr_t);
#else
static inline phys_addr_t __fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
#endif
/*
* Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return __fixup_bigphys_addr(phys_addr, size);
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags)
{
return NULL;
}
static inline int plat_iounmap(const volatile void __iomem *addr)
{
return 0;
}
#endif /* __ASM_MACH_AU1X00_IOREMAP_H */

5
arch/mips/include/asm/mach-bcm63xx/ioremap.h
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@ -4,11 +4,6 @@
#include <bcm63xx_cpu.h> #include <bcm63xx_cpu.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bcm63xx_internal_registers(phys_addr_t offset) static inline int is_bcm63xx_internal_registers(phys_addr_t offset)
{ {
switch (bcm63xx_get_cpu_id()) { switch (bcm63xx_get_cpu_id()) {

5
arch/mips/include/asm/mach-bmips/ioremap.h
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@ -4,11 +4,6 @@
#include <linux/types.h> #include <linux/types.h>
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline int is_bmips_internal_registers(phys_addr_t offset) static inline int is_bmips_internal_registers(phys_addr_t offset)
{ {
if (offset >= 0xfff80000) if (offset >= 0xfff80000)

9
arch/mips/include/asm/mach-generic/ioremap.h
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@ -7,15 +7,6 @@
#include <linux/types.h> #include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags) unsigned long flags)
{ {

9
arch/mips/include/asm/mach-tx39xx/ioremap.h
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@ -7,15 +7,6 @@
#include <linux/types.h> #include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags) unsigned long flags)
{ {

9
arch/mips/include/asm/mach-tx49xx/ioremap.h
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@ -7,15 +7,6 @@
#include <linux/types.h> #include <linux/types.h>
/*
* Allow physical addresses to be fixed up to help peripherals located
* outside the low 32-bit range -- generic pass-through version.
*/
static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
{
return phys_addr;
}
static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size, static inline void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
unsigned long flags) unsigned long flags)
{ {

23
arch/mips/include/asm/pgtable.h
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@ -507,20 +507,17 @@ static inline void update_mmu_cache_pmd(struct vm_area_struct *vma,
#define kern_addr_valid(addr) (1) #define kern_addr_valid(addr) (1)
#ifdef CONFIG_PHYS_ADDR_T_64BIT /*
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot); * Allow physical addresses to be fixed up to help 36-bit peripherals.
*/
static inline int io_remap_pfn_range(struct vm_area_struct *vma, #ifdef CONFIG_MIPS_FIXUP_BIGPHYS_ADDR
unsigned long vaddr, phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size);
unsigned long pfn, int io_remap_pfn_range(struct vm_area_struct *vma, unsigned long vaddr,
unsigned long size, unsigned long pfn, unsigned long size, pgprot_t prot);
pgprot_t prot)
{
phys_addr_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
}
#define io_remap_pfn_range io_remap_pfn_range #define io_remap_pfn_range io_remap_pfn_range
#endif #else
#define fixup_bigphys_addr(addr, size) (addr)
#endif /* CONFIG_MIPS_FIXUP_BIGPHYS_ADDR */
#ifdef CONFIG_TRANSPARENT_HUGEPAGE #ifdef CONFIG_TRANSPARENT_HUGEPAGE

2
arch/mips/pci/pci-alchemy.c
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@ -52,7 +52,7 @@ struct alchemy_pci_context {
static struct alchemy_pci_context *__alchemy_pci_ctx; static struct alchemy_pci_context *__alchemy_pci_ctx;
/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr /* IO/MEM resources for PCI. Keep the memres in sync with fixup_bigphys_addr
* in arch/mips/alchemy/common/setup.c * in arch/mips/alchemy/common/setup.c
*/ */
static struct resource alchemy_pci_def_memres = { static struct resource alchemy_pci_def_memres = {