forked from luck/tmp_suning_uos_patched
serial: sh-sci: Generalize port pin initialization.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt
parent
d830fa4584
commit
d5701647f1
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@ -64,10 +64,6 @@ struct sci_port {
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/* Port IRQs: ERI, RXI, TXI, BRI (optional) */
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unsigned int irqs[SCIx_NR_IRQS];
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/* Port pin configuration */
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void (*init_pins)(struct uart_port *port,
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unsigned int cflag);
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/* Port enable callback */
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void (*enable)(struct uart_port *port);
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@ -172,7 +168,7 @@ static inline void h8300_sci_disable(struct uart_port *port)
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#endif
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#if defined(__H8300H__) || defined(__H8300S__)
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static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
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static void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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int ch = (port->mapbase - SMR0) >> 3;
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@ -187,140 +183,99 @@ static void sci_init_pins_sci(struct uart_port *port, unsigned int cflag)
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/* tx mark output*/
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H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
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}
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#else
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#define sci_init_pins_sci NULL
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
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static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag)
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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if (cflag & CRTSCTS)
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fcr_val |= SCFCR_MCE;
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sci_out(port, SCFCR, fcr_val);
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}
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#else
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#define sci_init_pins_irda NULL
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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set_sh771x_scif_pfc(port);
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if (cflag & CRTSCTS)
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fcr_val |= SCFCR_MCE;
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sci_out(port, SCFCR, fcr_val);
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if (port->mapbase == 0xA4400000) {
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__raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
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__raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
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} else if (port->mapbase == 0xA4410000)
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__raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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unsigned short data;
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if (cflag & CRTSCTS) {
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/* enable RTS/CTS */
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 9-2; enable all scif pins but sck */
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data = ctrl_inw(PORT_PTCR);
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ctrl_outw((data & 0xfc03), PORT_PTCR);
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xfc03), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 9-2 */
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data = ctrl_inw(PORT_PVCR);
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ctrl_outw((data & 0xfc03), PORT_PVCR);
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xfc03), PORT_PVCR);
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}
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fcr_val |= SCFCR_MCE;
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} else {
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if (port->mapbase == 0xa4430000) { /* SCIF0 */
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/* Clear PTCR bit 5-2; enable only tx and rx */
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data = ctrl_inw(PORT_PTCR);
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ctrl_outw((data & 0xffc3), PORT_PTCR);
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data = __raw_readw(PORT_PTCR);
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__raw_writew((data & 0xffc3), PORT_PTCR);
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} else if (port->mapbase == 0xa4438000) { /* SCIF1 */
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/* Clear PVCR bit 5-2 */
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data = ctrl_inw(PORT_PVCR);
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ctrl_outw((data & 0xffc3), PORT_PVCR);
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data = __raw_readw(PORT_PVCR);
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__raw_writew((data & 0xffc3), PORT_PVCR);
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}
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}
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sci_out(port, SCFCR, fcr_val);
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}
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#elif defined(CONFIG_CPU_SH3)
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/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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unsigned short data;
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/* We need to set SCPCR to enable RTS/CTS */
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data = ctrl_inw(SCPCR);
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data = __raw_readw(SCPCR);
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/* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
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ctrl_outw(data & 0x0fcf, SCPCR);
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__raw_writew(data & 0x0fcf, SCPCR);
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if (cflag & CRTSCTS)
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fcr_val |= SCFCR_MCE;
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else {
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if (!(cflag & CRTSCTS)) {
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/* We need to set SCPCR to enable RTS/CTS */
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data = ctrl_inw(SCPCR);
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data = __raw_readw(SCPCR);
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/* Clear out SCP7MD1,0, SCP4MD1,0,
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Set SCP6MD1,0 = {01} (output) */
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ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR);
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__raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
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data = ctrl_inb(SCPDR);
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/* Set /RTS2 (bit6) = 0 */
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ctrl_outb(data & 0xbf, SCPDR);
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}
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sci_out(port, SCFCR, fcr_val);
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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unsigned short data;
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if (port->mapbase == 0xffe00000) {
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data = ctrl_inw(PSCR);
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data = __raw_readw(PSCR);
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data &= ~0x03cf;
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if (cflag & CRTSCTS)
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fcr_val |= SCFCR_MCE;
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else
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if (!(cflag & CRTSCTS))
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data |= 0x0340;
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ctrl_outw(data, PSCR);
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__raw_writew(data, PSCR);
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}
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/* SCIF1 and SCIF2 should be setup by board code */
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sci_out(port, SCFCR, fcr_val);
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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{
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/* Nothing to do here.. */
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sci_out(port, SCFCR, 0);
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}
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#else
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/* For SH7750 */
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static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
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{
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unsigned int fcr_val = 0;
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if (cflag & CRTSCTS) {
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fcr_val |= SCFCR_MCE;
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} else {
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#if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366)
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/* Nothing */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SHX3)
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ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (!(cflag & CRTSCTS))
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__raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */
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}
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#elif defined(CONFIG_CPU_SH4)
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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if (!(cflag & CRTSCTS))
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__raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
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}
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#else
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ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */
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#endif
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}
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sci_out(port, SCFCR, fcr_val);
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static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
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{
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/* Nothing to do */
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}
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#endif
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@ -941,7 +896,6 @@ static void sci_shutdown(struct uart_port *port)
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static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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struct ktermios *old)
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{
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struct sci_port *s = &sci_ports[port->line];
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unsigned int status, baud, smr_val;
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int t = -1;
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@ -983,8 +937,8 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
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udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
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}
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if (likely(s->init_pins))
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s->init_pins(port, termios->c_cflag);
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sci_init_pins(port, termios->c_cflag);
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sci_out(port, SCFCR, (termios->c_cflag & CRTSCTS) ? SCFCR_MCE : 0);
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sci_out(port, SCSCR, SCSCR_INIT(port));
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@ -1025,19 +979,6 @@ static void sci_config_port(struct uart_port *port, int flags)
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port->type = s->type;
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switch (port->type) {
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case PORT_SCI:
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s->init_pins = sci_init_pins_sci;
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break;
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case PORT_SCIF:
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case PORT_SCIFA:
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s->init_pins = sci_init_pins_scif;
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break;
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case PORT_IRDA:
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s->init_pins = sci_init_pins_irda;
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break;
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}
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if (port->flags & UPF_IOREMAP && !port->membase) {
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#if defined(CONFIG_SUPERH64)
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port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF");
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@ -507,18 +507,6 @@ static inline int sci_rxd_in(struct uart_port *port)
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{
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return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
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}
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static inline void set_sh771x_scif_pfc(struct uart_port *port)
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{
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if (port->mapbase == 0xA4400000){
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ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
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ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
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return;
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}
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if (port->mapbase == 0xA4410000){
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ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
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return;
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}
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}
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721)
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static inline int sci_rxd_in(struct uart_port *port)
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