forked from luck/tmp_suning_uos_patched
ioat3: pq support
ioat3.2 adds support for raid6 syndrome generation (xor sum of galois field multiplication products) using up to 8 sources. It can also perform an pq-zero-sum operation to validate whether the syndrome for a given set of sources matches a previously computed syndrome. Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams
parent
9de6fc717b
commit
d69d235b7d
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@ -69,10 +69,12 @@
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#define src_cnt_to_hw(x) ((x) - 2)
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/* provide a lookup table for setting the source address in the base or
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* extended descriptor of an xor descriptor
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* extended descriptor of an xor or pq descriptor
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*/
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static const u8 xor_idx_to_desc __read_mostly = 0xd0;
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static const u8 xor_idx_to_field[] __read_mostly = { 1, 4, 5, 6, 7, 0, 1, 2 };
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static const u8 pq_idx_to_desc __read_mostly = 0xf8;
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static const u8 pq_idx_to_field[] __read_mostly = { 1, 4, 5, 0, 1, 2, 4, 5 };
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static dma_addr_t xor_get_src(struct ioat_raw_descriptor *descs[2], int idx)
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{
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@ -89,6 +91,23 @@ static void xor_set_src(struct ioat_raw_descriptor *descs[2],
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raw->field[xor_idx_to_field[idx]] = addr + offset;
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}
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static dma_addr_t pq_get_src(struct ioat_raw_descriptor *descs[2], int idx)
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{
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struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
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return raw->field[pq_idx_to_field[idx]];
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}
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static void pq_set_src(struct ioat_raw_descriptor *descs[2],
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dma_addr_t addr, u32 offset, u8 coef, int idx)
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{
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struct ioat_pq_descriptor *pq = (struct ioat_pq_descriptor *) descs[0];
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struct ioat_raw_descriptor *raw = descs[pq_idx_to_desc >> idx & 1];
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raw->field[pq_idx_to_field[idx]] = addr + offset;
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pq->coef[idx] = coef;
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}
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static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
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struct ioat_ring_ent *desc, int idx)
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{
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@ -148,6 +167,58 @@ static void ioat3_dma_unmap(struct ioat2_dma_chan *ioat,
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PCI_DMA_FROMDEVICE, flags, 1);
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break;
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}
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case IOAT_OP_PQ_VAL:
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case IOAT_OP_PQ: {
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struct ioat_pq_descriptor *pq = desc->pq;
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struct ioat_ring_ent *ext;
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struct ioat_pq_ext_descriptor *pq_ex = NULL;
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int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
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struct ioat_raw_descriptor *descs[2];
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int i;
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if (src_cnt > 3) {
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ext = ioat2_get_ring_ent(ioat, idx + 1);
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pq_ex = ext->pq_ex;
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}
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/* in the 'continue' case don't unmap the dests as sources */
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if (dmaf_p_disabled_continue(flags))
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src_cnt--;
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else if (dmaf_continue(flags))
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src_cnt -= 3;
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if (!(flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
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descs[0] = (struct ioat_raw_descriptor *) pq;
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descs[1] = (struct ioat_raw_descriptor *) pq_ex;
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for (i = 0; i < src_cnt; i++) {
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dma_addr_t src = pq_get_src(descs, i);
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ioat_unmap(pdev, src - offset, len,
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PCI_DMA_TODEVICE, flags, 0);
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}
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/* the dests are sources in pq validate operations */
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if (pq->ctl_f.op == IOAT_OP_XOR_VAL) {
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if (!(flags & DMA_PREP_PQ_DISABLE_P))
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ioat_unmap(pdev, pq->p_addr - offset,
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len, PCI_DMA_TODEVICE, flags, 0);
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if (!(flags & DMA_PREP_PQ_DISABLE_Q))
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ioat_unmap(pdev, pq->q_addr - offset,
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len, PCI_DMA_TODEVICE, flags, 0);
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break;
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}
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}
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if (!(flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
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if (!(flags & DMA_PREP_PQ_DISABLE_P))
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ioat_unmap(pdev, pq->p_addr - offset, len,
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PCI_DMA_BIDIRECTIONAL, flags, 1);
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if (!(flags & DMA_PREP_PQ_DISABLE_Q))
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ioat_unmap(pdev, pq->q_addr - offset, len,
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PCI_DMA_BIDIRECTIONAL, flags, 1);
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}
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break;
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}
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default:
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dev_err(&pdev->dev, "%s: unknown op type: %#x\n",
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__func__, desc->hw->ctl_f.op);
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@ -164,6 +235,12 @@ static bool desc_has_ext(struct ioat_ring_ent *desc)
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if (src_cnt_to_sw(xor->ctl_f.src_cnt) > 5)
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return true;
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} else if (hw->ctl_f.op == IOAT_OP_PQ ||
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hw->ctl_f.op == IOAT_OP_PQ_VAL) {
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struct ioat_pq_descriptor *pq = desc->pq;
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if (src_cnt_to_sw(pq->ctl_f.src_cnt) > 3)
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return true;
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}
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return false;
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@ -513,6 +590,182 @@ ioat3_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
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src_cnt - 1, len, flags);
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}
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static void
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dump_pq_desc_dbg(struct ioat2_dma_chan *ioat, struct ioat_ring_ent *desc, struct ioat_ring_ent *ext)
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{
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struct device *dev = to_dev(&ioat->base);
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struct ioat_pq_descriptor *pq = desc->pq;
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struct ioat_pq_ext_descriptor *pq_ex = ext ? ext->pq_ex : NULL;
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struct ioat_raw_descriptor *descs[] = { (void *) pq, (void *) pq_ex };
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int src_cnt = src_cnt_to_sw(pq->ctl_f.src_cnt);
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int i;
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dev_dbg(dev, "desc[%d]: (%#llx->%#llx) flags: %#x"
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" sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
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desc_id(desc), (unsigned long long) desc->txd.phys,
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(unsigned long long) (pq_ex ? pq_ex->next : pq->next),
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desc->txd.flags, pq->size, pq->ctl, pq->ctl_f.op, pq->ctl_f.int_en,
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pq->ctl_f.compl_write,
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pq->ctl_f.p_disable ? "" : "p", pq->ctl_f.q_disable ? "" : "q",
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pq->ctl_f.src_cnt);
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for (i = 0; i < src_cnt; i++)
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dev_dbg(dev, "\tsrc[%d]: %#llx coef: %#x\n", i,
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(unsigned long long) pq_get_src(descs, i), pq->coef[i]);
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dev_dbg(dev, "\tP: %#llx\n", pq->p_addr);
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dev_dbg(dev, "\tQ: %#llx\n", pq->q_addr);
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}
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static struct dma_async_tx_descriptor *
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__ioat3_prep_pq_lock(struct dma_chan *c, enum sum_check_flags *result,
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const dma_addr_t *dst, const dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf,
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size_t len, unsigned long flags)
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{
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_ring_ent *compl_desc;
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struct ioat_ring_ent *desc;
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struct ioat_ring_ent *ext;
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size_t total_len = len;
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struct ioat_pq_descriptor *pq;
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struct ioat_pq_ext_descriptor *pq_ex = NULL;
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struct ioat_dma_descriptor *hw;
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u32 offset = 0;
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int num_descs;
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int with_ext;
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int i, s;
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u16 idx;
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u8 op = result ? IOAT_OP_PQ_VAL : IOAT_OP_PQ;
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dev_dbg(to_dev(chan), "%s\n", __func__);
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/* the engine requires at least two sources (we provide
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* at least 1 implied source in the DMA_PREP_CONTINUE case)
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*/
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BUG_ON(src_cnt + dmaf_continue(flags) < 2);
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num_descs = ioat2_xferlen_to_descs(ioat, len);
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/* we need 2x the number of descriptors to cover greater than 3
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* sources
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*/
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if (src_cnt > 3 || flags & DMA_PREP_CONTINUE) {
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with_ext = 1;
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num_descs *= 2;
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} else
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with_ext = 0;
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/* completion writes from the raid engine may pass completion
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* writes from the legacy engine, so we need one extra null
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* (legacy) descriptor to ensure all completion writes arrive in
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* order.
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*/
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if (likely(num_descs) &&
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ioat2_alloc_and_lock(&idx, ioat, num_descs+1) == 0)
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/* pass */;
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else
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return NULL;
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for (i = 0; i < num_descs; i += 1 + with_ext) {
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struct ioat_raw_descriptor *descs[2];
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size_t xfer_size = min_t(size_t, len, 1 << ioat->xfercap_log);
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desc = ioat2_get_ring_ent(ioat, idx + i);
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pq = desc->pq;
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/* save a branch by unconditionally retrieving the
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* extended descriptor pq_set_src() knows to not write
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* to it in the single descriptor case
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*/
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ext = ioat2_get_ring_ent(ioat, idx + i + with_ext);
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pq_ex = ext->pq_ex;
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descs[0] = (struct ioat_raw_descriptor *) pq;
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descs[1] = (struct ioat_raw_descriptor *) pq_ex;
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for (s = 0; s < src_cnt; s++)
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pq_set_src(descs, src[s], offset, scf[s], s);
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/* see the comment for dma_maxpq in include/linux/dmaengine.h */
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if (dmaf_p_disabled_continue(flags))
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pq_set_src(descs, dst[1], offset, 1, s++);
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else if (dmaf_continue(flags)) {
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pq_set_src(descs, dst[0], offset, 0, s++);
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pq_set_src(descs, dst[1], offset, 1, s++);
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pq_set_src(descs, dst[1], offset, 0, s++);
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}
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pq->size = xfer_size;
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pq->p_addr = dst[0] + offset;
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pq->q_addr = dst[1] + offset;
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pq->ctl = 0;
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pq->ctl_f.op = op;
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pq->ctl_f.src_cnt = src_cnt_to_hw(s);
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pq->ctl_f.p_disable = !!(flags & DMA_PREP_PQ_DISABLE_P);
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pq->ctl_f.q_disable = !!(flags & DMA_PREP_PQ_DISABLE_Q);
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len -= xfer_size;
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offset += xfer_size;
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}
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/* last pq descriptor carries the unmap parameters and fence bit */
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desc->txd.flags = flags;
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desc->len = total_len;
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if (result)
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desc->result = result;
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pq->ctl_f.fence = !!(flags & DMA_PREP_FENCE);
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dump_pq_desc_dbg(ioat, desc, ext);
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/* completion descriptor carries interrupt bit */
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compl_desc = ioat2_get_ring_ent(ioat, idx + i);
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compl_desc->txd.flags = flags & DMA_PREP_INTERRUPT;
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hw = compl_desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = !!(flags & DMA_PREP_INTERRUPT);
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hw->ctl_f.compl_write = 1;
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hw->size = NULL_DESC_BUFFER_SIZE;
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dump_desc_dbg(ioat, compl_desc);
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/* we leave the channel locked to ensure in order submission */
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return &desc->txd;
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}
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static struct dma_async_tx_descriptor *
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ioat3_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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unsigned long flags)
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{
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/* handle the single source multiply case from the raid6
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* recovery path
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*/
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if (unlikely((flags & DMA_PREP_PQ_DISABLE_P) && src_cnt == 1)) {
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dma_addr_t single_source[2];
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unsigned char single_source_coef[2];
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BUG_ON(flags & DMA_PREP_PQ_DISABLE_Q);
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single_source[0] = src[0];
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single_source[1] = src[0];
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single_source_coef[0] = scf[0];
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single_source_coef[1] = 0;
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return __ioat3_prep_pq_lock(chan, NULL, dst, single_source, 2,
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single_source_coef, len, flags);
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} else
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return __ioat3_prep_pq_lock(chan, NULL, dst, src, src_cnt, scf,
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len, flags);
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}
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struct dma_async_tx_descriptor *
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ioat3_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
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unsigned int src_cnt, const unsigned char *scf, size_t len,
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enum sum_check_flags *pqres, unsigned long flags)
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{
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/* the cleanup routine only sets bits on validate failure, it
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* does not clear bits on validate success... so clear it here
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*/
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*pqres = 0;
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return __ioat3_prep_pq_lock(chan, pqres, pq, src, src_cnt, scf, len,
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flags);
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}
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static void __devinit ioat3_dma_test_callback(void *dma_async_param)
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{
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struct completion *cmp = dma_async_param;
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@ -822,6 +1075,16 @@ int __devinit ioat3_dma_probe(struct ioatdma_device *device, int dca)
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dma_cap_set(DMA_XOR_VAL, dma->cap_mask);
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dma->device_prep_dma_xor_val = ioat3_prep_xor_val;
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}
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if (cap & IOAT_CAP_PQ) {
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dma_set_maxpq(dma, 8, 0);
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dma->pq_align = 2;
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dma_cap_set(DMA_PQ, dma->cap_mask);
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dma->device_prep_dma_pq = ioat3_prep_pq;
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dma_cap_set(DMA_PQ_VAL, dma->cap_mask);
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dma->device_prep_dma_pq_val = ioat3_prep_pq_val;
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}
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/* -= IOAT ver.3 workarounds =- */
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/* Write CHANERRMSK_INT with 3E07h to mask out the errors
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