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Merge series "ASoC: SOF: DSP core management fixes for 5.10" from Kai Vehmanen <kai.vehmanen@linux.intel.com>:

Browse Source 
This series contains some improvements to how DSP core management
is done in SOF, and adds a distinction between cores managed by
the host versus cores managed by the DSP.

Pierre-Louis Bossart (1):
  ASoC: SOF: Intel: hda-loader: s/master/primary

Ranjani Sridharan (3):
  ASoC: SOF: rename cores_mask to host_managed_cores_mask
  ASoC: SOF: Intel: hda: modify core_power_up/down op
  ASoC: SOF: Intel: remove the  HDA_DSP_CORE_MASK() macro

 sound/soc/sof/intel/apl.c        |  2 +-
 sound/soc/sof/intel/bdw.c        |  2 +-
 sound/soc/sof/intel/byt.c        |  6 +++---
 sound/soc/sof/intel/cnl.c        | 15 ++++-----------
 sound/soc/sof/intel/hda-dsp.c    | 20 +++++++++++++++++---
 sound/soc/sof/intel/hda-loader.c | 11 +++++------
 sound/soc/sof/intel/hda.c        |  2 +-
 sound/soc/sof/intel/hda.h        |  3 ---
 sound/soc/sof/intel/shim.h       |  2 +-
 sound/soc/sof/intel/tgl.c        |  2 +-
 10 files changed, 34 insertions(+), 31 deletions(-)

--
2.27.0
This commit is contained in:
Mark Brown 2020-09-11 15:52:24 +01:00
commit d70a4412e2
No known key found for this signature in database
GPG Key ID: 24D68B725D5487D0
10 changed files with 34 additions and 31 deletions
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2
sound/soc/sof/intel/apl.c
View File

@ -129,7 +129,7 @@ const struct sof_intel_dsp_desc apl_chip_info = {
/* Apollolake */
.cores_num = 2,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) | HDA_DSP_CORE_MASK(1),
.host_managed_cores_mask = GENMASK(1, 0),
.ipc_req = HDA_DSP_REG_HIPCI,
.ipc_req_mask = HDA_DSP_REG_HIPCI_BUSY,
.ipc_ack = HDA_DSP_REG_HIPCIE,

2
sound/soc/sof/intel/bdw.c
View File

@ -655,7 +655,7 @@ EXPORT_SYMBOL_NS(sof_bdw_ops, SND_SOC_SOF_BROADWELL);
const struct sof_intel_dsp_desc bdw_chip_info = {
.cores_num = 1,
.cores_mask = 1,
.host_managed_cores_mask = 1,
};
EXPORT_SYMBOL_NS(bdw_chip_info, SND_SOC_SOF_BROADWELL);

6
sound/soc/sof/intel/byt.c
View File

@ -651,7 +651,7 @@ EXPORT_SYMBOL_NS(sof_tng_ops, SND_SOC_SOF_MERRIFIELD);
const struct sof_intel_dsp_desc tng_chip_info = {
.cores_num = 1,
.cores_mask = 1,
.host_managed_cores_mask = 1,
};
EXPORT_SYMBOL_NS(tng_chip_info, SND_SOC_SOF_MERRIFIELD);
@ -896,7 +896,7 @@ EXPORT_SYMBOL_NS(sof_byt_ops, SND_SOC_SOF_BAYTRAIL);
const struct sof_intel_dsp_desc byt_chip_info = {
.cores_num = 1,
.cores_mask = 1,
.host_managed_cores_mask = 1,
};
EXPORT_SYMBOL_NS(byt_chip_info, SND_SOC_SOF_BAYTRAIL);
@ -976,7 +976,7 @@ EXPORT_SYMBOL_NS(sof_cht_ops, SND_SOC_SOF_BAYTRAIL);
const struct sof_intel_dsp_desc cht_chip_info = {
.cores_num = 1,
.cores_mask = 1,
.host_managed_cores_mask = 1,
};
EXPORT_SYMBOL_NS(cht_chip_info, SND_SOC_SOF_BAYTRAIL);

15
sound/soc/sof/intel/cnl.c
View File

@ -334,10 +334,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
/* Cannonlake */
.cores_num = 4,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3),
.host_managed_cores_mask = GENMASK(3, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
@ -353,10 +350,7 @@ const struct sof_intel_dsp_desc icl_chip_info = {
/* Icelake */
.cores_num = 4,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1) |
HDA_DSP_CORE_MASK(2) |
HDA_DSP_CORE_MASK(3),
.host_managed_cores_mask = GENMASK(3, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
@ -372,7 +366,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
/* Elkhartlake */
.cores_num = 4,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0),
.host_managed_cores_mask = BIT(0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
@ -388,8 +382,7 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
/* Jasperlake */
.cores_num = 2,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0) |
HDA_DSP_CORE_MASK(1),
.host_managed_cores_mask = GENMASK(1, 0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,

20
sound/soc/sof/intel/hda-dsp.c
View File

@ -239,10 +239,15 @@ bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
int ret;
/* return if core is already enabled */
if (hda_dsp_core_is_enabled(sdev, core_mask))
/* restrict core_mask to host managed cores mask */
core_mask &= chip->host_managed_cores_mask;
/* return if core_mask is not valid or cores are already enabled */
if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
return 0;
/* power up */
@ -259,8 +264,17 @@ int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
unsigned int core_mask)
{
struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
const struct sof_intel_dsp_desc *chip = hda->desc;
int ret;
/* restrict core_mask to host managed cores mask */
core_mask &= chip->host_managed_cores_mask;
/* return if core_mask is not valid */
if (!core_mask)
return 0;
/* place core in reset prior to power down */
ret = hda_dsp_core_stall_reset(sdev, core_mask);
if (ret < 0) {
@ -610,7 +624,7 @@ static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
#endif
/* power down DSP */
ret = hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
if (ret < 0) {
dev_err(sdev->dev,
"error: failed to power down core during suspend\n");

11
sound/soc/sof/intel/hda-loader.c
View File

@ -91,7 +91,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
int i;
/* step 1: power up corex */
ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
ret = hda_dsp_core_power_up(sdev, chip->host_managed_cores_mask);
if (ret < 0) {
if (iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev, "error: dsp core 0/1 power up failed\n");
@ -114,7 +114,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
((stream_tag - 1) << 9)));
/* step 3: unset core 0 reset state & unstall/run core 0 */
ret = hda_dsp_core_run(sdev, HDA_DSP_CORE_MASK(0));
ret = hda_dsp_core_run(sdev, BIT(0));
if (ret < 0) {
if (iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev,
@ -146,8 +146,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
chip->ipc_ack_mask);
/* step 5: power down corex */
ret = hda_dsp_core_power_down(sdev,
chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
ret = hda_dsp_core_power_down(sdev, chip->host_managed_cores_mask & ~(BIT(0)));
if (ret < 0) {
if (iteration == HDA_FW_BOOT_ATTEMPTS)
dev_err(sdev->dev,
@ -176,7 +175,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, int stream_tag, int iteration)
err:
hda_dsp_dump(sdev, SOF_DBG_REGS | SOF_DBG_PCI | SOF_DBG_MBOX);
hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
return ret;
}
@ -427,7 +426,7 @@ int hda_dsp_cl_boot_firmware(struct snd_sof_dev *sdev)
}
/*
* return master core id if both fw copy
* return primary core id if both fw copy
* and stream clean up are successful
*/
if (!ret)

2
sound/soc/sof/intel/hda.c
View File

@ -928,7 +928,7 @@ int hda_dsp_remove(struct snd_sof_dev *sdev)
/* disable cores */
if (chip)
hda_dsp_core_reset_power_down(sdev, chip->cores_mask);
hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
/* disable DSP */
snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,

3
sound/soc/sof/intel/hda.h
View File

@ -305,9 +305,6 @@
#define HDA_DSP_ADSPCS_CPA_SHIFT 24
#define HDA_DSP_ADSPCS_CPA_MASK(cm) ((cm) << HDA_DSP_ADSPCS_CPA_SHIFT)
/* Mask for a given core index, c = 0.. number of supported cores - 1 */
#define HDA_DSP_CORE_MASK(c) BIT(c)
/*
* Mask for a given number of cores
* nc = number of supported cores

2
sound/soc/sof/intel/shim.h
View File

@ -154,7 +154,7 @@
/* DSP hardware descriptor */
struct sof_intel_dsp_desc {
int cores_num;
int cores_mask;
int host_managed_cores_mask;
int init_core_mask; /* cores available after fw boot */
int ipc_req;
int ipc_req_mask;

2
sound/soc/sof/intel/tgl.c
View File

@ -124,7 +124,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
/* Tigerlake */
.cores_num = 4,
.init_core_mask = 1,
.cores_mask = HDA_DSP_CORE_MASK(0),
.host_managed_cores_mask = BIT(0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,