AcoSail/kernel_optimize_test
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sh: Add cache definitions for SH-5.

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Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Paul Mundt 2007-11-08 19:00:27 +09:00
parent a096a7e476
commit d752542ade
1 changed files with 7 additions and 52 deletions
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59
include/asm-sh64/cache.h → include/asm-sh/cpu-sh5/cache.h
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@ -12,22 +12,16 @@
* Copyright (C) 2003, 2004 Paul Mundt * Copyright (C) 2003, 2004 Paul Mundt
* *
*/ */
#include <asm/cacheflush.h>
#define L1_CACHE_SHIFT 5 #define L1_CACHE_SHIFT 5
/* bytes per L1 cache line */
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_ALIGN_MASK (~(L1_CACHE_BYTES - 1))
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES - 1)) & L1_CACHE_ALIGN_MASK)
#define L1_CACHE_SIZE_BYTES (L1_CACHE_BYTES << 10)
#ifdef MODULE /* Valid and Dirty bits */
#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES))) #define SH_CACHE_VALID (1LL<<0)
#else #define SH_CACHE_UPDATED (1LL<<57)
#define __cacheline_aligned \
__attribute__((__aligned__(L1_CACHE_BYTES), \ /* Cache flags */
__section__(".data.cacheline_aligned"))) #define SH_CACHE_MODE_WT (1LL<<0)
#endif #define SH_CACHE_MODE_WB (1LL<<1)
/* /*
* Control Registers. * Control Registers.
@ -58,7 +52,6 @@
#define OCCR1_NOLOCK 0x0 /* Set No Locking */ #define OCCR1_NOLOCK 0x0 /* Set No Locking */
/* /*
* SH-5 * SH-5
* A bit of description here, for neff=32. * A bit of description here, for neff=32.
@ -77,43 +70,6 @@
* *
*/ */
/* Valid and Dirty bits */
#define SH_CACHE_VALID (1LL<<0)
#define SH_CACHE_UPDATED (1LL<<57)
/* Cache flags */
#define SH_CACHE_MODE_WT (1LL<<0)
#define SH_CACHE_MODE_WB (1LL<<1)
#ifndef __ASSEMBLY__
/*
* Cache information structure.
*
* Defined for both I and D cache, per-processor.
*/
struct cache_info {
unsigned int ways;
unsigned int sets;
unsigned int linesz;
unsigned int way_shift;
unsigned int entry_shift;
unsigned int set_shift;
unsigned int way_step_shift;
unsigned int asid_shift;
unsigned int way_ofs;
unsigned int asid_mask;
unsigned int idx_mask;
unsigned int epn_mask;
unsigned long flags;
};
#endif /* __ASSEMBLY__ */
/* Instruction cache */ /* Instruction cache */
#define CACHE_IC_ADDRESS_ARRAY 0x01000000 #define CACHE_IC_ADDRESS_ARRAY 0x01000000
@ -130,7 +86,6 @@ struct cache_info {
/* Mask to select synonym bit(s) */ /* Mask to select synonym bit(s) */
#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT) #define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
/* /*
* Instruction cache can't be invalidated based on physical addresses. * Instruction cache can't be invalidated based on physical addresses.
* No Instruction Cache defines required, then. * No Instruction Cache defines required, then.