forked from luck/tmp_suning_uos_patched
drm/radeon/kms: clean up some magic numbers
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@gmail.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
9453d62118
commit
d75ee3be44
@ -1031,8 +1031,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
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WREG32(RADEON_CP_CSQ_MODE,
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REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
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REG_SET(RADEON_INDIRECT1_START, indirect1_start));
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WREG32(0x718, 0);
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WREG32(0x744, 0x00004D4D);
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WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
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WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
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WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
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radeon_ring_start(rdev);
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r = radeon_ring_test(rdev);
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@ -2347,10 +2347,10 @@ void r100_vga_set_state(struct radeon_device *rdev, bool state)
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temp = RREG32(RADEON_CONFIG_CNTL);
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if (state == false) {
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temp &= ~(1<<8);
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temp |= (1<<9);
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temp &= ~RADEON_CFG_VGA_RAM_EN;
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temp |= RADEON_CFG_VGA_IO_DIS;
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} else {
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temp &= ~(1<<9);
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temp &= ~RADEON_CFG_VGA_IO_DIS;
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}
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WREG32(RADEON_CONFIG_CNTL, temp);
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}
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@ -69,6 +69,9 @@ void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
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mb();
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}
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#define R300_PTE_WRITEABLE (1 << 2)
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#define R300_PTE_READABLE (1 << 3)
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int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
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@ -78,7 +81,7 @@ int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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}
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addr = (lower_32_bits(addr) >> 8) |
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((upper_32_bits(addr) & 0xff) << 24) |
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0xc;
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R300_PTE_WRITEABLE | R300_PTE_READABLE;
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/* on x86 we want this to be CPU endian, on powerpc
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* on powerpc without HW swappers, it'll get swapped on way
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* into VRAM - so no need for cpu_to_le32 on VRAM tables */
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@ -135,7 +138,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
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WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
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WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
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/* Clear error */
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WREG32_PCIE(0x18, 0);
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WREG32_PCIE(RADEON_PCIE_TX_GART_ERROR, 0);
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tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
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tmp |= RADEON_PCIE_TX_GART_EN;
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tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
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@ -96,7 +96,7 @@ void r420_pipes_init(struct radeon_device *rdev)
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"programming pipes. Bad things might happen.\n");
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}
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/* get max number of pipes */
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gb_pipe_select = RREG32(0x402C);
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gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
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num_pipes = ((gb_pipe_select >> 12) & 3) + 1;
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/* SE chips have 1 pipe */
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@ -79,8 +79,8 @@ static void r520_gpu_init(struct radeon_device *rdev)
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WREG32(0x4128, 0xFF);
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}
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r420_pipes_init(rdev);
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gb_pipe_select = RREG32(0x402C);
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tmp = RREG32(0x170C);
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gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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pipe_select_current = (tmp >> 2) & 3;
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tmp = (1 << pipe_select_current) |
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(((gb_pipe_select >> 8) & 0xF) << 4);
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@ -375,6 +375,8 @@
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#define RADEON_CONFIG_APER_SIZE 0x0108
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#define RADEON_CONFIG_BONDS 0x00e8
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#define RADEON_CONFIG_CNTL 0x00e0
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# define RADEON_CFG_VGA_RAM_EN (1 << 8)
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# define RADEON_CFG_VGA_IO_DIS (1 << 9)
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# define RADEON_CFG_ATI_REV_A11 (0 << 16)
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# define RADEON_CFG_ATI_REV_A12 (1 << 16)
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# define RADEON_CFG_ATI_REV_A13 (2 << 16)
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@ -203,6 +203,9 @@ void rs400_gart_fini(struct radeon_device *rdev)
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radeon_gart_table_ram_free(rdev);
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}
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#define RS400_PTE_WRITEABLE (1 << 2)
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#define RS400_PTE_READABLE (1 << 3)
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int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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{
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uint32_t entry;
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@ -213,7 +216,7 @@ int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
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entry = (lower_32_bits(addr) & PAGE_MASK) |
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((upper_32_bits(addr) & 0xff) << 4) |
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0xc;
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RS400_PTE_WRITEABLE | RS400_PTE_READABLE;
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entry = cpu_to_le32(entry);
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rdev->gart.table.ram.ptr[i] = entry;
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return 0;
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@ -226,8 +229,8 @@ int rs400_mc_wait_for_idle(struct radeon_device *rdev)
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for (i = 0; i < rdev->usec_timeout; i++) {
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/* read MC_STATUS */
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tmp = RREG32(0x0150);
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if (tmp & (1 << 2)) {
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tmp = RREG32(RADEON_MC_STATUS);
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if (tmp & RADEON_MC_IDLE) {
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return 0;
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}
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DRM_UDELAY(1);
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@ -241,7 +244,7 @@ void rs400_gpu_init(struct radeon_device *rdev)
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r420_pipes_init(rdev);
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if (rs400_mc_wait_for_idle(rdev)) {
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printk(KERN_WARNING "rs400: Failed to wait MC idle while "
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"programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
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"programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS));
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}
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}
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@ -300,9 +303,9 @@ static int rs400_debugfs_gart_info(struct seq_file *m, void *data)
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seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp);
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tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION);
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seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp);
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tmp = RREG32_MC(0x100);
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tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION);
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seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp);
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tmp = RREG32(0x134);
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tmp = RREG32(RS690_HDP_FB_LOCATION);
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seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp);
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} else {
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tmp = RREG32(RADEON_AGP_BASE);
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@ -69,13 +69,13 @@ void rv515_ring_start(struct radeon_device *rdev)
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ISYNC_CPSCRATCH_IDLEGUI);
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radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
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radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
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radeon_ring_write(rdev, PACKET0(0x170C, 0));
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radeon_ring_write(rdev, 1 << 31);
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radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
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radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
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radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
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radeon_ring_write(rdev, 0);
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radeon_ring_write(rdev, PACKET0(0x42C8, 0));
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radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0));
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radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
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radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
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radeon_ring_write(rdev, 0);
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@ -153,8 +153,8 @@ void rv515_gpu_init(struct radeon_device *rdev)
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}
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rv515_vga_render_disable(rdev);
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r420_pipes_init(rdev);
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gb_pipe_select = RREG32(0x402C);
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tmp = RREG32(0x170C);
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gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
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tmp = RREG32(R300_DST_PIPE_CONFIG);
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pipe_select_current = (tmp >> 2) & 3;
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tmp = (1 << pipe_select_current) |
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(((gb_pipe_select >> 8) & 0xF) << 4);
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