forked from luck/tmp_suning_uos_patched
drm/amd/display: Add 170Mpix/sec DSC throughput support
[why] It was missing, although defined in DP spec [how] - Add handling of this value to DSC code - Also remove unused file dsc_helpers.c Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Nikola Cornij
Alex Deucher
parent
c703e753c8
commit
d7cd0e053b
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@ -74,6 +74,12 @@ static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *lin
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static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput)
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{
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switch (dpcd_throughput) {
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case DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED:
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*throughput = 0;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_170:
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*throughput = 170;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_340:
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*throughput = 340;
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break;
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@ -170,7 +176,7 @@ static void get_dsc_enc_caps(
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/* Returns 'false' if no intersection was found for at least one capablity.
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* It also implicitly validates some sink caps against invalid value of zero.
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*/
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static bool dc_intersect_dsc_caps(
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static bool intersect_dsc_caps(
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const struct dsc_dec_dpcd_caps *dsc_sink_caps,
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const struct dsc_enc_caps *dsc_enc_caps,
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enum dc_pixel_encoding pixel_encoding,
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@ -537,7 +543,7 @@ static bool setup_dsc_config(
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goto done;
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// Intersect decoder with encoder DSC caps and validate DSC settings
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is_dsc_possible = dc_intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);
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is_dsc_possible = intersect_dsc_caps(dsc_sink_caps, dsc_enc_caps, timing->pixel_encoding, &dsc_common_caps);
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if (!is_dsc_possible)
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goto done;
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@ -1,243 +0,0 @@
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/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
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#include "dc.h"
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#include "dsc.h"
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#include "dc_hw_types.h"
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#include <drm/drm_dp_helper.h>
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#define DC_LOGGER \
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dsc->ctx->logger
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static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size);
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static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *line_buff_bit_depth);
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static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput);
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static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bpp_increment_div);
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void dsc_optc_config_log(struct display_stream_compressor *dsc,
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struct dsc_optc_config *config)
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{
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DC_LOG_DSC("Setting optc DSC config at DSC inst %d", dsc->inst);
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DC_LOG_DSC("\n\tbytes_per_pixel %d\n\tis_pixel_format_444 %d\n\tslice_width %d",
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config->bytes_per_pixel,
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config->is_pixel_format_444, config->slice_width);
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}
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void dsc_config_log(struct display_stream_compressor *dsc,
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const struct dsc_config *config)
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{
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DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst);
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DC_LOG_DSC("\n\tnum_slices_h %d\n\tnum_slices_v %d\n\tbits_per_pixel %d\n\tcolor_depth %d",
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config->dc_dsc_cfg.num_slices_h,
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config->dc_dsc_cfg.num_slices_v,
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config->dc_dsc_cfg.bits_per_pixel,
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config->color_depth);
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}
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bool dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_data, struct dsc_dec_dpcd_caps *dsc_sink_caps)
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{
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dsc_sink_caps->is_dsc_supported = (dpcd_dsc_data[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED) != 0;
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if (!dsc_sink_caps->is_dsc_supported)
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return true;
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dsc_sink_caps->dsc_version = dpcd_dsc_data[DP_DSC_REV - DP_DSC_SUPPORT];
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{
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int buff_block_size;
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int buff_size;
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if (!dsc_buff_block_size_from_dpcd(dpcd_dsc_data[DP_DSC_RC_BUF_BLK_SIZE - DP_DSC_SUPPORT], &buff_block_size))
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return false;
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buff_size = dpcd_dsc_data[DP_DSC_RC_BUF_SIZE - DP_DSC_SUPPORT] + 1;
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dsc_sink_caps->rc_buffer_size = buff_size * buff_block_size;
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}
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dsc_sink_caps->slice_caps1.raw = dpcd_dsc_data[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
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if (!dsc_line_buff_depth_from_dpcd(dpcd_dsc_data[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT], &dsc_sink_caps->lb_bit_depth))
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return false;
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dsc_sink_caps->is_block_pred_supported =
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(dpcd_dsc_data[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_BLK_PREDICTION_IS_SUPPORTED) != 0;
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dsc_sink_caps->edp_max_bits_per_pixel =
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dpcd_dsc_data[DP_DSC_MAX_BITS_PER_PIXEL_LOW - DP_DSC_SUPPORT] |
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dpcd_dsc_data[DP_DSC_MAX_BITS_PER_PIXEL_HI - DP_DSC_SUPPORT] << 8;
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dsc_sink_caps->color_formats.raw = dpcd_dsc_data[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT];
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dsc_sink_caps->color_depth.raw = dpcd_dsc_data[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
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{
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int dpcd_throughput = dpcd_dsc_data[DP_DSC_PEAK_THROUGHPUT - DP_DSC_SUPPORT];
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if (!dsc_throughput_from_dpcd(dpcd_throughput & DP_DSC_THROUGHPUT_MODE_0_MASK, &dsc_sink_caps->throughput_mode_0_mps))
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return false;
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dpcd_throughput = (dpcd_throughput & DP_DSC_THROUGHPUT_MODE_1_MASK) >> DP_DSC_THROUGHPUT_MODE_1_SHIFT;
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if (!dsc_throughput_from_dpcd(dpcd_throughput, &dsc_sink_caps->throughput_mode_1_mps))
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return false;
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}
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dsc_sink_caps->max_slice_width = dpcd_dsc_data[DP_DSC_MAX_SLICE_WIDTH - DP_DSC_SUPPORT] * 320;
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dsc_sink_caps->slice_caps2.raw = dpcd_dsc_data[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
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if (!dsc_bpp_increment_div_from_dpcd(dpcd_dsc_data[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT], &dsc_sink_caps->bpp_increment_div))
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return false;
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return true;
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}
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/* This module's internal functions */
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static bool dsc_buff_block_size_from_dpcd(int dpcd_buff_block_size, int *buff_block_size)
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{
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switch (dpcd_buff_block_size) {
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case DP_DSC_RC_BUF_BLK_SIZE_1:
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*buff_block_size = 1024;
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break;
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case DP_DSC_RC_BUF_BLK_SIZE_4:
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*buff_block_size = 4 * 1024;
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break;
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case DP_DSC_RC_BUF_BLK_SIZE_16:
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*buff_block_size = 16 * 1024;
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break;
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case DP_DSC_RC_BUF_BLK_SIZE_64:
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*buff_block_size = 64 * 1024;
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break;
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default: {
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dm_error("%s: DPCD DSC buffer size not recoginzed.\n", __func__);
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return false;
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}
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}
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return true;
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}
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static bool dsc_line_buff_depth_from_dpcd(int dpcd_line_buff_bit_depth, int *line_buff_bit_depth)
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{
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if (0 <= dpcd_line_buff_bit_depth && dpcd_line_buff_bit_depth <= 7)
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*line_buff_bit_depth = dpcd_line_buff_bit_depth + 9;
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else if (dpcd_line_buff_bit_depth == 8)
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*line_buff_bit_depth = 8;
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else {
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dm_error("%s: DPCD DSC buffer depth not recoginzed.\n", __func__);
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return false;
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}
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return true;
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}
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static bool dsc_throughput_from_dpcd(int dpcd_throughput, int *throughput)
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{
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switch (dpcd_throughput) {
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case DP_DSC_THROUGHPUT_MODE_0_340:
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*throughput = 340;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_400:
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*throughput = 400;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_450:
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*throughput = 450;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_500:
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*throughput = 500;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_550:
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*throughput = 550;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_600:
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*throughput = 600;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_650:
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*throughput = 650;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_700:
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*throughput = 700;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_750:
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*throughput = 750;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_800:
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*throughput = 800;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_850:
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*throughput = 850;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_900:
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*throughput = 900;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_950:
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*throughput = 950;
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break;
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case DP_DSC_THROUGHPUT_MODE_0_1000:
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*throughput = 1000;
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break;
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default: {
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dm_error("%s: DPCD DSC througput mode not recoginzed.\n", __func__);
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return false;
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}
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}
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return true;
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}
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static bool dsc_bpp_increment_div_from_dpcd(int bpp_increment_dpcd, uint32_t *bpp_increment_div)
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{
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switch (bpp_increment_dpcd) {
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case 0:
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*bpp_increment_div = 16;
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break;
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case 1:
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*bpp_increment_div = 8;
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break;
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case 2:
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*bpp_increment_div = 4;
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break;
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case 3:
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*bpp_increment_div = 2;
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break;
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case 4:
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*bpp_increment_div = 1;
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break;
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default: {
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dm_error("%s: DPCD DSC bits-per-pixel increment not recoginzed.\n", __func__);
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return false;
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}
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}
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return true;
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}
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#endif // CONFIG_DRM_AMD_DC_DSC_SUPPORT
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@ -249,6 +249,7 @@
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#define DP_DSC_PEAK_THROUGHPUT 0x06B
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# define DP_DSC_THROUGHPUT_MODE_0_MASK (0xf << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_SHIFT 0
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# define DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED 0
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# define DP_DSC_THROUGHPUT_MODE_0_340 (1 << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_400 (2 << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_450 (3 << 0)
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@ -263,8 +264,10 @@
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# define DP_DSC_THROUGHPUT_MODE_0_900 (12 << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_950 (13 << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_1000 (14 << 0)
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# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_MASK (0xf << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_SHIFT 4
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# define DP_DSC_THROUGHPUT_MODE_1_UPSUPPORTED 0
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# define DP_DSC_THROUGHPUT_MODE_1_340 (1 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_400 (2 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_450 (3 << 4)
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@ -279,6 +282,7 @@
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# define DP_DSC_THROUGHPUT_MODE_1_900 (12 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_950 (13 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_1000 (14 << 4)
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# define DP_DSC_THROUGHPUT_MODE_1_170 (15 << 4)
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#define DP_DSC_MAX_SLICE_WIDTH 0x06C
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#define DP_DSC_MIN_SLICE_WIDTH_VALUE 2560
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