forked from luck/tmp_suning_uos_patched
ARM: 6383/1: Implement phys_mem_access_prot() to avoid attributes aliasing
ARMv7 onwards requires that there are no aliases to the same physical location using different memory types (i.e. Normal vs Strongly Ordered). Access to SO mappings when the unaligned accesses are handled in hardware is also Unpredictable (pgprot_noncached() mappings in user space). The /dev/mem driver requires uncached mappings with O_SYNC. The patch implements the phys_mem_access_prot() function which generates Strongly Ordered memory attributes if !pfn_valid() (independent of O_SYNC) and Normal Noncacheable (writecombine) if O_SYNC. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -317,6 +317,10 @@ static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
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#define __HAVE_PHYS_MEM_ACCESS_PROT
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struct file;
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extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot);
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#else
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#define pgprot_dmacoherent(prot) \
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__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
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@ -15,6 +15,7 @@
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#include <linux/nodemask.h>
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#include <linux/memblock.h>
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#include <linux/sort.h>
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#include <linux/fs.h>
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#include <asm/cputype.h>
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#include <asm/sections.h>
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@ -498,6 +499,19 @@ static void __init build_mem_type_table(void)
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}
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}
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#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
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pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
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unsigned long size, pgprot_t vma_prot)
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{
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if (!pfn_valid(pfn))
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return pgprot_noncached(vma_prot);
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else if (file->f_flags & O_SYNC)
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return pgprot_writecombine(vma_prot);
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return vma_prot;
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}
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EXPORT_SYMBOL(phys_mem_access_prot);
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#endif
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#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
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static void __init *early_alloc(unsigned long sz)
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