forked from luck/tmp_suning_uos_patched
crypto: remove uses of __constant_{endian} helpers
Base versions handle constant folding just fine. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Harvey Harrison
Herbert Xu
parent
664134d291
commit
dad3df2044
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@ -73,7 +73,7 @@ do { \
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* /afs/transarc.com/public/afsps/afs.rel31b.export-src/rxkad/sboxes.h
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*/
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#undef Z
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#define Z(x) __constant_cpu_to_be32(x << 3)
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#define Z(x) cpu_to_be32(x << 3)
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static const __be32 sbox0[256] = {
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Z(0xea), Z(0x7f), Z(0xb2), Z(0x64), Z(0x9d), Z(0xb0), Z(0xd9), Z(0x11),
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Z(0xcd), Z(0x86), Z(0x86), Z(0x91), Z(0x0a), Z(0xb2), Z(0x93), Z(0x06),
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@ -110,7 +110,7 @@ static const __be32 sbox0[256] = {
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};
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#undef Z
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#define Z(x) __constant_cpu_to_be32((x << 27) | (x >> 5))
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#define Z(x) cpu_to_be32((x << 27) | (x >> 5))
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static const __be32 sbox1[256] = {
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Z(0x77), Z(0x14), Z(0xa6), Z(0xfe), Z(0xb2), Z(0x5e), Z(0x8c), Z(0x3e),
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Z(0x67), Z(0x6c), Z(0xa1), Z(0x0d), Z(0xc2), Z(0xa2), Z(0xc1), Z(0x85),
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@ -147,7 +147,7 @@ static const __be32 sbox1[256] = {
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};
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#undef Z
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#define Z(x) __constant_cpu_to_be32(x << 11)
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#define Z(x) cpu_to_be32(x << 11)
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static const __be32 sbox2[256] = {
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Z(0xf0), Z(0x37), Z(0x24), Z(0x53), Z(0x2a), Z(0x03), Z(0x83), Z(0x86),
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Z(0xd1), Z(0xec), Z(0x50), Z(0xf0), Z(0x42), Z(0x78), Z(0x2f), Z(0x6d),
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@ -184,7 +184,7 @@ static const __be32 sbox2[256] = {
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};
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#undef Z
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#define Z(x) __constant_cpu_to_be32(x << 19)
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#define Z(x) cpu_to_be32(x << 19)
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static const __be32 sbox3[256] = {
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Z(0xa9), Z(0x2a), Z(0x48), Z(0x51), Z(0x84), Z(0x7e), Z(0x49), Z(0xe2),
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Z(0xb5), Z(0xb7), Z(0x42), Z(0x33), Z(0x7d), Z(0x5d), Z(0xa6), Z(0x12),
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@ -134,34 +134,34 @@
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*/
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/* written back when done */
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#define DESC_HDR_DONE __constant_cpu_to_be32(0xff000000)
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#define DESC_HDR_LO_ICCR1_MASK __constant_cpu_to_be32(0x00180000)
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#define DESC_HDR_LO_ICCR1_PASS __constant_cpu_to_be32(0x00080000)
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#define DESC_HDR_LO_ICCR1_FAIL __constant_cpu_to_be32(0x00100000)
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#define DESC_HDR_DONE cpu_to_be32(0xff000000)
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#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
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#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
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#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
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/* primary execution unit select */
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#define DESC_HDR_SEL0_MASK __constant_cpu_to_be32(0xf0000000)
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#define DESC_HDR_SEL0_AFEU __constant_cpu_to_be32(0x10000000)
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#define DESC_HDR_SEL0_DEU __constant_cpu_to_be32(0x20000000)
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#define DESC_HDR_SEL0_MDEUA __constant_cpu_to_be32(0x30000000)
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#define DESC_HDR_SEL0_MDEUB __constant_cpu_to_be32(0xb0000000)
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#define DESC_HDR_SEL0_RNG __constant_cpu_to_be32(0x40000000)
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#define DESC_HDR_SEL0_PKEU __constant_cpu_to_be32(0x50000000)
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#define DESC_HDR_SEL0_AESU __constant_cpu_to_be32(0x60000000)
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#define DESC_HDR_SEL0_KEU __constant_cpu_to_be32(0x70000000)
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#define DESC_HDR_SEL0_CRCU __constant_cpu_to_be32(0x80000000)
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#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
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#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
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#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
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#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
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#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
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#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
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#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
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#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
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#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
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#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
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/* primary execution unit mode (MODE0) and derivatives */
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#define DESC_HDR_MODE0_ENCRYPT __constant_cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_AESU_CBC __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_DEU_CBC __constant_cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_DEU_3DES __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_INIT __constant_cpu_to_be32(0x01000000)
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#define DESC_HDR_MODE0_MDEU_HMAC __constant_cpu_to_be32(0x00800000)
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#define DESC_HDR_MODE0_MDEU_PAD __constant_cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_MDEU_MD5 __constant_cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_SHA256 __constant_cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
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#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
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#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
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@ -170,19 +170,19 @@
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DESC_HDR_MODE0_MDEU_HMAC)
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/* secondary execution unit select (SEL1) */
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#define DESC_HDR_SEL1_MASK __constant_cpu_to_be32(0x000f0000)
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#define DESC_HDR_SEL1_MDEUA __constant_cpu_to_be32(0x00030000)
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#define DESC_HDR_SEL1_MDEUB __constant_cpu_to_be32(0x000b0000)
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#define DESC_HDR_SEL1_CRCU __constant_cpu_to_be32(0x00080000)
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#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
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#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
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#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
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#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
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/* secondary execution unit mode (MODE1) and derivatives */
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#define DESC_HDR_MODE1_MDEU_CICV __constant_cpu_to_be32(0x00004000)
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#define DESC_HDR_MODE1_MDEU_INIT __constant_cpu_to_be32(0x00001000)
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#define DESC_HDR_MODE1_MDEU_HMAC __constant_cpu_to_be32(0x00000800)
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#define DESC_HDR_MODE1_MDEU_PAD __constant_cpu_to_be32(0x00000400)
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#define DESC_HDR_MODE1_MDEU_MD5 __constant_cpu_to_be32(0x00000200)
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#define DESC_HDR_MODE1_MDEU_SHA256 __constant_cpu_to_be32(0x00000100)
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#define DESC_HDR_MODE1_MDEU_SHA1 __constant_cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
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#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
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#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
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#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
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#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
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#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
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#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
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@ -191,16 +191,16 @@
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DESC_HDR_MODE1_MDEU_HMAC)
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/* direction of overall data flow (DIR) */
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#define DESC_HDR_DIR_INBOUND __constant_cpu_to_be32(0x00000002)
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#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
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/* request done notification (DN) */
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#define DESC_HDR_DONE_NOTIFY __constant_cpu_to_be32(0x00000001)
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#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
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/* descriptor types */
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#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP __constant_cpu_to_be32(0 << 3)
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#define DESC_HDR_TYPE_IPSEC_ESP __constant_cpu_to_be32(1 << 3)
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#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU __constant_cpu_to_be32(2 << 3)
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#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU __constant_cpu_to_be32(4 << 3)
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#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
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#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
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#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
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#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
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/* link table extent field bits */
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#define DESC_PTR_LNKTBL_JUMP 0x80
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