forked from luck/tmp_suning_uos_patched
qcom clock changes for 3.18
Some fixes for the IPQ driver and some code consolidation and refactoring. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABCAAGBQJUIJ/oAAoJENidgRMleOc94WoP/1f7pk2ZWZzLPF1WRDwff0Ng 71g5iRYhzwxHvM5bgMLBtBRaDGY9Q2aUPPAfJNYF76foR3CPwB0XPVPk+vNaJGl7 Yxwighg9wNz904dVKsEeErmdaHZKzQCtser6/aj43EWRMfwoT9OLgwKJApVaVoUz bTMEKLN/HEcp/FECShulfvk9qnvMCKckxuRidl01UwXv/Ha3Em84MkxAGJZmbGha RGcvlkU5E06x6FEhtWM/lk2UoFTX1D2+tIugt05q3eUSvt93zy/9tGYqiaeHKO5w AaYS09qYNCrbW6LovlATv6hecwfVvMliT6uz9us+dk2vzqdtjcwaXldOouWr/7H2 M62aQIUJg7QpS5p28WnUcNhv4rJUT7+sRrGmsgVRx0Amn/97Ed/v62y9cyPjWsou 6QKehahf/Kq690M/jWU3vkanWvszFHZ/dw+GsAPSlx9kHZAUbSqim1x/zlaKZ+S7 nh3v6glwlhFCogdBDOZr1nPiFFGK2VESukFmWU12qA0huqEQ7rh0eLB2HBwN8neu Leli/e7vnjcuhqjixqlrZGXv/O8cU8EHW1VCtP4FyiLZTBVe7nlWMARdgCYcauC/ cWNsO6FlU6y0qqpFCZ+p+nUU2+/n1tnfzzS/j55pzwp6keqt5lJcUL/yHOP8mhez ewruBUdui4U1gFjazfj0 =fPIM -----END PGP SIGNATURE----- Merge tag 'qcom-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next qcom clock changes for 3.18 Some fixes for the IPQ driver and some code consolidation and refactoring.
This commit is contained in:
Mike Turquette
commit
db0bcc33a8
|
|
@ -97,7 +97,7 @@ static unsigned long
|
|||
clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
u32 l, m, n;
|
||||
u32 l, m, n, config;
|
||||
unsigned long rate;
|
||||
u64 tmp;
|
||||
|
||||
|
|
@ -116,13 +116,79 @@ clk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
do_div(tmp, n);
|
||||
rate += tmp;
|
||||
}
|
||||
if (pll->post_div_width) {
|
||||
regmap_read(pll->clkr.regmap, pll->config_reg, &config);
|
||||
config >>= pll->post_div_shift;
|
||||
config &= BIT(pll->post_div_width) - 1;
|
||||
rate /= config + 1;
|
||||
}
|
||||
|
||||
return rate;
|
||||
}
|
||||
|
||||
static const
|
||||
struct pll_freq_tbl *find_freq(const struct pll_freq_tbl *f, unsigned long rate)
|
||||
{
|
||||
if (!f)
|
||||
return NULL;
|
||||
|
||||
for (; f->freq; f++)
|
||||
if (rate <= f->freq)
|
||||
return f;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static long
|
||||
clk_pll_determine_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *p_rate, struct clk **p)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
const struct pll_freq_tbl *f;
|
||||
|
||||
f = find_freq(pll->freq_tbl, rate);
|
||||
if (!f)
|
||||
return clk_pll_recalc_rate(hw, *p_rate);
|
||||
|
||||
return f->freq;
|
||||
}
|
||||
|
||||
static int
|
||||
clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long p_rate)
|
||||
{
|
||||
struct clk_pll *pll = to_clk_pll(hw);
|
||||
const struct pll_freq_tbl *f;
|
||||
bool enabled;
|
||||
u32 mode;
|
||||
u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;
|
||||
|
||||
f = find_freq(pll->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);
|
||||
enabled = (mode & enable_mask) == enable_mask;
|
||||
|
||||
if (enabled)
|
||||
clk_pll_disable(hw);
|
||||
|
||||
regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);
|
||||
regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);
|
||||
regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);
|
||||
regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);
|
||||
|
||||
if (enabled)
|
||||
clk_pll_enable(hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct clk_ops clk_pll_ops = {
|
||||
.enable = clk_pll_enable,
|
||||
.disable = clk_pll_disable,
|
||||
.recalc_rate = clk_pll_recalc_rate,
|
||||
.determine_rate = clk_pll_determine_rate,
|
||||
.set_rate = clk_pll_set_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_pll_ops);
|
||||
|
||||
|
|
|
|||
|
|
@ -17,6 +17,21 @@
|
|||
#include <linux/clk-provider.h>
|
||||
#include "clk-regmap.h"
|
||||
|
||||
/**
|
||||
* struct pll_freq_tbl - PLL frequency table
|
||||
* @l: L value
|
||||
* @m: M value
|
||||
* @n: N value
|
||||
* @ibits: internal values
|
||||
*/
|
||||
struct pll_freq_tbl {
|
||||
unsigned long freq;
|
||||
u16 l;
|
||||
u16 m;
|
||||
u16 n;
|
||||
u32 ibits;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_pll - phase locked loop (PLL)
|
||||
* @l_reg: L register
|
||||
|
|
@ -26,6 +41,7 @@
|
|||
* @mode_reg: mode register
|
||||
* @status_reg: status register
|
||||
* @status_bit: ANDed with @status_reg to determine if PLL is enabled
|
||||
* @freq_tbl: PLL frequency table
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
*/
|
||||
struct clk_pll {
|
||||
|
|
@ -36,6 +52,10 @@ struct clk_pll {
|
|||
u32 mode_reg;
|
||||
u32 status_reg;
|
||||
u8 status_bit;
|
||||
u8 post_div_width;
|
||||
u8 post_div_shift;
|
||||
|
||||
const struct pll_freq_tbl *freq_tbl;
|
||||
|
||||
struct clk_regmap clkr;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#include <asm/div64.h>
|
||||
|
||||
#include "clk-rcg.h"
|
||||
#include "common.h"
|
||||
|
||||
static u32 ns_to_src(struct src_sel *s, u32 ns)
|
||||
{
|
||||
|
|
@ -67,16 +68,16 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
|
|||
{
|
||||
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
|
||||
int num_parents = __clk_get_num_parents(hw->clk);
|
||||
u32 ns, ctl;
|
||||
u32 ns, reg;
|
||||
int bank;
|
||||
int i;
|
||||
struct src_sel *s;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
|
||||
bank = reg_to_bank(rcg, ctl);
|
||||
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
|
||||
bank = reg_to_bank(rcg, reg);
|
||||
s = &rcg->s[bank];
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
|
||||
ns = ns_to_src(s, ns);
|
||||
|
||||
for (i = 0; i < num_parents; i++)
|
||||
|
|
@ -192,90 +193,93 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
|
|||
|
||||
static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
|
||||
{
|
||||
u32 ns, md, ctl, *regp;
|
||||
u32 ns, md, reg;
|
||||
int bank, new_bank;
|
||||
struct mn *mn;
|
||||
struct pre_div *p;
|
||||
struct src_sel *s;
|
||||
bool enabled;
|
||||
u32 md_reg;
|
||||
u32 bank_reg;
|
||||
u32 md_reg, ns_reg;
|
||||
bool banked_mn = !!rcg->mn[1].width;
|
||||
bool banked_p = !!rcg->p[1].pre_div_width;
|
||||
struct clk_hw *hw = &rcg->clkr.hw;
|
||||
|
||||
enabled = __clk_is_enabled(hw->clk);
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
|
||||
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
|
||||
|
||||
if (banked_mn) {
|
||||
regp = &ctl;
|
||||
bank_reg = rcg->clkr.enable_reg;
|
||||
} else {
|
||||
regp = &ns;
|
||||
bank_reg = rcg->ns_reg;
|
||||
}
|
||||
|
||||
bank = reg_to_bank(rcg, *regp);
|
||||
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
|
||||
bank = reg_to_bank(rcg, reg);
|
||||
new_bank = enabled ? !bank : bank;
|
||||
|
||||
ns_reg = rcg->ns_reg[new_bank];
|
||||
regmap_read(rcg->clkr.regmap, ns_reg, &ns);
|
||||
|
||||
if (banked_mn) {
|
||||
mn = &rcg->mn[new_bank];
|
||||
md_reg = rcg->md_reg[new_bank];
|
||||
|
||||
ns |= BIT(mn->mnctr_reset_bit);
|
||||
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
|
||||
regmap_write(rcg->clkr.regmap, ns_reg, ns);
|
||||
|
||||
regmap_read(rcg->clkr.regmap, md_reg, &md);
|
||||
md = mn_to_md(mn, f->m, f->n, md);
|
||||
regmap_write(rcg->clkr.regmap, md_reg, md);
|
||||
|
||||
ns = mn_to_ns(mn, f->m, f->n, ns);
|
||||
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
|
||||
regmap_write(rcg->clkr.regmap, ns_reg, ns);
|
||||
|
||||
ctl = mn_to_reg(mn, f->m, f->n, ctl);
|
||||
regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl);
|
||||
/* Two NS registers means mode control is in NS register */
|
||||
if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
|
||||
ns = mn_to_reg(mn, f->m, f->n, ns);
|
||||
regmap_write(rcg->clkr.regmap, ns_reg, ns);
|
||||
} else {
|
||||
reg = mn_to_reg(mn, f->m, f->n, reg);
|
||||
regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
|
||||
}
|
||||
|
||||
ns &= ~BIT(mn->mnctr_reset_bit);
|
||||
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
|
||||
} else {
|
||||
regmap_write(rcg->clkr.regmap, ns_reg, ns);
|
||||
}
|
||||
|
||||
if (banked_p) {
|
||||
p = &rcg->p[new_bank];
|
||||
ns = pre_div_to_ns(p, f->pre_div - 1, ns);
|
||||
}
|
||||
|
||||
s = &rcg->s[new_bank];
|
||||
ns = src_to_ns(s, s->parent_map[f->src], ns);
|
||||
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
|
||||
regmap_write(rcg->clkr.regmap, ns_reg, ns);
|
||||
|
||||
if (enabled) {
|
||||
*regp ^= BIT(rcg->mux_sel_bit);
|
||||
regmap_write(rcg->clkr.regmap, bank_reg, *regp);
|
||||
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
|
||||
reg ^= BIT(rcg->mux_sel_bit);
|
||||
regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
|
||||
}
|
||||
}
|
||||
|
||||
static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
|
||||
u32 ns, ctl, md, reg;
|
||||
u32 ns, md, reg;
|
||||
int bank;
|
||||
struct freq_tbl f = { 0 };
|
||||
bool banked_mn = !!rcg->mn[1].width;
|
||||
bool banked_p = !!rcg->p[1].pre_div_width;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
|
||||
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl);
|
||||
reg = banked_mn ? ctl : ns;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
|
||||
bank = reg_to_bank(rcg, reg);
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
|
||||
|
||||
if (banked_mn) {
|
||||
regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
|
||||
f.m = md_to_m(&rcg->mn[bank], md);
|
||||
f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m);
|
||||
} else {
|
||||
f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
|
||||
}
|
||||
f.src = index;
|
||||
|
||||
if (banked_p)
|
||||
f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
|
||||
|
||||
f.src = index;
|
||||
configure_bank(rcg, &f);
|
||||
|
||||
return 0;
|
||||
|
|
@ -336,41 +340,30 @@ clk_dyn_rcg_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
u32 m, n, pre_div, ns, md, mode, reg;
|
||||
int bank;
|
||||
struct mn *mn;
|
||||
bool banked_p = !!rcg->p[1].pre_div_width;
|
||||
bool banked_mn = !!rcg->mn[1].width;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
|
||||
|
||||
if (banked_mn)
|
||||
regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, ®);
|
||||
else
|
||||
reg = ns;
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
|
||||
bank = reg_to_bank(rcg, reg);
|
||||
|
||||
regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
|
||||
m = n = pre_div = mode = 0;
|
||||
|
||||
if (banked_mn) {
|
||||
mn = &rcg->mn[bank];
|
||||
regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md);
|
||||
m = md_to_m(mn, md);
|
||||
n = ns_m_to_n(mn, ns, m);
|
||||
/* Two NS registers means mode control is in NS register */
|
||||
if (rcg->ns_reg[0] != rcg->ns_reg[1])
|
||||
reg = ns;
|
||||
mode = reg_to_mnctr_mode(mn, reg);
|
||||
return calc_rate(parent_rate, m, n, mode, 0);
|
||||
} else {
|
||||
pre_div = ns_to_pre_div(&rcg->p[bank], ns);
|
||||
return calc_rate(parent_rate, 0, 0, 0, pre_div);
|
||||
}
|
||||
}
|
||||
|
||||
static const
|
||||
struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
|
||||
{
|
||||
if (!f)
|
||||
return NULL;
|
||||
if (banked_p)
|
||||
pre_div = ns_to_pre_div(&rcg->p[bank], ns);
|
||||
|
||||
for (; f->freq; f++)
|
||||
if (rate <= f->freq)
|
||||
return f;
|
||||
|
||||
return NULL;
|
||||
return calc_rate(parent_rate, m, n, mode, pre_div);
|
||||
}
|
||||
|
||||
static long _freq_tbl_determine_rate(struct clk_hw *hw,
|
||||
|
|
@ -379,7 +372,7 @@ static long _freq_tbl_determine_rate(struct clk_hw *hw,
|
|||
{
|
||||
unsigned long clk_flags;
|
||||
|
||||
f = find_freq(f, rate);
|
||||
f = qcom_find_freq(f, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -477,7 +470,7 @@ static int clk_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
struct clk_rcg *rcg = to_clk_rcg(hw);
|
||||
const struct freq_tbl *f;
|
||||
|
||||
f = find_freq(rcg->freq_tbl, rate);
|
||||
f = qcom_find_freq(rcg->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -497,7 +490,7 @@ static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
|
|||
struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw);
|
||||
const struct freq_tbl *f;
|
||||
|
||||
f = find_freq(rcg->freq_tbl, rate);
|
||||
f = qcom_find_freq(rcg->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -103,8 +103,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
|
|||
* struct clk_dyn_rcg - root clock generator with glitch free mux
|
||||
*
|
||||
* @mux_sel_bit: bit to switch glitch free mux
|
||||
* @ns_reg: NS register
|
||||
* @ns_reg: NS0 and NS1 register
|
||||
* @md_reg: MD0 and MD1 register
|
||||
* @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
|
||||
* @mn: mn counter (banked)
|
||||
* @s: source selector (banked)
|
||||
* @freq_tbl: frequency table
|
||||
|
|
@ -113,8 +114,9 @@ extern const struct clk_ops clk_rcg_bypass_ops;
|
|||
*
|
||||
*/
|
||||
struct clk_dyn_rcg {
|
||||
u32 ns_reg;
|
||||
u32 ns_reg[2];
|
||||
u32 md_reg[2];
|
||||
u32 bank_reg;
|
||||
|
||||
u8 mux_sel_bit;
|
||||
|
||||
|
|
|
|||
|
|
@ -24,6 +24,7 @@
|
|||
#include <asm/div64.h>
|
||||
|
||||
#include "clk-rcg.h"
|
||||
#include "common.h"
|
||||
|
||||
#define CMD_REG 0x0
|
||||
#define CMD_UPDATE BIT(0)
|
||||
|
|
@ -172,27 +173,13 @@ clk_rcg2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
|
|||
return calc_rate(parent_rate, m, n, mode, hid_div);
|
||||
}
|
||||
|
||||
static const
|
||||
struct freq_tbl *find_freq(const struct freq_tbl *f, unsigned long rate)
|
||||
{
|
||||
if (!f)
|
||||
return NULL;
|
||||
|
||||
for (; f->freq; f++)
|
||||
if (rate <= f->freq)
|
||||
return f;
|
||||
|
||||
/* Default to our fastest rate */
|
||||
return f - 1;
|
||||
}
|
||||
|
||||
static long _freq_tbl_determine_rate(struct clk_hw *hw,
|
||||
const struct freq_tbl *f, unsigned long rate,
|
||||
unsigned long *p_rate, struct clk **p)
|
||||
{
|
||||
unsigned long clk_flags;
|
||||
|
||||
f = find_freq(f, rate);
|
||||
f = qcom_find_freq(f, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
@ -268,7 +255,7 @@ static int __clk_rcg2_set_rate(struct clk_hw *hw, unsigned long rate)
|
|||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
const struct freq_tbl *f;
|
||||
|
||||
f = find_freq(rcg->freq_tbl, rate);
|
||||
f = qcom_find_freq(rcg->freq_tbl, rate);
|
||||
if (!f)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/reset-controller.h>
|
||||
|
||||
#include "common.h"
|
||||
#include "clk-rcg.h"
|
||||
#include "clk-regmap.h"
|
||||
#include "reset.h"
|
||||
|
||||
|
|
@ -27,6 +28,21 @@ struct qcom_cc {
|
|||
struct clk *clks[];
|
||||
};
|
||||
|
||||
const
|
||||
struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
|
||||
{
|
||||
if (!f)
|
||||
return NULL;
|
||||
|
||||
for (; f->freq; f++)
|
||||
if (rate <= f->freq)
|
||||
return f;
|
||||
|
||||
/* Default to our fastest rate */
|
||||
return f - 1;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(qcom_find_freq);
|
||||
|
||||
struct regmap *
|
||||
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -18,6 +18,7 @@ struct regmap_config;
|
|||
struct clk_regmap;
|
||||
struct qcom_reset_map;
|
||||
struct regmap;
|
||||
struct freq_tbl;
|
||||
|
||||
struct qcom_cc_desc {
|
||||
const struct regmap_config *config;
|
||||
|
|
@ -27,6 +28,9 @@ struct qcom_cc_desc {
|
|||
size_t num_resets;
|
||||
};
|
||||
|
||||
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
|
||||
unsigned long rate);
|
||||
|
||||
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
|
||||
const struct qcom_cc_desc *desc);
|
||||
extern int qcom_cc_really_probe(struct platform_device *pdev,
|
||||
|
|
|
|||
|
|
@ -32,6 +32,33 @@
|
|||
#include "clk-branch.h"
|
||||
#include "reset.h"
|
||||
|
||||
static struct clk_pll pll0 = {
|
||||
.l_reg = 0x30c4,
|
||||
.m_reg = 0x30c8,
|
||||
.n_reg = 0x30cc,
|
||||
.config_reg = 0x30d4,
|
||||
.mode_reg = 0x30c0,
|
||||
.status_reg = 0x30d8,
|
||||
.status_bit = 16,
|
||||
.clkr.hw.init = &(struct clk_init_data){
|
||||
.name = "pll0",
|
||||
.parent_names = (const char *[]){ "pxo" },
|
||||
.num_parents = 1,
|
||||
.ops = &clk_pll_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_regmap pll0_vote = {
|
||||
.enable_reg = 0x34c0,
|
||||
.enable_mask = BIT(0),
|
||||
.hw.init = &(struct clk_init_data){
|
||||
.name = "pll0_vote",
|
||||
.parent_names = (const char *[]){ "pll0" },
|
||||
.num_parents = 1,
|
||||
.ops = &clk_pll_vote_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_pll pll3 = {
|
||||
.l_reg = 0x3164,
|
||||
.m_reg = 0x3168,
|
||||
|
|
@ -154,7 +181,7 @@ static const u8 gcc_pxo_pll8_pll0[] = {
|
|||
static const char *gcc_pxo_pll8_pll0_map[] = {
|
||||
"pxo",
|
||||
"pll8_vote",
|
||||
"pll0",
|
||||
"pll0_vote",
|
||||
};
|
||||
|
||||
static struct freq_tbl clk_tbl_gsbi_uart[] = {
|
||||
|
|
@ -2133,6 +2160,8 @@ static struct clk_branch usb_fs1_h_clk = {
|
|||
};
|
||||
|
||||
static struct clk_regmap *gcc_ipq806x_clks[] = {
|
||||
[PLL0] = &pll0.clkr,
|
||||
[PLL0_VOTE] = &pll0_vote,
|
||||
[PLL3] = &pll3.clkr,
|
||||
[PLL8] = &pll8.clkr,
|
||||
[PLL8_VOTE] = &pll8_vote,
|
||||
|
|
|
|||
|
|
@ -773,9 +773,11 @@ static struct freq_tbl clk_tbl_gfx2d[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg gfx2d0_src = {
|
||||
.ns_reg = 0x0070,
|
||||
.ns_reg[0] = 0x0070,
|
||||
.ns_reg[1] = 0x0070,
|
||||
.md_reg[0] = 0x0064,
|
||||
.md_reg[1] = 0x0068,
|
||||
.bank_reg = 0x0060,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 25,
|
||||
|
|
@ -831,9 +833,11 @@ static struct clk_branch gfx2d0_clk = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg gfx2d1_src = {
|
||||
.ns_reg = 0x007c,
|
||||
.ns_reg[0] = 0x007c,
|
||||
.ns_reg[1] = 0x007c,
|
||||
.md_reg[0] = 0x0078,
|
||||
.md_reg[1] = 0x006c,
|
||||
.bank_reg = 0x0074,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 25,
|
||||
|
|
@ -930,9 +934,11 @@ static struct freq_tbl clk_tbl_gfx3d_8064[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg gfx3d_src = {
|
||||
.ns_reg = 0x008c,
|
||||
.ns_reg[0] = 0x008c,
|
||||
.ns_reg[1] = 0x008c,
|
||||
.md_reg[0] = 0x0084,
|
||||
.md_reg[1] = 0x0088,
|
||||
.bank_reg = 0x0080,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 25,
|
||||
|
|
@ -1006,9 +1012,11 @@ static struct freq_tbl clk_tbl_vcap[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg vcap_src = {
|
||||
.ns_reg = 0x021c,
|
||||
.ns_reg[0] = 0x021c,
|
||||
.ns_reg[1] = 0x021c,
|
||||
.md_reg[0] = 0x01ec,
|
||||
.md_reg[1] = 0x0218,
|
||||
.bank_reg = 0x0178,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 23,
|
||||
|
|
@ -1211,9 +1219,11 @@ static struct freq_tbl clk_tbl_mdp[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg mdp_src = {
|
||||
.ns_reg = 0x00d0,
|
||||
.ns_reg[0] = 0x00d0,
|
||||
.ns_reg[1] = 0x00d0,
|
||||
.md_reg[0] = 0x00c4,
|
||||
.md_reg[1] = 0x00c8,
|
||||
.bank_reg = 0x00c0,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 8,
|
||||
.mnctr_reset_bit = 31,
|
||||
|
|
@ -1318,7 +1328,9 @@ static struct freq_tbl clk_tbl_rot[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg rot_src = {
|
||||
.ns_reg = 0x00e8,
|
||||
.ns_reg[0] = 0x00e8,
|
||||
.ns_reg[1] = 0x00e8,
|
||||
.bank_reg = 0x00e8,
|
||||
.p[0] = {
|
||||
.pre_div_shift = 22,
|
||||
.pre_div_width = 4,
|
||||
|
|
@ -1542,9 +1554,11 @@ static struct freq_tbl clk_tbl_vcodec[] = {
|
|||
};
|
||||
|
||||
static struct clk_dyn_rcg vcodec_src = {
|
||||
.ns_reg = 0x0100,
|
||||
.ns_reg[0] = 0x0100,
|
||||
.ns_reg[1] = 0x0100,
|
||||
.md_reg[0] = 0x00fc,
|
||||
.md_reg[1] = 0x0128,
|
||||
.bank_reg = 0x00f8,
|
||||
.mn[0] = {
|
||||
.mnctr_en_bit = 5,
|
||||
.mnctr_reset_bit = 31,
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user