forked from luck/tmp_suning_uos_patched
[SCSI] qla2xxx: Correct additional posting issues during NVRAM accesses.
On MMIO relaxed-order platforms, it is possible for the proper delay during NVRAM access to begin before the request passes through the PCI bus (via a MMIO write) to the ISP. Thus, causing a subsequent read to the NVRAM part to fail. Add a MMIO read, after the MMIO write to insure any posted writes are flushed. Signed-off-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
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@ -126,6 +126,7 @@ qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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@ -178,6 +179,7 @@ qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
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/* Wait for NVRAM to become ready */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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@ -235,6 +237,7 @@ qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
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/* Read data from NVRAM. */
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for (cnt = 0; cnt < 16; cnt++) {
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WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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NVRAM_DELAY();
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data <<= 1;
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reg_data = RD_REG_WORD(®->nvram);
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@ -337,6 +340,7 @@ qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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@ -388,6 +392,7 @@ qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
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/* Wait for NVRAM to become ready. */
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WRT_REG_WORD(®->nvram, NVR_SELECT);
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RD_REG_WORD(®->nvram); /* PCI Posting. */
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do {
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NVRAM_DELAY();
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word = RD_REG_WORD(®->nvram);
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