From 228f1e6ab55f60f8cb3208dffc118afa6514b6af Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 3 Aug 2020 17:44:30 +0200 Subject: [PATCH 01/12] arm64: tegra: Add ID EEPROMs on Jetson AGX Xavier The P2888 processor module contains an EEPROM that provides means of identifying the module. The P2822 carrier board contains the same EEPROM with information identifying the carrier board. Both of them ar accessed via the GEN_I2C1 bus. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 15 +++++++++++++++ .../arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 13 +++++++++++++ 2 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 4c005b811233..0ea0bd83cb8e 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -57,6 +57,21 @@ serial@3110000 { status = "okay"; }; + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + /* SDMMC1 (SD/MMC) */ mmc@3400000 { cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 90b6ea5467fa..4d8a0e10250f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -23,6 +23,19 @@ interrupt-controller@2a40000 { }; }; + i2c@3160000 { + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + ddc: i2c@31c0000 { status = "okay"; }; From a41315610bab6f152280975500f33e3b069e10ff Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:08 +0200 Subject: [PATCH 02/12] arm64: tegra: Wire up pinctrl states for all DPAUX controllers All four DPAUX controllers on Tegra194 control the pin configuration of their companion I2C controllers. Wire up all the pinctrl states for the I2C controllers so that their pins can be correctly muxed when needed. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 48160f48003a..466872a4512f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -329,6 +329,9 @@ dp_aux_ch1_i2c: i2c@3190000 { clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C4>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux1_i2c>; + pinctrl-1 = <&state_dpaux1_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; @@ -343,10 +346,14 @@ dp_aux_ch0_i2c: i2c@31b0000 { clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C6>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux0_i2c>; + pinctrl-1 = <&state_dpaux0_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; - gen7_i2c: i2c@31c0000 { + /* shares pads with dpaux2 */ + dp_aux_ch2_i2c: i2c@31c0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x031c0000 0x10000>; interrupts = ; @@ -356,10 +363,14 @@ gen7_i2c: i2c@31c0000 { clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C7>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux2_i2c>; + pinctrl-1 = <&state_dpaux2_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; - gen9_i2c: i2c@31e0000 { + /* shares pads with dpaux3 */ + dp_aux_ch3_i2c: i2c@31e0000 { compatible = "nvidia,tegra194-i2c"; reg = <0x031e0000 0x10000>; interrupts = ; @@ -369,6 +380,9 @@ gen9_i2c: i2c@31e0000 { clock-names = "div-clk"; resets = <&bpmp TEGRA194_RESET_I2C9>; reset-names = "i2c"; + pinctrl-0 = <&state_dpaux3_i2c>; + pinctrl-1 = <&state_dpaux3_off>; + pinctrl-names = "default", "idle"; status = "disabled"; }; From 78bc57ffa809222ff56c05181afe38fea1068ad8 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:09 +0200 Subject: [PATCH 03/12] arm64: tegra: Add VBUS supply for micro USB port on Jetson Nano The VBUS supply for the micro USB port on Jetson Nano is derived from the main system supply and always on. Describe in nevertheless to fix warnings during boot. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 2282ea1c6279..b8d1fa72e177 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -541,6 +541,8 @@ usb2-0 { mode = "peripheral"; usb-role-switch; + vbus-supply = <&vdd_5v0_usb>; + connector { compatible = "gpio-usb-b-connector", "usb-b-connector"; @@ -843,4 +845,14 @@ avdd_io_edp_1v05: regulator@7 { vin-supply = <&avdd_1v05_pll>; }; + + vdd_5v0_usb: regulator@8 { + compatible = "regulator-fixed"; + + regulator-name = "VDD_5V_USB"; + regulator-min-microvolt = <50000000>; + regulator-max-microvolt = <50000000>; + + vin-supply = <&vdd_5v0_sys>; + }; }; From da415b71cd4fe0f02dbe7c044392e74c6d091e26 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:10 +0200 Subject: [PATCH 04/12] arm64: tegra: Disable SD card write-protection on Jetson Nano There is no GPIO hooked up to the write-protection pin of the SD slot. Make sure to describe this properly in device tree to avoid errors or warnings being emitted by the operating system. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index b8d1fa72e177..553a5585edac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -576,6 +576,7 @@ mmc@700b0000 { bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>; + disable-wp; vqmmc-supply = <&vddio_sdmmc>; vmmc-supply = <&vdd_3v3_sd>; From 0cc6ba3ce87c2845689599a87ee993d1aec9ca89 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:41:11 +0200 Subject: [PATCH 05/12] arm64: tegra: Describe display controller outputs for Tegra210 Both display controllers can drive both DSI and both SOR outputs on Tegra210. Describe this in device tree so that the operating system doesn't have to guess. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 829f786af133..27d4e3f134ca 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -194,6 +194,7 @@ dc@54200000 { iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <0>; }; @@ -208,10 +209,11 @@ dc@54240000 { iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,outputs = <&dsia &dsib &sor0 &sor1>; nvidia,head = <1>; }; - dsi@54300000 { + dsia: dsi@54300000 { compatible = "nvidia,tegra210-dsi"; reg = <0x0 0x54300000 0x0 0x00040000>; clocks = <&tegra_car TEGRA210_CLK_DSIA>, @@ -248,7 +250,7 @@ nvjpg@54380000 { status = "disabled"; }; - dsi@54400000 { + dsib: dsi@54400000 { compatible = "nvidia,tegra210-dsi"; reg = <0x0 0x54400000 0x0 0x00040000>; clocks = <&tegra_car TEGRA210_CLK_DSIB>, @@ -284,7 +286,7 @@ tsec@54500000 { status = "disabled"; }; - sor@54540000 { + sor0: sor@54540000 { compatible = "nvidia,tegra210-sor"; reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = ; @@ -304,7 +306,7 @@ sor@54540000 { status = "disabled"; }; - sor@54580000 { + sor1: sor@54580000 { compatible = "nvidia,tegra210-sor1"; reg = <0x0 0x54580000 0x0 0x00040000>; interrupts = ; From 562da8b494c4e2f72d0789a03e6ccd9dc14d3f25 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 6 Aug 2020 17:42:45 +0200 Subject: [PATCH 06/12] arm64: tegra: Use valid PWM period for VDD_GPU on Tegra210 The PWM on Tegra210 can run at a maximum frequency of 48 MHz and cannot reach the minimum period is 5334 ns. The currently configured period of 4880 ns is not within the valid range, so set it to 8000 ns. This value was taken from the downstream DTS files and seems to work fine. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 6a4b50aaa25d..85ee7e6b71ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -337,7 +337,7 @@ psci { vdd_gpu: regulator@100 { compatible = "pwm-regulator"; - pwms = <&pwm 1 4880>; + pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; regulator-min-microvolt = <710000>; regulator-max-microvolt = <1320000>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 553a5585edac..c55716c336c1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -821,7 +821,7 @@ vdd_cpu: regulator@5 { vdd_gpu: regulator@6 { compatible = "pwm-regulator"; - pwms = <&pwm 1 4880>; + pwms = <&pwm 1 8000>; regulator-name = "VDD_GPU"; regulator-min-microvolt = <710000>; From 818ae79a50da560c645e022170bed8401eea452e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Tue, 21 Jul 2020 17:10:55 +0200 Subject: [PATCH 07/12] arm64: tegra: Properly size register regions for GPU on Tegra194 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Memory I/O regions for the GV11B found on Tegra194 are 16 MiB rather than 256 MiB. Reported-by: Terje Bergström Signed-off-by: Thierry Reding Reviewed-By: Terje Bergström Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 466872a4512f..421b9e0883d9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1412,8 +1412,8 @@ sor3: sor@15bc0000 { gpu@17000000 { compatible = "nvidia,gv11b"; - reg = <0x17000000 0x10000000>, - <0x18000000 0x10000000>; + reg = <0x17000000 0x1000000>, + <0x18000000 0x1000000>; interrupts = , ; interrupt-names = "stall", "nonstall"; From 547141b56c6cdc34727917d4ddd315321640f6df Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Sun, 19 Jul 2020 10:31:29 +0530 Subject: [PATCH 08/12] arm64: tegra: Enable ACONNECT, ADMA and AGIC on Jetson Nano These devices are required for audio sub system and current patch ensures probe path of these devices gets tested. Later sound card support would be added which can use these devices at runtime. Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index c55716c336c1..ba892cd4b5a9 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -624,6 +624,18 @@ clock@70110000 { pinctrl-1 = <&dvfs_pwm_inactive_state>; }; + aconnect@702c0000 { + status = "okay"; + + dma@702e2000 { + status = "okay"; + }; + + interrupt-controller@702f9000 { + status = "okay"; + }; + }; + clk32k_in: clock@0 { compatible = "fixed-clock"; clock-frequency = <32768>; From 177208f7b06d1669514cc465268c8432f577b7fd Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Sun, 19 Jul 2020 10:31:30 +0530 Subject: [PATCH 09/12] arm64: tegra: Add DT binding for AHUB components This patch adds few AHUB modules for Tegra210, Tegra186 and Tegra194. Bindings for following modules are added. * AHUB added as a child node under ACONNECT * AHUB includes many HW accelerators and below components are added as its children. * ADMAIF * I2S * DMIC * DSPK (added for Tegra186 and Tegra194 only, since Tegra210 does not have this module) Signed-off-by: Sameer Pujar Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 217 +++++++++++++++++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 225 ++++++++++++++++++++++- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 140 ++++++++++++++ 3 files changed, 580 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 34d249d85da7..7869aeccee1a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -85,7 +85,7 @@ aconnect { ranges = <0x02900000 0x0 0x02900000 0x200000>; status = "disabled"; - dma-controller@2930000 { + adma: dma-controller@2930000 { compatible = "nvidia,tegra186-adma"; reg = <0x02930000 0x20000>; interrupt-parent = <&agic>; @@ -140,6 +140,221 @@ agic: interrupt-controller@2a40000 { clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra186-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA186_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S1>, + <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S2>, + <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S3>, + <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S4>, + <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S5>, + <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra186-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA186_CLK_I2S6>, + <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA186_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA186_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA186_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + }; }; mc: memory-controller@2c00000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 421b9e0883d9..311c1c86d9b1 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -83,7 +83,7 @@ aconnect@2900000 { ranges = <0x02900000 0x02900000 0x200000>; status = "disabled"; - dma-controller@2930000 { + adma: dma-controller@2930000 { compatible = "nvidia,tegra194-adma", "nvidia,tegra186-adma"; reg = <0x02930000 0x20000>; @@ -140,6 +140,229 @@ agic: interrupt-controller@2a40000 { clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@2900800 { + compatible = "nvidia,tegra194-ahub", + "nvidia,tegra186-ahub"; + reg = <0x02900800 0x800>; + clocks = <&bpmp TEGRA194_CLK_AHUB>; + clock-names = "ahub"; + assigned-clocks = <&bpmp TEGRA194_CLK_AHUB>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900800 0x02900800 0x11800>; + status = "disabled"; + + tegra_admaif: admaif@290f000 { + compatible = "nvidia,tegra194-admaif", + "nvidia,tegra186-admaif"; + reg = <0x0290f000 0x1000>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20"; + status = "disabled"; + }; + + tegra_i2s1: i2s@2901000 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901000 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S1>, + <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@2901100 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901100 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S2>, + <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@2901200 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901200 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S3>, + <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@2901300 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901300 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S4>, + <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@2901400 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901400 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S5>, + <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S5>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_i2s6: i2s@2901500 { + compatible = "nvidia,tegra194-i2s", + "nvidia,tegra210-i2s"; + reg = <0x2901500 0x100>; + clocks = <&bpmp TEGRA194_CLK_I2S6>, + <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&bpmp TEGRA194_CLK_I2S6>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S6"; + status = "disabled"; + }; + + tegra_dmic1: dmic@2904000 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904000 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@2904100 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904100 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@2904200 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904200 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + + tegra_dmic4: dmic@2904300 { + compatible = "nvidia,tegra194-dmic", + "nvidia,tegra210-dmic"; + reg = <0x2904300 0x100>; + clocks = <&bpmp TEGRA194_CLK_DMIC4>; + clock-names = "dmic"; + assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC4"; + status = "disabled"; + }; + + tegra_dspk1: dspk@2905000 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905000 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK1>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK1"; + status = "disabled"; + }; + + tegra_dspk2: dspk@2905100 { + compatible = "nvidia,tegra194-dspk", + "nvidia,tegra186-dspk"; + reg = <0x2905100 0x100>; + clocks = <&bpmp TEGRA194_CLK_DSPK2>; + clock-names = "dspk"; + assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; + assigned-clock-parents = <&bpmp TEGRA194_CLK_PLLA_OUT0>; + assigned-clock-rates = <12288000>; + sound-name-prefix = "DSPK2"; + status = "disabled"; + }; + }; }; pinmux: pinmux@2430000 { diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 27d4e3f134ca..0b288308ef8b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1383,6 +1383,146 @@ agic: interrupt-controller@702f9000 { clock-names = "clk"; status = "disabled"; }; + + tegra_ahub: ahub@702d0800 { + compatible = "nvidia,tegra210-ahub"; + reg = <0x702d0800 0x800>; + clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + clock-names = "ahub"; + assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x702d0000 0x702d0000 0x0000e400>; + status = "disabled"; + + tegra_admaif: admaif@702d0000 { + compatible = "nvidia,tegra210-admaif"; + reg = <0x702d0000 0x800>; + dmas = <&adma 1>, <&adma 1>, + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>; + dma-names = "rx1", "tx1", + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10"; + status = "disabled"; + }; + + tegra_i2s1: i2s@702d1000 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S0>, + <&tegra_car TEGRA210_CLK_I2S0_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S1"; + status = "disabled"; + }; + + tegra_i2s2: i2s@702d1100 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S1>, + <&tegra_car TEGRA210_CLK_I2S1_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S2"; + status = "disabled"; + }; + + tegra_i2s3: i2s@702d1200 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S2>, + <&tegra_car TEGRA210_CLK_I2S2_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S3"; + status = "disabled"; + }; + + tegra_i2s4: i2s@702d1300 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1300 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S3>, + <&tegra_car TEGRA210_CLK_I2S3_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S4"; + status = "disabled"; + }; + + tegra_i2s5: i2s@702d1400 { + compatible = "nvidia,tegra210-i2s"; + reg = <0x702d1400 0x100>; + clocks = <&tegra_car TEGRA210_CLK_I2S4>, + <&tegra_car TEGRA210_CLK_I2S4_SYNC>; + clock-names = "i2s", "sync_input"; + assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <1536000>; + sound-name-prefix = "I2S5"; + status = "disabled"; + }; + + tegra_dmic1: dmic@702d4000 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4000 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC1"; + status = "disabled"; + }; + + tegra_dmic2: dmic@702d4100 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4100 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC2"; + status = "disabled"; + }; + + tegra_dmic3: dmic@702d4200 { + compatible = "nvidia,tegra210-dmic"; + reg = <0x702d4200 0x100>; + clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + clock-names = "dmic"; + assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; + assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; + assigned-clock-rates = <3072000>; + sound-name-prefix = "DMIC3"; + status = "disabled"; + }; + }; }; spi@70410000 { From a4387f2973a0562c9432e79f3b7eb33de59ee045 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 16 Sep 2020 10:49:51 +0100 Subject: [PATCH 10/12] arm64: tegra: Add label properties for EEPROMs Populate the label property for the AT24 EEPROMs on the various Jetson platforms. Note that the name 'module' is used to identify the EEPROM on the processor module board and the name 'system' is used to identify the EEPROM on the main base board (which is sometimes referred to as the carrier board). Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 1 + arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 1 + arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 1 + arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts | 1 + arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 ++ 7 files changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index 802b8c52489a..381a84912ba8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -222,6 +222,7 @@ eeprom@57 { compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 53d92fdd7f06..fd9177447711 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -173,6 +173,7 @@ eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index 0ea0bd83cb8e..d71b7a1140fe 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -64,6 +64,7 @@ eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8ls>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 4d8a0e10250f..54d057beec59 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -28,6 +28,7 @@ eeprom@56 { compatible = "atmel,24c02"; reg = <0x56>; + label = "system"; vcc-supply = <&vdd_1v8ls>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 85ee7e6b71ac..6077d572d828 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -273,6 +273,7 @@ eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts index 56adf287a82c..4c9c2a054642 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2371-2180.dts @@ -86,6 +86,7 @@ eeprom@57 { compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index ba892cd4b5a9..859241db4b4d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -144,6 +144,7 @@ eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; + label = "module"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; @@ -155,6 +156,7 @@ eeprom@57 { compatible = "atmel,24c02"; reg = <0x57>; + label = "system"; vcc-supply = <&vdd_1v8>; address-width = <8>; pagesize = <8>; From 2b9ee384b450d4b8b7a44806f382e43f61a47a4c Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 16 Sep 2020 10:49:52 +0100 Subject: [PATCH 11/12] arm64: tegra: Populate EEPROMs for Jetson Xavier NX Populate the EEPROMs that are present on the Jetson Xavier NX developer platform. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- .../nvidia/tegra194-p3509-0000+p3668-0000.dts | 14 ++++++++++++++ .../boot/dts/nvidia/tegra194-p3668-0000.dtsi | 16 ++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts index c1c589805d6b..7f97b34216a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000+p3668-0000.dts @@ -27,6 +27,20 @@ ddc: i2c@3190000 { status = "okay"; }; + i2c@3160000 { + eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + + label = "system"; + vcc-supply = <&vdd_1v8>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + hda@3510000 { nvidia,model = "jetson-xavier-nx-hda"; status = "okay"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi index 10cb836aea7e..a2893be80507 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3668-0000.dtsi @@ -58,6 +58,22 @@ serial@c280000 { status = "okay"; }; + i2c@3160000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + label = "module"; + vcc-supply = <&vdd_1v8ls>; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + /* SDMMC1 (SD/MMC) */ mmc@3400000 { status = "okay"; From 639448912ba17a9af9e759efbab37d36c6e29dea Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 17 Sep 2020 12:07:52 +0200 Subject: [PATCH 12/12] arm64: tegra: Initial Tegra234 VDK support The NVIDIA Tegra234 VDK is a simulation platform for the Orin SoC. It supports a subset of the peripherals that will be available in the final chip and serves as a bootstrapping platform. Reviewed-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/Makefile | 1 + .../boot/dts/nvidia/tegra234-sim-vdk.dts | 40 ++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 189 ++++++++++++++++++ drivers/soc/tegra/Kconfig | 10 + include/dt-bindings/clock/tegra234-clock.h | 14 ++ include/dt-bindings/reset/tegra234-reset.h | 10 + 6 files changed, 264 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts create mode 100644 arch/arm64/boot/dts/nvidia/tegra234.dtsi create mode 100644 include/dt-bindings/clock/tegra234-clock.h create mode 100644 include/dt-bindings/reset/tegra234-reset.h diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 2273fc5db19c..9296d12d11e9 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2894-0050-a08.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p3509-0000+p3668-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-sim-vdk.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts new file mode 100644 index 000000000000..f6e6a24829af --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234-sim-vdk.dts @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra234.dtsi" + +/ { + model = "NVIDIA Tegra234 VDK"; + compatible = "nvidia,tegra234-vdk", "nvidia,tegra234"; + + aliases { + sdhci3 = "/cbb@0/sdhci@3460000"; + serial0 = &uarta; + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlycon=uart8250,mmio32,0x03100000"; + stdout-path = "serial0:115200n8"; + }; + + cbb@0 { + serial@3100000 { + status = "okay"; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + only-1-8-v; + }; + + rtc@c2a0000 { + status = "okay"; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi new file mode 100644 index 000000000000..f0efb3a62804 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include +#include +#include +#include + +/ { + compatible = "nvidia,tegra234"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + bus@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0x0 0x0 0x0 0x40000000>; + + misc@100000 { + compatible = "nvidia,tegra234-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + status = "okay"; + }; + + uarta: serial@3100000 { + compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart"; + reg = <0x03100000 0x10000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_UARTA>; + clock-names = "serial"; + resets = <&bpmp TEGRA234_RESET_UARTA>; + reset-names = "serial"; + status = "disabled"; + }; + + mmc@3460000 { + compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; + reg = <0x03460000 0x20000>; + interrupts = ; + clocks = <&bpmp TEGRA234_CLK_SDMMC4>; + clock-names = "sdhci"; + resets = <&bpmp TEGRA234_RESET_SDMMC4>; + reset-names = "sdhci"; + dma-coherent; + status = "disabled"; + }; + + fuse@3810000 { + compatible = "nvidia,tegra234-efuse"; + reg = <0x03810000 0x10000>; + clocks = <&bpmp TEGRA234_CLK_FUSE>; + clock-names = "fuse"; + }; + + hsp_top0: hsp@3c00000 { + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; + reg = <0x03c00000 0xa0000>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "doorbell", "shared0", "shared1", "shared2", + "shared3", "shared4", "shared5", "shared6", + "shared7"; + #mbox-cells = <2>; + }; + + hsp_aon: hsp@c150000 { + compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp"; + reg = <0x0c150000 0x90000>; + interrupts = , + , + , + ; + /* + * Shared interrupt 0 is routed only to AON/SPE, so + * we only have 4 shared interrupts for the CCPLEX. + */ + interrupt-names = "shared1", "shared2", "shared3", "shared4"; + #mbox-cells = <2>; + }; + + rtc@c2a0000 { + compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc"; + reg = <0x0c2a0000 0x10000>; + interrupt-parent = <&pmc>; + interrupts = <73 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + pmc: pmc@c360000 { + compatible = "nvidia,tegra234-pmc"; + reg = <0x0c360000 0x10000>, + <0x0c370000 0x10000>, + <0x0c380000 0x10000>, + <0x0c390000 0x10000>, + <0x0c3a0000 0x10000>; + reg-names = "pmc", "wake", "aotag", "scratch", "misc"; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + gic: interrupt-controller@f400000 { + compatible = "arm,gic-v3"; + reg = <0x0f400000 0x010000>, /* GICD */ + <0x0f440000 0x200000>; /* GICR */ + interrupt-parent = <&gic>; + interrupts = ; + + #redistributor-regions = <1>; + #interrupt-cells = <3>; + interrupt-controller; + }; + }; + + sysram@40000000 { + compatible = "nvidia,tegra234-sysram", "mmio-sram"; + reg = <0x0 0x40000000 0x0 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x40000000 0x50000>; + + cpu_bpmp_tx: shmem@4e000 { + reg = <0x4e000 0x1000>; + label = "cpu-bpmp-tx"; + pool; + }; + + cpu_bpmp_rx: shmem@4f000 { + reg = <0x4f000 0x1000>; + label = "cpu-bpmp-rx"; + pool; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp"; + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + reg = <0x000>; + + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + status = "okay"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + interrupt-parent = <&gic>; + always-on; + }; +}; diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index 6bc603d0b9d9..976dee036470 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -119,6 +119,16 @@ config ARCH_TEGRA_194_SOC help Enable support for the NVIDIA Tegra194 SoC. +config ARCH_TEGRA_234_SOC + bool "NVIDIA Tegra234 SoC" + select MAILBOX + select TEGRA_BPMP + select TEGRA_HSP_MBOX + select TEGRA_IVC + select SOC_TEGRA_PMC + help + Enable support for the NVIDIA Tegra234 SoC. + endif endif diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h new file mode 100644 index 000000000000..2c82072950ee --- /dev/null +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H +#define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H + +/** @brief output of gate CLK_ENB_FUSE */ +#define TEGRA234_CLK_FUSE 40 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ +#define TEGRA234_CLK_SDMMC4 123 +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ +#define TEGRA234_CLK_UARTA 155 + +#endif diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h new file mode 100644 index 000000000000..b3c63be06d2d --- /dev/null +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_RESET_TEGRA234_RESET_H +#define DT_BINDINGS_RESET_TEGRA234_RESET_H + +#define TEGRA234_RESET_SDMMC4 85 +#define TEGRA234_RESET_UARTA 100 + +#endif