forked from luck/tmp_suning_uos_patched
[PATCH] powermac pci iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
This commit is contained in:
parent
24954a1418
commit
de125bf395
@ -136,14 +136,14 @@ static void __init fixup_bus_range(struct device_node *bridge)
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|(((unsigned int)(off)) & 0xFCUL) \
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|(((unsigned int)(off)) & 0xFCUL) \
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|1UL)
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|1UL)
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static unsigned long macrisc_cfg_access(struct pci_controller* hose,
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static volatile void __iomem *macrisc_cfg_access(struct pci_controller* hose,
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u8 bus, u8 dev_fn, u8 offset)
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u8 bus, u8 dev_fn, u8 offset)
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{
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{
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unsigned int caddr;
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unsigned int caddr;
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if (bus == hose->first_busno) {
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if (bus == hose->first_busno) {
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if (dev_fn < (11 << 3))
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if (dev_fn < (11 << 3))
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return 0;
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return NULL;
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caddr = MACRISC_CFA0(dev_fn, offset);
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caddr = MACRISC_CFA0(dev_fn, offset);
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} else
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} else
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caddr = MACRISC_CFA1(bus, dev_fn, offset);
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caddr = MACRISC_CFA1(bus, dev_fn, offset);
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@ -154,14 +154,14 @@ static unsigned long macrisc_cfg_access(struct pci_controller* hose,
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} while (in_le32(hose->cfg_addr) != caddr);
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} while (in_le32(hose->cfg_addr) != caddr);
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offset &= has_uninorth ? 0x07 : 0x03;
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offset &= has_uninorth ? 0x07 : 0x03;
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return ((unsigned long)hose->cfg_data) + offset;
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return hose->cfg_data + offset;
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}
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}
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static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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int offset, int len, u32 *val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -177,13 +177,13 @@ static int macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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*val = in_8((u8 *)addr);
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*val = in_8(addr);
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break;
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break;
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case 2:
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case 2:
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*val = in_le16((u16 *)addr);
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*val = in_le16(addr);
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break;
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break;
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default:
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default:
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*val = in_le32((u32 *)addr);
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*val = in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -193,7 +193,7 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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int offset, int len, u32 val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -209,16 +209,16 @@ static int macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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out_8((u8 *)addr, val);
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out_8(addr, val);
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(void) in_8((u8 *)addr);
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(void) in_8(addr);
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break;
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break;
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case 2:
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case 2:
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out_le16((u16 *)addr, val);
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out_le16(addr, val);
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(void) in_le16((u16 *)addr);
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(void) in_le16(addr);
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break;
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break;
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default:
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default:
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out_le32((u32 *)addr, val);
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out_le32(addr, val);
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(void) in_le32((u32 *)addr);
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(void) in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -348,25 +348,23 @@ static int u3_ht_skip_device(struct pci_controller *hose,
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+ (((unsigned int)bus) << 16) \
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+ (((unsigned int)bus) << 16) \
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+ 0x01000000UL)
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+ 0x01000000UL)
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static unsigned long u3_ht_cfg_access(struct pci_controller* hose,
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static volatile void __iomem *u3_ht_cfg_access(struct pci_controller* hose,
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u8 bus, u8 devfn, u8 offset)
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u8 bus, u8 devfn, u8 offset)
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{
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{
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if (bus == hose->first_busno) {
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if (bus == hose->first_busno) {
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/* For now, we don't self probe U3 HT bridge */
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/* For now, we don't self probe U3 HT bridge */
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if (PCI_SLOT(devfn) == 0)
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if (PCI_SLOT(devfn) == 0)
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return 0;
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return NULL;
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return ((unsigned long)hose->cfg_data) +
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return hose->cfg_data + U3_HT_CFA0(devfn, offset);
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U3_HT_CFA0(devfn, offset);
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} else
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} else
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return ((unsigned long)hose->cfg_data) +
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return hose->cfg_data + U3_HT_CFA1(bus, devfn, offset);
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U3_HT_CFA1(bus, devfn, offset);
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}
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}
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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int offset, int len, u32 *val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -400,13 +398,13 @@ static int u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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*val = in_8((u8 *)addr);
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*val = in_8(addr);
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break;
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break;
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case 2:
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case 2:
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*val = in_le16((u16 *)addr);
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*val = in_le16(addr);
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break;
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break;
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default:
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default:
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*val = in_le32((u32 *)addr);
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*val = in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -416,7 +414,7 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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int offset, int len, u32 val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -442,16 +440,16 @@ static int u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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out_8((u8 *)addr, val);
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out_8(addr, val);
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(void) in_8((u8 *)addr);
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(void) in_8(addr);
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break;
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break;
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case 2:
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case 2:
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out_le16((u16 *)addr, val);
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out_le16(addr, val);
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(void) in_le16((u16 *)addr);
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(void) in_le16(addr);
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break;
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break;
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default:
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default:
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out_le32((u32 *)addr, val);
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out_le32((u32 __iomem *)addr, val);
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(void) in_le32((u32 *)addr);
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(void) in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -476,7 +474,7 @@ static struct pci_ops u3_ht_pci_ops =
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|(((unsigned int)(off)) & 0xfcU) \
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|(((unsigned int)(off)) & 0xfcU) \
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|1UL)
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|1UL)
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static unsigned long u4_pcie_cfg_access(struct pci_controller* hose,
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static volatile void __iomem *u4_pcie_cfg_access(struct pci_controller* hose,
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u8 bus, u8 dev_fn, int offset)
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u8 bus, u8 dev_fn, int offset)
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{
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{
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unsigned int caddr;
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unsigned int caddr;
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@ -492,14 +490,14 @@ static unsigned long u4_pcie_cfg_access(struct pci_controller* hose,
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} while (in_le32(hose->cfg_addr) != caddr);
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} while (in_le32(hose->cfg_addr) != caddr);
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offset &= 0x03;
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offset &= 0x03;
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return ((unsigned long)hose->cfg_data) + offset;
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return hose->cfg_data + offset;
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}
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}
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static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val)
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int offset, int len, u32 *val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -515,13 +513,13 @@ static int u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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*val = in_8((u8 *)addr);
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*val = in_8(addr);
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break;
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break;
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case 2:
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case 2:
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*val = in_le16((u16 *)addr);
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*val = in_le16(addr);
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break;
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break;
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default:
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default:
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*val = in_le32((u32 *)addr);
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*val = in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -531,7 +529,7 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val)
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int offset, int len, u32 val)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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unsigned long addr;
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volatile void __iomem *addr;
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hose = pci_bus_to_host(bus);
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hose = pci_bus_to_host(bus);
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if (hose == NULL)
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if (hose == NULL)
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@ -547,16 +545,16 @@ static int u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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*/
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*/
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switch (len) {
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switch (len) {
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case 1:
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case 1:
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out_8((u8 *)addr, val);
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out_8(addr, val);
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(void) in_8((u8 *)addr);
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(void) in_8(addr);
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break;
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break;
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case 2:
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case 2:
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out_le16((u16 *)addr, val);
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out_le16(addr, val);
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(void) in_le16((u16 *)addr);
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(void) in_le16(addr);
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break;
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break;
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default:
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default:
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out_le32((u32 *)addr, val);
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out_le32(addr, val);
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(void) in_le32((u32 *)addr);
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(void) in_le32(addr);
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break;
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break;
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}
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}
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return PCIBIOS_SUCCESSFUL;
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return PCIBIOS_SUCCESSFUL;
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@ -773,8 +771,7 @@ static void __init setup_u3_ht(struct pci_controller* hose)
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* the reg address cell, we shall fix that by killing struct
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* the reg address cell, we shall fix that by killing struct
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* reg_property and using some accessor functions instead
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* reg_property and using some accessor functions instead
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*/
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*/
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hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000,
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hose->cfg_data = ioremap(0xf2000000, 0x02000000);
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0x02000000);
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/*
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/*
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* /ht node doesn't expose a "ranges" property, so we "remove"
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* /ht node doesn't expose a "ranges" property, so we "remove"
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